1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __CI_DPM_H__
24#define __CI_DPM_H__
25
26#include "ppsmc.h"
27
28#define SMU__NUM_SCLK_DPM_STATE 8
29#define SMU__NUM_MCLK_DPM_LEVELS 6
30#define SMU__NUM_LCLK_DPM_LEVELS 8
31#define SMU__NUM_PCIE_DPM_LEVELS 8
32#include "smu7_discrete.h"
33
34#define CISLANDS_MAX_HARDWARE_POWERLEVELS 2
35
36#define CISLANDS_UNUSED_GPIO_PIN 0x7F
37
38struct ci_pl {
39 u32 mclk;
40 u32 sclk;
41 enum radeon_pcie_gen pcie_gen;
42 u16 pcie_lane;
43};
44
45struct ci_ps {
46 u16 performance_level_count;
47 bool dc_compatible;
48 u32 sclk_t;
49 struct ci_pl performance_levels[CISLANDS_MAX_HARDWARE_POWERLEVELS];
50};
51
52struct ci_dpm_level {
53 bool enabled;
54 u32 value;
55 u32 param1;
56};
57
58#define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5
59#define MAX_REGULAR_DPM_NUMBER 8
60#define CISLAND_MINIMUM_ENGINE_CLOCK 800
61
62struct ci_single_dpm_table {
63 u32 count;
64 struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
65};
66
67struct ci_dpm_table {
68 struct ci_single_dpm_table sclk_table;
69 struct ci_single_dpm_table mclk_table;
70 struct ci_single_dpm_table pcie_speed_table;
71 struct ci_single_dpm_table vddc_table;
72 struct ci_single_dpm_table vddci_table;
73 struct ci_single_dpm_table mvdd_table;
74};
75
76struct ci_mc_reg_entry {
77 u32 mclk_max;
78 u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
79};
80
81struct ci_mc_reg_table {
82 u8 last;
83 u8 num_entries;
84 u16 valid_flag;
85 struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
86 SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
87};
88
89struct ci_ulv_parm
90{
91 bool supported;
92 u32 cg_ulv_parameter;
93 u32 volt_change_delay;
94 struct ci_pl pl;
95};
96
97#define CISLANDS_MAX_LEAKAGE_COUNT 8
98
99struct ci_leakage_voltage {
100 u16 count;
101 u16 leakage_id[CISLANDS_MAX_LEAKAGE_COUNT];
102 u16 actual_voltage[CISLANDS_MAX_LEAKAGE_COUNT];
103};
104
105struct ci_dpm_level_enable_mask {
106 u32 uvd_dpm_enable_mask;
107 u32 vce_dpm_enable_mask;
108 u32 acp_dpm_enable_mask;
109 u32 samu_dpm_enable_mask;
110 u32 sclk_dpm_enable_mask;
111 u32 mclk_dpm_enable_mask;
112 u32 pcie_dpm_enable_mask;
113};
114
115struct ci_vbios_boot_state
116{
117 u16 mvdd_bootup_value;
118 u16 vddc_bootup_value;
119 u16 vddci_bootup_value;
120 u32 sclk_bootup_value;
121 u32 mclk_bootup_value;
122 u16 pcie_gen_bootup_value;
123 u16 pcie_lane_bootup_value;
124};
125
126struct ci_clock_registers {
127 u32 cg_spll_func_cntl;
128 u32 cg_spll_func_cntl_2;
129 u32 cg_spll_func_cntl_3;
130 u32 cg_spll_func_cntl_4;
131 u32 cg_spll_spread_spectrum;
132 u32 cg_spll_spread_spectrum_2;
133 u32 dll_cntl;
134 u32 mclk_pwrmgt_cntl;
135 u32 mpll_ad_func_cntl;
136 u32 mpll_dq_func_cntl;
137 u32 mpll_func_cntl;
138 u32 mpll_func_cntl_1;
139 u32 mpll_func_cntl_2;
140 u32 mpll_ss1;
141 u32 mpll_ss2;
142};
143
144struct ci_thermal_temperature_setting {
145 s32 temperature_low;
146 s32 temperature_high;
147 s32 temperature_shutdown;
148};
149
150struct ci_pcie_perf_range {
151 u16 max;
152 u16 min;
153};
154
155enum ci_pt_config_reg_type {
156 CISLANDS_CONFIGREG_MMR = 0,
157 CISLANDS_CONFIGREG_SMC_IND,
158 CISLANDS_CONFIGREG_DIDT_IND,
159 CISLANDS_CONFIGREG_CACHE,
160 CISLANDS_CONFIGREG_MAX
161};
162
163#define POWERCONTAINMENT_FEATURE_BAPM 0x00000001
164#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002
165#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004
166
167struct ci_pt_config_reg {
168 u32 offset;
169 u32 mask;
170 u32 shift;
171 u32 value;
172 enum ci_pt_config_reg_type type;
173};
174
175struct ci_pt_defaults {
176 u8 svi_load_line_en;
177 u8 svi_load_line_vddc;
178 u8 tdc_vddc_throttle_release_limit_perc;
179 u8 tdc_mawt;
180 u8 tdc_waterfall_ctl;
181 u8 dte_ambient_temp_base;
182 u32 display_cac;
183 u32 bapm_temp_gradient;
184 u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
185 u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
186};
187
188#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
189#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
190#define DPMTABLE_UPDATE_SCLK 0x00000004
191#define DPMTABLE_UPDATE_MCLK 0x00000008
192
193struct ci_power_info {
194 struct ci_dpm_table dpm_table;
195 u32 voltage_control;
196 u32 mvdd_control;
197 u32 vddci_control;
198 u32 active_auto_throttle_sources;
199 struct ci_clock_registers clock_registers;
200 u16 acpi_vddc;
201 u16 acpi_vddci;
202 enum radeon_pcie_gen force_pcie_gen;
203 enum radeon_pcie_gen acpi_pcie_gen;
204 struct ci_leakage_voltage vddc_leakage;
205 struct ci_leakage_voltage vddci_leakage;
206 u16 max_vddc_in_pp_table;
207 u16 min_vddc_in_pp_table;
208 u16 max_vddci_in_pp_table;
209 u16 min_vddci_in_pp_table;
210 u32 mclk_strobe_mode_threshold;
211 u32 mclk_stutter_mode_threshold;
212 u32 mclk_edc_enable_threshold;
213 u32 mclk_edc_wr_enable_threshold;
214 struct ci_vbios_boot_state vbios_boot_state;
215 /* smc offsets */
216 u32 sram_end;
217 u32 dpm_table_start;
218 u32 soft_regs_start;
219 u32 mc_reg_table_start;
220 u32 fan_table_start;
221 u32 arb_table_start;
222 /* smc tables */
223 SMU7_Discrete_DpmTable smc_state_table;
224 SMU7_Discrete_MCRegisters smc_mc_reg_table;
225 SMU7_Discrete_PmFuses smc_powertune_table;
226 /* other stuff */
227 struct ci_mc_reg_table mc_reg_table;
228 struct atom_voltage_table vddc_voltage_table;
229 struct atom_voltage_table vddci_voltage_table;
230 struct atom_voltage_table mvdd_voltage_table;
231 struct ci_ulv_parm ulv;
232 u32 power_containment_features;
233 const struct ci_pt_defaults *powertune_defaults;
234 u32 dte_tj_offset;
235 bool vddc_phase_shed_control;
236 struct ci_thermal_temperature_setting thermal_temp_setting;
237 struct ci_dpm_level_enable_mask dpm_level_enable_mask;
238 u32 need_update_smu7_dpm_table;
239 u32 sclk_dpm_key_disabled;
240 u32 mclk_dpm_key_disabled;
241 u32 pcie_dpm_key_disabled;
242 u32 thermal_sclk_dpm_enabled;
243 struct ci_pcie_perf_range pcie_gen_performance;
244 struct ci_pcie_perf_range pcie_lane_performance;
245 struct ci_pcie_perf_range pcie_gen_powersaving;
246 struct ci_pcie_perf_range pcie_lane_powersaving;
247 u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS];
248 u32 mclk_activity_target;
249 u32 low_sclk_interrupt_t;
250 u32 last_mclk_dpm_enable_mask;
251 u32 sys_pcie_mask;
252 /* caps */
253 bool caps_power_containment;
254 bool caps_cac;
255 bool caps_sq_ramping;
256 bool caps_db_ramping;
257 bool caps_td_ramping;
258 bool caps_tcp_ramping;
259 bool caps_fps;
260 bool caps_sclk_ds;
261 bool caps_sclk_ss_support;
262 bool caps_mclk_ss_support;
263 bool caps_uvd_dpm;
264 bool caps_vce_dpm;
265 bool caps_samu_dpm;
266 bool caps_acp_dpm;
267 bool caps_automatic_dc_transition;
268 bool caps_sclk_throttle_low_notification;
269 bool caps_dynamic_ac_timing;
270 bool caps_od_fuzzy_fan_control_support;
271 /* flags */
272 bool thermal_protection;
273 bool pcie_performance_request;
274 bool dynamic_ss;
275 bool dll_default_on;
276 bool cac_enabled;
277 bool uvd_enabled;
278 bool battery_state;
279 bool pspp_notify_required;
280 bool mem_gddr5;
281 bool enable_bapm_feature;
282 bool enable_tdc_limit_feature;
283 bool enable_pkg_pwr_tracking_feature;
284 bool use_pcie_performance_levels;
285 bool use_pcie_powersaving_levels;
286 bool uvd_power_gated;
287 /* driver states */
288 struct radeon_ps current_rps;
289 struct ci_ps current_ps;
290 struct radeon_ps requested_rps;
291 struct ci_ps requested_ps;
292 /* fan control */
293 bool fan_ctrl_is_in_default_mode;
294 bool fan_is_controlled_by_smc;
295 u32 t_min;
296 u32 fan_ctrl_default_mode;
297};
298
299#define CISLANDS_VOLTAGE_CONTROL_NONE 0x0
300#define CISLANDS_VOLTAGE_CONTROL_BY_GPIO 0x1
301#define CISLANDS_VOLTAGE_CONTROL_BY_SVID2 0x2
302
303#define CISLANDS_Q88_FORMAT_CONVERSION_UNIT 256
304
305#define CISLANDS_VRC_DFLT0 0x3FFFC000
306#define CISLANDS_VRC_DFLT1 0x000400
307#define CISLANDS_VRC_DFLT2 0xC00080
308#define CISLANDS_VRC_DFLT3 0xC00200
309#define CISLANDS_VRC_DFLT4 0xC01680
310#define CISLANDS_VRC_DFLT5 0xC00033
311#define CISLANDS_VRC_DFLT6 0xC00033
312#define CISLANDS_VRC_DFLT7 0x3FFFC000
313
314#define CISLANDS_CGULVPARAMETER_DFLT 0x00040035
315#define CISLAND_TARGETACTIVITY_DFLT 30
316#define CISLAND_MCLK_TARGETACTIVITY_DFLT 10
317
318#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
319#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
320#define PCIE_PERF_REQ_PECI_GEN1 2
321#define PCIE_PERF_REQ_PECI_GEN2 3
322#define PCIE_PERF_REQ_PECI_GEN3 4
323
324int ci_copy_bytes_to_smc(struct radeon_device *rdev,
325 u32 smc_start_address,
326 const u8 *src, u32 byte_count, u32 limit);
327void ci_start_smc(struct radeon_device *rdev);
328void ci_reset_smc(struct radeon_device *rdev);
329int ci_program_jump_on_start(struct radeon_device *rdev);
330void ci_stop_smc_clock(struct radeon_device *rdev);
331void ci_start_smc_clock(struct radeon_device *rdev);
332bool ci_is_smc_running(struct radeon_device *rdev);
333PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev);
334int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit);
335int ci_read_smc_sram_dword(struct radeon_device *rdev,
336 u32 smc_address, u32 *value, u32 limit);
337int ci_write_smc_sram_dword(struct radeon_device *rdev,
338 u32 smc_address, u32 value, u32 limit);
339
340#endif
341