1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27#include <drm/drmP.h>
28#include "radeon.h"
29#include "radeon_asic.h"
30#include "radeon_audio.h"
31#include "cikd.h"
32#include "atom.h"
33#include "cik_blit_shaders.h"
34#include "radeon_ucode.h"
35#include "clearstate_ci.h"
36
37#define SH_MEM_CONFIG_GFX_DEFAULT \
38 ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED)
39
40MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin");
41MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
42MODULE_FIRMWARE("radeon/BONAIRE_ce.bin");
43MODULE_FIRMWARE("radeon/BONAIRE_mec.bin");
44MODULE_FIRMWARE("radeon/BONAIRE_mc.bin");
45MODULE_FIRMWARE("radeon/BONAIRE_mc2.bin");
46MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin");
47MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin");
48MODULE_FIRMWARE("radeon/BONAIRE_smc.bin");
49
50MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
51MODULE_FIRMWARE("radeon/bonaire_me.bin");
52MODULE_FIRMWARE("radeon/bonaire_ce.bin");
53MODULE_FIRMWARE("radeon/bonaire_mec.bin");
54MODULE_FIRMWARE("radeon/bonaire_mc.bin");
55MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
56MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
57MODULE_FIRMWARE("radeon/bonaire_smc.bin");
58MODULE_FIRMWARE("radeon/bonaire_k_smc.bin");
59
60MODULE_FIRMWARE("radeon/HAWAII_pfp.bin");
61MODULE_FIRMWARE("radeon/HAWAII_me.bin");
62MODULE_FIRMWARE("radeon/HAWAII_ce.bin");
63MODULE_FIRMWARE("radeon/HAWAII_mec.bin");
64MODULE_FIRMWARE("radeon/HAWAII_mc.bin");
65MODULE_FIRMWARE("radeon/HAWAII_mc2.bin");
66MODULE_FIRMWARE("radeon/HAWAII_rlc.bin");
67MODULE_FIRMWARE("radeon/HAWAII_sdma.bin");
68MODULE_FIRMWARE("radeon/HAWAII_smc.bin");
69
70MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
71MODULE_FIRMWARE("radeon/hawaii_me.bin");
72MODULE_FIRMWARE("radeon/hawaii_ce.bin");
73MODULE_FIRMWARE("radeon/hawaii_mec.bin");
74MODULE_FIRMWARE("radeon/hawaii_mc.bin");
75MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
76MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
77MODULE_FIRMWARE("radeon/hawaii_smc.bin");
78MODULE_FIRMWARE("radeon/hawaii_k_smc.bin");
79
80MODULE_FIRMWARE("radeon/KAVERI_pfp.bin");
81MODULE_FIRMWARE("radeon/KAVERI_me.bin");
82MODULE_FIRMWARE("radeon/KAVERI_ce.bin");
83MODULE_FIRMWARE("radeon/KAVERI_mec.bin");
84MODULE_FIRMWARE("radeon/KAVERI_rlc.bin");
85MODULE_FIRMWARE("radeon/KAVERI_sdma.bin");
86
87MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
88MODULE_FIRMWARE("radeon/kaveri_me.bin");
89MODULE_FIRMWARE("radeon/kaveri_ce.bin");
90MODULE_FIRMWARE("radeon/kaveri_mec.bin");
91MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
92MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
93MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
94
95MODULE_FIRMWARE("radeon/KABINI_pfp.bin");
96MODULE_FIRMWARE("radeon/KABINI_me.bin");
97MODULE_FIRMWARE("radeon/KABINI_ce.bin");
98MODULE_FIRMWARE("radeon/KABINI_mec.bin");
99MODULE_FIRMWARE("radeon/KABINI_rlc.bin");
100MODULE_FIRMWARE("radeon/KABINI_sdma.bin");
101
102MODULE_FIRMWARE("radeon/kabini_pfp.bin");
103MODULE_FIRMWARE("radeon/kabini_me.bin");
104MODULE_FIRMWARE("radeon/kabini_ce.bin");
105MODULE_FIRMWARE("radeon/kabini_mec.bin");
106MODULE_FIRMWARE("radeon/kabini_rlc.bin");
107MODULE_FIRMWARE("radeon/kabini_sdma.bin");
108
109MODULE_FIRMWARE("radeon/MULLINS_pfp.bin");
110MODULE_FIRMWARE("radeon/MULLINS_me.bin");
111MODULE_FIRMWARE("radeon/MULLINS_ce.bin");
112MODULE_FIRMWARE("radeon/MULLINS_mec.bin");
113MODULE_FIRMWARE("radeon/MULLINS_rlc.bin");
114MODULE_FIRMWARE("radeon/MULLINS_sdma.bin");
115
116MODULE_FIRMWARE("radeon/mullins_pfp.bin");
117MODULE_FIRMWARE("radeon/mullins_me.bin");
118MODULE_FIRMWARE("radeon/mullins_ce.bin");
119MODULE_FIRMWARE("radeon/mullins_mec.bin");
120MODULE_FIRMWARE("radeon/mullins_rlc.bin");
121MODULE_FIRMWARE("radeon/mullins_sdma.bin");
122
123extern int r600_ih_ring_alloc(struct radeon_device *rdev);
124extern void r600_ih_ring_fini(struct radeon_device *rdev);
125extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
126extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
127extern bool evergreen_is_display_hung(struct radeon_device *rdev);
128extern void sumo_rlc_fini(struct radeon_device *rdev);
129extern int sumo_rlc_init(struct radeon_device *rdev);
130extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
131extern void si_rlc_reset(struct radeon_device *rdev);
132extern void si_init_uvd_internal_cg(struct radeon_device *rdev);
133static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);
134extern int cik_sdma_resume(struct radeon_device *rdev);
135extern void cik_sdma_enable(struct radeon_device *rdev, bool enable);
136extern void cik_sdma_fini(struct radeon_device *rdev);
137extern void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable);
138static void cik_rlc_stop(struct radeon_device *rdev);
139static void cik_pcie_gen3_enable(struct radeon_device *rdev);
140static void cik_program_aspm(struct radeon_device *rdev);
141static void cik_init_pg(struct radeon_device *rdev);
142static void cik_init_cg(struct radeon_device *rdev);
143static void cik_fini_pg(struct radeon_device *rdev);
144static void cik_fini_cg(struct radeon_device *rdev);
145static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
146 bool enable);
147
148/**
149 * cik_get_allowed_info_register - fetch the register for the info ioctl
150 *
151 * @rdev: radeon_device pointer
152 * @reg: register offset in bytes
153 * @val: register value
154 *
155 * Returns 0 for success or -EINVAL for an invalid register
156 *
157 */
158int cik_get_allowed_info_register(struct radeon_device *rdev,
159 u32 reg, u32 *val)
160{
161 switch (reg) {
162 case GRBM_STATUS:
163 case GRBM_STATUS2:
164 case GRBM_STATUS_SE0:
165 case GRBM_STATUS_SE1:
166 case GRBM_STATUS_SE2:
167 case GRBM_STATUS_SE3:
168 case SRBM_STATUS:
169 case SRBM_STATUS2:
170 case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET):
171 case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET):
172 case UVD_STATUS:
173 /* TODO VCE */
174 *val = RREG32(reg);
175 return 0;
176 default:
177 return -EINVAL;
178 }
179}
180
181/*
182 * Indirect registers accessor
183 */
184u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
185{
186 unsigned long flags;
187 u32 r;
188
189 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
190 WREG32(CIK_DIDT_IND_INDEX, (reg));
191 r = RREG32(CIK_DIDT_IND_DATA);
192 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
193 return r;
194}
195
196void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
197{
198 unsigned long flags;
199
200 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
201 WREG32(CIK_DIDT_IND_INDEX, (reg));
202 WREG32(CIK_DIDT_IND_DATA, (v));
203 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
204}
205
206/* get temperature in millidegrees */
207int ci_get_temp(struct radeon_device *rdev)
208{
209 u32 temp;
210 int actual_temp = 0;
211
212 temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
213 CTF_TEMP_SHIFT;
214
215 if (temp & 0x200)
216 actual_temp = 255;
217 else
218 actual_temp = temp & 0x1ff;
219
220 actual_temp = actual_temp * 1000;
221
222 return actual_temp;
223}
224
225/* get temperature in millidegrees */
226int kv_get_temp(struct radeon_device *rdev)
227{
228 u32 temp;
229 int actual_temp = 0;
230
231 temp = RREG32_SMC(0xC0300E0C);
232
233 if (temp)
234 actual_temp = (temp / 8) - 49;
235 else
236 actual_temp = 0;
237
238 actual_temp = actual_temp * 1000;
239
240 return actual_temp;
241}
242
243/*
244 * Indirect registers accessor
245 */
246u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg)
247{
248 unsigned long flags;
249 u32 r;
250
251 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
252 WREG32(PCIE_INDEX, reg);
253 (void)RREG32(PCIE_INDEX);
254 r = RREG32(PCIE_DATA);
255 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
256 return r;
257}
258
259void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
260{
261 unsigned long flags;
262
263 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
264 WREG32(PCIE_INDEX, reg);
265 (void)RREG32(PCIE_INDEX);
266 WREG32(PCIE_DATA, v);
267 (void)RREG32(PCIE_DATA);
268 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
269}
270
271static const u32 spectre_rlc_save_restore_register_list[] =
272{
273 (0x0e00 << 16) | (0xc12c >> 2),
274 0x00000000,
275 (0x0e00 << 16) | (0xc140 >> 2),
276 0x00000000,
277 (0x0e00 << 16) | (0xc150 >> 2),
278 0x00000000,
279 (0x0e00 << 16) | (0xc15c >> 2),
280 0x00000000,
281 (0x0e00 << 16) | (0xc168 >> 2),
282 0x00000000,
283 (0x0e00 << 16) | (0xc170 >> 2),
284 0x00000000,
285 (0x0e00 << 16) | (0xc178 >> 2),
286 0x00000000,
287 (0x0e00 << 16) | (0xc204 >> 2),
288 0x00000000,
289 (0x0e00 << 16) | (0xc2b4 >> 2),
290 0x00000000,
291 (0x0e00 << 16) | (0xc2b8 >> 2),
292 0x00000000,
293 (0x0e00 << 16) | (0xc2bc >> 2),
294 0x00000000,
295 (0x0e00 << 16) | (0xc2c0 >> 2),
296 0x00000000,
297 (0x0e00 << 16) | (0x8228 >> 2),
298 0x00000000,
299 (0x0e00 << 16) | (0x829c >> 2),
300 0x00000000,
301 (0x0e00 << 16) | (0x869c >> 2),
302 0x00000000,
303 (0x0600 << 16) | (0x98f4 >> 2),
304 0x00000000,
305 (0x0e00 << 16) | (0x98f8 >> 2),
306 0x00000000,
307 (0x0e00 << 16) | (0x9900 >> 2),
308 0x00000000,
309 (0x0e00 << 16) | (0xc260 >> 2),
310 0x00000000,
311 (0x0e00 << 16) | (0x90e8 >> 2),
312 0x00000000,
313 (0x0e00 << 16) | (0x3c000 >> 2),
314 0x00000000,
315 (0x0e00 << 16) | (0x3c00c >> 2),
316 0x00000000,
317 (0x0e00 << 16) | (0x8c1c >> 2),
318 0x00000000,
319 (0x0e00 << 16) | (0x9700 >> 2),
320 0x00000000,
321 (0x0e00 << 16) | (0xcd20 >> 2),
322 0x00000000,
323 (0x4e00 << 16) | (0xcd20 >> 2),
324 0x00000000,
325 (0x5e00 << 16) | (0xcd20 >> 2),
326 0x00000000,
327 (0x6e00 << 16) | (0xcd20 >> 2),
328 0x00000000,
329 (0x7e00 << 16) | (0xcd20 >> 2),
330 0x00000000,
331 (0x8e00 << 16) | (0xcd20 >> 2),
332 0x00000000,
333 (0x9e00 << 16) | (0xcd20 >> 2),
334 0x00000000,
335 (0xae00 << 16) | (0xcd20 >> 2),
336 0x00000000,
337 (0xbe00 << 16) | (0xcd20 >> 2),
338 0x00000000,
339 (0x0e00 << 16) | (0x89bc >> 2),
340 0x00000000,
341 (0x0e00 << 16) | (0x8900 >> 2),
342 0x00000000,
343 0x3,
344 (0x0e00 << 16) | (0xc130 >> 2),
345 0x00000000,
346 (0x0e00 << 16) | (0xc134 >> 2),
347 0x00000000,
348 (0x0e00 << 16) | (0xc1fc >> 2),
349 0x00000000,
350 (0x0e00 << 16) | (0xc208 >> 2),
351 0x00000000,
352 (0x0e00 << 16) | (0xc264 >> 2),
353 0x00000000,
354 (0x0e00 << 16) | (0xc268 >> 2),
355 0x00000000,
356 (0x0e00 << 16) | (0xc26c >> 2),
357 0x00000000,
358 (0x0e00 << 16) | (0xc270 >> 2),
359 0x00000000,
360 (0x0e00 << 16) | (0xc274 >> 2),
361 0x00000000,
362 (0x0e00 << 16) | (0xc278 >> 2),
363 0x00000000,
364 (0x0e00 << 16) | (0xc27c >> 2),
365 0x00000000,
366 (0x0e00 << 16) | (0xc280 >> 2),
367 0x00000000,
368 (0x0e00 << 16) | (0xc284 >> 2),
369 0x00000000,
370 (0x0e00 << 16) | (0xc288 >> 2),
371 0x00000000,
372 (0x0e00 << 16) | (0xc28c >> 2),
373 0x00000000,
374 (0x0e00 << 16) | (0xc290 >> 2),
375 0x00000000,
376 (0x0e00 << 16) | (0xc294 >> 2),
377 0x00000000,
378 (0x0e00 << 16) | (0xc298 >> 2),
379 0x00000000,
380 (0x0e00 << 16) | (0xc29c >> 2),
381 0x00000000,
382 (0x0e00 << 16) | (0xc2a0 >> 2),
383 0x00000000,
384 (0x0e00 << 16) | (0xc2a4 >> 2),
385 0x00000000,
386 (0x0e00 << 16) | (0xc2a8 >> 2),
387 0x00000000,
388 (0x0e00 << 16) | (0xc2ac >> 2),
389 0x00000000,
390 (0x0e00 << 16) | (0xc2b0 >> 2),
391 0x00000000,
392 (0x0e00 << 16) | (0x301d0 >> 2),
393 0x00000000,
394 (0x0e00 << 16) | (0x30238 >> 2),
395 0x00000000,
396 (0x0e00 << 16) | (0x30250 >> 2),
397 0x00000000,
398 (0x0e00 << 16) | (0x30254 >> 2),
399 0x00000000,
400 (0x0e00 << 16) | (0x30258 >> 2),
401 0x00000000,
402 (0x0e00 << 16) | (0x3025c >> 2),
403 0x00000000,
404 (0x4e00 << 16) | (0xc900 >> 2),
405 0x00000000,
406 (0x5e00 << 16) | (0xc900 >> 2),
407 0x00000000,
408 (0x6e00 << 16) | (0xc900 >> 2),
409 0x00000000,
410 (0x7e00 << 16) | (0xc900 >> 2),
411 0x00000000,
412 (0x8e00 << 16) | (0xc900 >> 2),
413 0x00000000,
414 (0x9e00 << 16) | (0xc900 >> 2),
415 0x00000000,
416 (0xae00 << 16) | (0xc900 >> 2),
417 0x00000000,
418 (0xbe00 << 16) | (0xc900 >> 2),
419 0x00000000,
420 (0x4e00 << 16) | (0xc904 >> 2),
421 0x00000000,
422 (0x5e00 << 16) | (0xc904 >> 2),
423 0x00000000,
424 (0x6e00 << 16) | (0xc904 >> 2),
425 0x00000000,
426 (0x7e00 << 16) | (0xc904 >> 2),
427 0x00000000,
428 (0x8e00 << 16) | (0xc904 >> 2),
429 0x00000000,
430 (0x9e00 << 16) | (0xc904 >> 2),
431 0x00000000,
432 (0xae00 << 16) | (0xc904 >> 2),
433 0x00000000,
434 (0xbe00 << 16) | (0xc904 >> 2),
435 0x00000000,
436 (0x4e00 << 16) | (0xc908 >> 2),
437 0x00000000,
438 (0x5e00 << 16) | (0xc908 >> 2),
439 0x00000000,
440 (0x6e00 << 16) | (0xc908 >> 2),
441 0x00000000,
442 (0x7e00 << 16) | (0xc908 >> 2),
443 0x00000000,
444 (0x8e00 << 16) | (0xc908 >> 2),
445 0x00000000,
446 (0x9e00 << 16) | (0xc908 >> 2),
447 0x00000000,
448 (0xae00 << 16) | (0xc908 >> 2),
449 0x00000000,
450 (0xbe00 << 16) | (0xc908 >> 2),
451 0x00000000,
452 (0x4e00 << 16) | (0xc90c >> 2),
453 0x00000000,
454 (0x5e00 << 16) | (0xc90c >> 2),
455 0x00000000,
456 (0x6e00 << 16) | (0xc90c >> 2),
457 0x00000000,
458 (0x7e00 << 16) | (0xc90c >> 2),
459 0x00000000,
460 (0x8e00 << 16) | (0xc90c >> 2),
461 0x00000000,
462 (0x9e00 << 16) | (0xc90c >> 2),
463 0x00000000,
464 (0xae00 << 16) | (0xc90c >> 2),
465 0x00000000,
466 (0xbe00 << 16) | (0xc90c >> 2),
467 0x00000000,
468 (0x4e00 << 16) | (0xc910 >> 2),
469 0x00000000,
470 (0x5e00 << 16) | (0xc910 >> 2),
471 0x00000000,
472 (0x6e00 << 16) | (0xc910 >> 2),
473 0x00000000,
474 (0x7e00 << 16) | (0xc910 >> 2),
475 0x00000000,
476 (0x8e00 << 16) | (0xc910 >> 2),
477 0x00000000,
478 (0x9e00 << 16) | (0xc910 >> 2),
479 0x00000000,
480 (0xae00 << 16) | (0xc910 >> 2),
481 0x00000000,
482 (0xbe00 << 16) | (0xc910 >> 2),
483 0x00000000,
484 (0x0e00 << 16) | (0xc99c >> 2),
485 0x00000000,
486 (0x0e00 << 16) | (0x9834 >> 2),
487 0x00000000,
488 (0x0000 << 16) | (0x30f00 >> 2),
489 0x00000000,
490 (0x0001 << 16) | (0x30f00 >> 2),
491 0x00000000,
492 (0x0000 << 16) | (0x30f04 >> 2),
493 0x00000000,
494 (0x0001 << 16) | (0x30f04 >> 2),
495 0x00000000,
496 (0x0000 << 16) | (0x30f08 >> 2),
497 0x00000000,
498 (0x0001 << 16) | (0x30f08 >> 2),
499 0x00000000,
500 (0x0000 << 16) | (0x30f0c >> 2),
501 0x00000000,
502 (0x0001 << 16) | (0x30f0c >> 2),
503 0x00000000,
504 (0x0600 << 16) | (0x9b7c >> 2),
505 0x00000000,
506 (0x0e00 << 16) | (0x8a14 >> 2),
507 0x00000000,
508 (0x0e00 << 16) | (0x8a18 >> 2),
509 0x00000000,
510 (0x0600 << 16) | (0x30a00 >> 2),
511 0x00000000,
512 (0x0e00 << 16) | (0x8bf0 >> 2),
513 0x00000000,
514 (0x0e00 << 16) | (0x8bcc >> 2),
515 0x00000000,
516 (0x0e00 << 16) | (0x8b24 >> 2),
517 0x00000000,
518 (0x0e00 << 16) | (0x30a04 >> 2),
519 0x00000000,
520 (0x0600 << 16) | (0x30a10 >> 2),
521 0x00000000,
522 (0x0600 << 16) | (0x30a14 >> 2),
523 0x00000000,
524 (0x0600 << 16) | (0x30a18 >> 2),
525 0x00000000,
526 (0x0600 << 16) | (0x30a2c >> 2),
527 0x00000000,
528 (0x0e00 << 16) | (0xc700 >> 2),
529 0x00000000,
530 (0x0e00 << 16) | (0xc704 >> 2),
531 0x00000000,
532 (0x0e00 << 16) | (0xc708 >> 2),
533 0x00000000,
534 (0x0e00 << 16) | (0xc768 >> 2),
535 0x00000000,
536 (0x0400 << 16) | (0xc770 >> 2),
537 0x00000000,
538 (0x0400 << 16) | (0xc774 >> 2),
539 0x00000000,
540 (0x0400 << 16) | (0xc778 >> 2),
541 0x00000000,
542 (0x0400 << 16) | (0xc77c >> 2),
543 0x00000000,
544 (0x0400 << 16) | (0xc780 >> 2),
545 0x00000000,
546 (0x0400 << 16) | (0xc784 >> 2),
547 0x00000000,
548 (0x0400 << 16) | (0xc788 >> 2),
549 0x00000000,
550 (0x0400 << 16) | (0xc78c >> 2),
551 0x00000000,
552 (0x0400 << 16) | (0xc798 >> 2),
553 0x00000000,
554 (0x0400 << 16) | (0xc79c >> 2),
555 0x00000000,
556 (0x0400 << 16) | (0xc7a0 >> 2),
557 0x00000000,
558 (0x0400 << 16) | (0xc7a4 >> 2),
559 0x00000000,
560 (0x0400 << 16) | (0xc7a8 >> 2),
561 0x00000000,
562 (0x0400 << 16) | (0xc7ac >> 2),
563 0x00000000,
564 (0x0400 << 16) | (0xc7b0 >> 2),
565 0x00000000,
566 (0x0400 << 16) | (0xc7b4 >> 2),
567 0x00000000,
568 (0x0e00 << 16) | (0x9100 >> 2),
569 0x00000000,
570 (0x0e00 << 16) | (0x3c010 >> 2),
571 0x00000000,
572 (0x0e00 << 16) | (0x92a8 >> 2),
573 0x00000000,
574 (0x0e00 << 16) | (0x92ac >> 2),
575 0x00000000,
576 (0x0e00 << 16) | (0x92b4 >> 2),
577 0x00000000,
578 (0x0e00 << 16) | (0x92b8 >> 2),
579 0x00000000,
580 (0x0e00 << 16) | (0x92bc >> 2),
581 0x00000000,
582 (0x0e00 << 16) | (0x92c0 >> 2),
583 0x00000000,
584 (0x0e00 << 16) | (0x92c4 >> 2),
585 0x00000000,
586 (0x0e00 << 16) | (0x92c8 >> 2),
587 0x00000000,
588 (0x0e00 << 16) | (0x92cc >> 2),
589 0x00000000,
590 (0x0e00 << 16) | (0x92d0 >> 2),
591 0x00000000,
592 (0x0e00 << 16) | (0x8c00 >> 2),
593 0x00000000,
594 (0x0e00 << 16) | (0x8c04 >> 2),
595 0x00000000,
596 (0x0e00 << 16) | (0x8c20 >> 2),
597 0x00000000,
598 (0x0e00 << 16) | (0x8c38 >> 2),
599 0x00000000,
600 (0x0e00 << 16) | (0x8c3c >> 2),
601 0x00000000,
602 (0x0e00 << 16) | (0xae00 >> 2),
603 0x00000000,
604 (0x0e00 << 16) | (0x9604 >> 2),
605 0x00000000,
606 (0x0e00 << 16) | (0xac08 >> 2),
607 0x00000000,
608 (0x0e00 << 16) | (0xac0c >> 2),
609 0x00000000,
610 (0x0e00 << 16) | (0xac10 >> 2),
611 0x00000000,
612 (0x0e00 << 16) | (0xac14 >> 2),
613 0x00000000,
614 (0x0e00 << 16) | (0xac58 >> 2),
615 0x00000000,
616 (0x0e00 << 16) | (0xac68 >> 2),
617 0x00000000,
618 (0x0e00 << 16) | (0xac6c >> 2),
619 0x00000000,
620 (0x0e00 << 16) | (0xac70 >> 2),
621 0x00000000,
622 (0x0e00 << 16) | (0xac74 >> 2),
623 0x00000000,
624 (0x0e00 << 16) | (0xac78 >> 2),
625 0x00000000,
626 (0x0e00 << 16) | (0xac7c >> 2),
627 0x00000000,
628 (0x0e00 << 16) | (0xac80 >> 2),
629 0x00000000,
630 (0x0e00 << 16) | (0xac84 >> 2),
631 0x00000000,
632 (0x0e00 << 16) | (0xac88 >> 2),
633 0x00000000,
634 (0x0e00 << 16) | (0xac8c >> 2),
635 0x00000000,
636 (0x0e00 << 16) | (0x970c >> 2),
637 0x00000000,
638 (0x0e00 << 16) | (0x9714 >> 2),
639 0x00000000,
640 (0x0e00 << 16) | (0x9718 >> 2),
641 0x00000000,
642 (0x0e00 << 16) | (0x971c >> 2),
643 0x00000000,
644 (0x0e00 << 16) | (0x31068 >> 2),
645 0x00000000,
646 (0x4e00 << 16) | (0x31068 >> 2),
647 0x00000000,
648 (0x5e00 << 16) | (0x31068 >> 2),
649 0x00000000,
650 (0x6e00 << 16) | (0x31068 >> 2),
651 0x00000000,
652 (0x7e00 << 16) | (0x31068 >> 2),
653 0x00000000,
654 (0x8e00 << 16) | (0x31068 >> 2),
655 0x00000000,
656 (0x9e00 << 16) | (0x31068 >> 2),
657 0x00000000,
658 (0xae00 << 16) | (0x31068 >> 2),
659 0x00000000,
660 (0xbe00 << 16) | (0x31068 >> 2),
661 0x00000000,
662 (0x0e00 << 16) | (0xcd10 >> 2),
663 0x00000000,
664 (0x0e00 << 16) | (0xcd14 >> 2),
665 0x00000000,
666 (0x0e00 << 16) | (0x88b0 >> 2),
667 0x00000000,
668 (0x0e00 << 16) | (0x88b4 >> 2),
669 0x00000000,
670 (0x0e00 << 16) | (0x88b8 >> 2),
671 0x00000000,
672 (0x0e00 << 16) | (0x88bc >> 2),
673 0x00000000,
674 (0x0400 << 16) | (0x89c0 >> 2),
675 0x00000000,
676 (0x0e00 << 16) | (0x88c4 >> 2),
677 0x00000000,
678 (0x0e00 << 16) | (0x88c8 >> 2),
679 0x00000000,
680 (0x0e00 << 16) | (0x88d0 >> 2),
681 0x00000000,
682 (0x0e00 << 16) | (0x88d4 >> 2),
683 0x00000000,
684 (0x0e00 << 16) | (0x88d8 >> 2),
685 0x00000000,
686 (0x0e00 << 16) | (0x8980 >> 2),
687 0x00000000,
688 (0x0e00 << 16) | (0x30938 >> 2),
689 0x00000000,
690 (0x0e00 << 16) | (0x3093c >> 2),
691 0x00000000,
692 (0x0e00 << 16) | (0x30940 >> 2),
693 0x00000000,
694 (0x0e00 << 16) | (0x89a0 >> 2),
695 0x00000000,
696 (0x0e00 << 16) | (0x30900 >> 2),
697 0x00000000,
698 (0x0e00 << 16) | (0x30904 >> 2),
699 0x00000000,
700 (0x0e00 << 16) | (0x89b4 >> 2),
701 0x00000000,
702 (0x0e00 << 16) | (0x3c210 >> 2),
703 0x00000000,
704 (0x0e00 << 16) | (0x3c214 >> 2),
705 0x00000000,
706 (0x0e00 << 16) | (0x3c218 >> 2),
707 0x00000000,
708 (0x0e00 << 16) | (0x8904 >> 2),
709 0x00000000,
710 0x5,
711 (0x0e00 << 16) | (0x8c28 >> 2),
712 (0x0e00 << 16) | (0x8c2c >> 2),
713 (0x0e00 << 16) | (0x8c30 >> 2),
714 (0x0e00 << 16) | (0x8c34 >> 2),
715 (0x0e00 << 16) | (0x9600 >> 2),
716};
717
718static const u32 kalindi_rlc_save_restore_register_list[] =
719{
720 (0x0e00 << 16) | (0xc12c >> 2),
721 0x00000000,
722 (0x0e00 << 16) | (0xc140 >> 2),
723 0x00000000,
724 (0x0e00 << 16) | (0xc150 >> 2),
725 0x00000000,
726 (0x0e00 << 16) | (0xc15c >> 2),
727 0x00000000,
728 (0x0e00 << 16) | (0xc168 >> 2),
729 0x00000000,
730 (0x0e00 << 16) | (0xc170 >> 2),
731 0x00000000,
732 (0x0e00 << 16) | (0xc204 >> 2),
733 0x00000000,
734 (0x0e00 << 16) | (0xc2b4 >> 2),
735 0x00000000,
736 (0x0e00 << 16) | (0xc2b8 >> 2),
737 0x00000000,
738 (0x0e00 << 16) | (0xc2bc >> 2),
739 0x00000000,
740 (0x0e00 << 16) | (0xc2c0 >> 2),
741 0x00000000,
742 (0x0e00 << 16) | (0x8228 >> 2),
743 0x00000000,
744 (0x0e00 << 16) | (0x829c >> 2),
745 0x00000000,
746 (0x0e00 << 16) | (0x869c >> 2),
747 0x00000000,
748 (0x0600 << 16) | (0x98f4 >> 2),
749 0x00000000,
750 (0x0e00 << 16) | (0x98f8 >> 2),
751 0x00000000,
752 (0x0e00 << 16) | (0x9900 >> 2),
753 0x00000000,
754 (0x0e00 << 16) | (0xc260 >> 2),
755 0x00000000,
756 (0x0e00 << 16) | (0x90e8 >> 2),
757 0x00000000,
758 (0x0e00 << 16) | (0x3c000 >> 2),
759 0x00000000,
760 (0x0e00 << 16) | (0x3c00c >> 2),
761 0x00000000,
762 (0x0e00 << 16) | (0x8c1c >> 2),
763 0x00000000,
764 (0x0e00 << 16) | (0x9700 >> 2),
765 0x00000000,
766 (0x0e00 << 16) | (0xcd20 >> 2),
767 0x00000000,
768 (0x4e00 << 16) | (0xcd20 >> 2),
769 0x00000000,
770 (0x5e00 << 16) | (0xcd20 >> 2),
771 0x00000000,
772 (0x6e00 << 16) | (0xcd20 >> 2),
773 0x00000000,
774 (0x7e00 << 16) | (0xcd20 >> 2),
775 0x00000000,
776 (0x0e00 << 16) | (0x89bc >> 2),
777 0x00000000,
778 (0x0e00 << 16) | (0x8900 >> 2),
779 0x00000000,
780 0x3,
781 (0x0e00 << 16) | (0xc130 >> 2),
782 0x00000000,
783 (0x0e00 << 16) | (0xc134 >> 2),
784 0x00000000,
785 (0x0e00 << 16) | (0xc1fc >> 2),
786 0x00000000,
787 (0x0e00 << 16) | (0xc208 >> 2),
788 0x00000000,
789 (0x0e00 << 16) | (0xc264 >> 2),
790 0x00000000,
791 (0x0e00 << 16) | (0xc268 >> 2),
792 0x00000000,
793 (0x0e00 << 16) | (0xc26c >> 2),
794 0x00000000,
795 (0x0e00 << 16) | (0xc270 >> 2),
796 0x00000000,
797 (0x0e00 << 16) | (0xc274 >> 2),
798 0x00000000,
799 (0x0e00 << 16) | (0xc28c >> 2),
800 0x00000000,
801 (0x0e00 << 16) | (0xc290 >> 2),
802 0x00000000,
803 (0x0e00 << 16) | (0xc294 >> 2),
804 0x00000000,
805 (0x0e00 << 16) | (0xc298 >> 2),
806 0x00000000,
807 (0x0e00 << 16) | (0xc2a0 >> 2),
808 0x00000000,
809 (0x0e00 << 16) | (0xc2a4 >> 2),
810 0x00000000,
811 (0x0e00 << 16) | (0xc2a8 >> 2),
812 0x00000000,
813 (0x0e00 << 16) | (0xc2ac >> 2),
814 0x00000000,
815 (0x0e00 << 16) | (0x301d0 >> 2),
816 0x00000000,
817 (0x0e00 << 16) | (0x30238 >> 2),
818 0x00000000,
819 (0x0e00 << 16) | (0x30250 >> 2),
820 0x00000000,
821 (0x0e00 << 16) | (0x30254 >> 2),
822 0x00000000,
823 (0x0e00 << 16) | (0x30258 >> 2),
824 0x00000000,
825 (0x0e00 << 16) | (0x3025c >> 2),
826 0x00000000,
827 (0x4e00 << 16) | (0xc900 >> 2),
828 0x00000000,
829 (0x5e00 << 16) | (0xc900 >> 2),
830 0x00000000,
831 (0x6e00 << 16) | (0xc900 >> 2),
832 0x00000000,
833 (0x7e00 << 16) | (0xc900 >> 2),
834 0x00000000,
835 (0x4e00 << 16) | (0xc904 >> 2),
836 0x00000000,
837 (0x5e00 << 16) | (0xc904 >> 2),
838 0x00000000,
839 (0x6e00 << 16) | (0xc904 >> 2),
840 0x00000000,
841 (0x7e00 << 16) | (0xc904 >> 2),
842 0x00000000,
843 (0x4e00 << 16) | (0xc908 >> 2),
844 0x00000000,
845 (0x5e00 << 16) | (0xc908 >> 2),
846 0x00000000,
847 (0x6e00 << 16) | (0xc908 >> 2),
848 0x00000000,
849 (0x7e00 << 16) | (0xc908 >> 2),
850 0x00000000,
851 (0x4e00 << 16) | (0xc90c >> 2),
852 0x00000000,
853 (0x5e00 << 16) | (0xc90c >> 2),
854 0x00000000,
855 (0x6e00 << 16) | (0xc90c >> 2),
856 0x00000000,
857 (0x7e00 << 16) | (0xc90c >> 2),
858 0x00000000,
859 (0x4e00 << 16) | (0xc910 >> 2),
860 0x00000000,
861 (0x5e00 << 16) | (0xc910 >> 2),
862 0x00000000,
863 (0x6e00 << 16) | (0xc910 >> 2),
864 0x00000000,
865 (0x7e00 << 16) | (0xc910 >> 2),
866 0x00000000,
867 (0x0e00 << 16) | (0xc99c >> 2),
868 0x00000000,
869 (0x0e00 << 16) | (0x9834 >> 2),
870 0x00000000,
871 (0x0000 << 16) | (0x30f00 >> 2),
872 0x00000000,
873 (0x0000 << 16) | (0x30f04 >> 2),
874 0x00000000,
875 (0x0000 << 16) | (0x30f08 >> 2),
876 0x00000000,
877 (0x0000 << 16) | (0x30f0c >> 2),
878 0x00000000,
879 (0x0600 << 16) | (0x9b7c >> 2),
880 0x00000000,
881 (0x0e00 << 16) | (0x8a14 >> 2),
882 0x00000000,
883 (0x0e00 << 16) | (0x8a18 >> 2),
884 0x00000000,
885 (0x0600 << 16) | (0x30a00 >> 2),
886 0x00000000,
887 (0x0e00 << 16) | (0x8bf0 >> 2),
888 0x00000000,
889 (0x0e00 << 16) | (0x8bcc >> 2),
890 0x00000000,
891 (0x0e00 << 16) | (0x8b24 >> 2),
892 0x00000000,
893 (0x0e00 << 16) | (0x30a04 >> 2),
894 0x00000000,
895 (0x0600 << 16) | (0x30a10 >> 2),
896 0x00000000,
897 (0x0600 << 16) | (0x30a14 >> 2),
898 0x00000000,
899 (0x0600 << 16) | (0x30a18 >> 2),
900 0x00000000,
901 (0x0600 << 16) | (0x30a2c >> 2),
902 0x00000000,
903 (0x0e00 << 16) | (0xc700 >> 2),
904 0x00000000,
905 (0x0e00 << 16) | (0xc704 >> 2),
906 0x00000000,
907 (0x0e00 << 16) | (0xc708 >> 2),
908 0x00000000,
909 (0x0e00 << 16) | (0xc768 >> 2),
910 0x00000000,
911 (0x0400 << 16) | (0xc770 >> 2),
912 0x00000000,
913 (0x0400 << 16) | (0xc774 >> 2),
914 0x00000000,
915 (0x0400 << 16) | (0xc798 >> 2),
916 0x00000000,
917 (0x0400 << 16) | (0xc79c >> 2),
918 0x00000000,
919 (0x0e00 << 16) | (0x9100 >> 2),
920 0x00000000,
921 (0x0e00 << 16) | (0x3c010 >> 2),
922 0x00000000,
923 (0x0e00 << 16) | (0x8c00 >> 2),
924 0x00000000,
925 (0x0e00 << 16) | (0x8c04 >> 2),
926 0x00000000,
927 (0x0e00 << 16) | (0x8c20 >> 2),
928 0x00000000,
929 (0x0e00 << 16) | (0x8c38 >> 2),
930 0x00000000,
931 (0x0e00 << 16) | (0x8c3c >> 2),
932 0x00000000,
933 (0x0e00 << 16) | (0xae00 >> 2),
934 0x00000000,
935 (0x0e00 << 16) | (0x9604 >> 2),
936 0x00000000,
937 (0x0e00 << 16) | (0xac08 >> 2),
938 0x00000000,
939 (0x0e00 << 16) | (0xac0c >> 2),
940 0x00000000,
941 (0x0e00 << 16) | (0xac10 >> 2),
942 0x00000000,
943 (0x0e00 << 16) | (0xac14 >> 2),
944 0x00000000,
945 (0x0e00 << 16) | (0xac58 >> 2),
946 0x00000000,
947 (0x0e00 << 16) | (0xac68 >> 2),
948 0x00000000,
949 (0x0e00 << 16) | (0xac6c >> 2),
950 0x00000000,
951 (0x0e00 << 16) | (0xac70 >> 2),
952 0x00000000,
953 (0x0e00 << 16) | (0xac74 >> 2),
954 0x00000000,
955 (0x0e00 << 16) | (0xac78 >> 2),
956 0x00000000,
957 (0x0e00 << 16) | (0xac7c >> 2),
958 0x00000000,
959 (0x0e00 << 16) | (0xac80 >> 2),
960 0x00000000,
961 (0x0e00 << 16) | (0xac84 >> 2),
962 0x00000000,
963 (0x0e00 << 16) | (0xac88 >> 2),
964 0x00000000,
965 (0x0e00 << 16) | (0xac8c >> 2),
966 0x00000000,
967 (0x0e00 << 16) | (0x970c >> 2),
968 0x00000000,
969 (0x0e00 << 16) | (0x9714 >> 2),
970 0x00000000,
971 (0x0e00 << 16) | (0x9718 >> 2),
972 0x00000000,
973 (0x0e00 << 16) | (0x971c >> 2),
974 0x00000000,
975 (0x0e00 << 16) | (0x31068 >> 2),
976 0x00000000,
977 (0x4e00 << 16) | (0x31068 >> 2),
978 0x00000000,
979 (0x5e00 << 16) | (0x31068 >> 2),
980 0x00000000,
981 (0x6e00 << 16) | (0x31068 >> 2),
982 0x00000000,
983 (0x7e00 << 16) | (0x31068 >> 2),
984 0x00000000,
985 (0x0e00 << 16) | (0xcd10 >> 2),
986 0x00000000,
987 (0x0e00 << 16) | (0xcd14 >> 2),
988 0x00000000,
989 (0x0e00 << 16) | (0x88b0 >> 2),
990 0x00000000,
991 (0x0e00 << 16) | (0x88b4 >> 2),
992 0x00000000,
993 (0x0e00 << 16) | (0x88b8 >> 2),
994 0x00000000,
995 (0x0e00 << 16) | (0x88bc >> 2),
996 0x00000000,
997 (0x0400 << 16) | (0x89c0 >> 2),
998 0x00000000,
999 (0x0e00 << 16) | (0x88c4 >> 2),
1000 0x00000000,
1001 (0x0e00 << 16) | (0x88c8 >> 2),
1002 0x00000000,
1003 (0x0e00 << 16) | (0x88d0 >> 2),
1004 0x00000000,
1005 (0x0e00 << 16) | (0x88d4 >> 2),
1006 0x00000000,
1007 (0x0e00 << 16) | (0x88d8 >> 2),
1008 0x00000000,
1009 (0x0e00 << 16) | (0x8980 >> 2),
1010 0x00000000,
1011 (0x0e00 << 16) | (0x30938 >> 2),
1012 0x00000000,
1013 (0x0e00 << 16) | (0x3093c >> 2),
1014 0x00000000,
1015 (0x0e00 << 16) | (0x30940 >> 2),
1016 0x00000000,
1017 (0x0e00 << 16) | (0x89a0 >> 2),
1018 0x00000000,
1019 (0x0e00 << 16) | (0x30900 >> 2),
1020 0x00000000,
1021 (0x0e00 << 16) | (0x30904 >> 2),
1022 0x00000000,
1023 (0x0e00 << 16) | (0x89b4 >> 2),
1024 0x00000000,
1025 (0x0e00 << 16) | (0x3e1fc >> 2),
1026 0x00000000,
1027 (0x0e00 << 16) | (0x3c210 >> 2),
1028 0x00000000,
1029 (0x0e00 << 16) | (0x3c214 >> 2),
1030 0x00000000,
1031 (0x0e00 << 16) | (0x3c218 >> 2),
1032 0x00000000,
1033 (0x0e00 << 16) | (0x8904 >> 2),
1034 0x00000000,
1035 0x5,
1036 (0x0e00 << 16) | (0x8c28 >> 2),
1037 (0x0e00 << 16) | (0x8c2c >> 2),
1038 (0x0e00 << 16) | (0x8c30 >> 2),
1039 (0x0e00 << 16) | (0x8c34 >> 2),
1040 (0x0e00 << 16) | (0x9600 >> 2),
1041};
1042
1043static const u32 bonaire_golden_spm_registers[] =
1044{
1045 0x30800, 0xe0ffffff, 0xe0000000
1046};
1047
1048static const u32 bonaire_golden_common_registers[] =
1049{
1050 0xc770, 0xffffffff, 0x00000800,
1051 0xc774, 0xffffffff, 0x00000800,
1052 0xc798, 0xffffffff, 0x00007fbf,
1053 0xc79c, 0xffffffff, 0x00007faf
1054};
1055
1056static const u32 bonaire_golden_registers[] =
1057{
1058 0x3354, 0x00000333, 0x00000333,
1059 0x3350, 0x000c0fc0, 0x00040200,
1060 0x9a10, 0x00010000, 0x00058208,
1061 0x3c000, 0xffff1fff, 0x00140000,
1062 0x3c200, 0xfdfc0fff, 0x00000100,
1063 0x3c234, 0x40000000, 0x40000200,
1064 0x9830, 0xffffffff, 0x00000000,
1065 0x9834, 0xf00fffff, 0x00000400,
1066 0x9838, 0x0002021c, 0x00020200,
1067 0xc78, 0x00000080, 0x00000000,
1068 0x5bb0, 0x000000f0, 0x00000070,
1069 0x5bc0, 0xf0311fff, 0x80300000,
1070 0x98f8, 0x73773777, 0x12010001,
1071 0x350c, 0x00810000, 0x408af000,
1072 0x7030, 0x31000111, 0x00000011,
1073 0x2f48, 0x73773777, 0x12010001,
1074 0x220c, 0x00007fb6, 0x0021a1b1,
1075 0x2210, 0x00007fb6, 0x002021b1,
1076 0x2180, 0x00007fb6, 0x00002191,
1077 0x2218, 0x00007fb6, 0x002121b1,
1078 0x221c, 0x00007fb6, 0x002021b1,
1079 0x21dc, 0x00007fb6, 0x00002191,
1080 0x21e0, 0x00007fb6, 0x00002191,
1081 0x3628, 0x0000003f, 0x0000000a,
1082 0x362c, 0x0000003f, 0x0000000a,
1083 0x2ae4, 0x00073ffe, 0x000022a2,
1084 0x240c, 0x000007ff, 0x00000000,
1085 0x8a14, 0xf000003f, 0x00000007,
1086 0x8bf0, 0x00002001, 0x00000001,
1087 0x8b24, 0xffffffff, 0x00ffffff,
1088 0x30a04, 0x0000ff0f, 0x00000000,
1089 0x28a4c, 0x07ffffff, 0x06000000,
1090 0x4d8, 0x00000fff, 0x00000100,
1091 0x3e78, 0x00000001, 0x00000002,
1092 0x9100, 0x03000000, 0x0362c688,
1093 0x8c00, 0x000000ff, 0x00000001,
1094 0xe40, 0x00001fff, 0x00001fff,
1095 0x9060, 0x0000007f, 0x00000020,
1096 0x9508, 0x00010000, 0x00010000,
1097 0xac14, 0x000003ff, 0x000000f3,
1098 0xac0c, 0xffffffff, 0x00001032
1099};
1100
1101static const u32 bonaire_mgcg_cgcg_init[] =
1102{
1103 0xc420, 0xffffffff, 0xfffffffc,
1104 0x30800, 0xffffffff, 0xe0000000,
1105 0x3c2a0, 0xffffffff, 0x00000100,
1106 0x3c208, 0xffffffff, 0x00000100,
1107 0x3c2c0, 0xffffffff, 0xc0000100,
1108 0x3c2c8, 0xffffffff, 0xc0000100,
1109 0x3c2c4, 0xffffffff, 0xc0000100,
1110 0x55e4, 0xffffffff, 0x00600100,
1111 0x3c280, 0xffffffff, 0x00000100,
1112 0x3c214, 0xffffffff, 0x06000100,
1113 0x3c220, 0xffffffff, 0x00000100,
1114 0x3c218, 0xffffffff, 0x06000100,
1115 0x3c204, 0xffffffff, 0x00000100,
1116 0x3c2e0, 0xffffffff, 0x00000100,
1117 0x3c224, 0xffffffff, 0x00000100,
1118 0x3c200, 0xffffffff, 0x00000100,
1119 0x3c230, 0xffffffff, 0x00000100,
1120 0x3c234, 0xffffffff, 0x00000100,
1121 0x3c250, 0xffffffff, 0x00000100,
1122 0x3c254, 0xffffffff, 0x00000100,
1123 0x3c258, 0xffffffff, 0x00000100,
1124 0x3c25c, 0xffffffff, 0x00000100,
1125 0x3c260, 0xffffffff, 0x00000100,
1126 0x3c27c, 0xffffffff, 0x00000100,
1127 0x3c278, 0xffffffff, 0x00000100,
1128 0x3c210, 0xffffffff, 0x06000100,
1129 0x3c290, 0xffffffff, 0x00000100,
1130 0x3c274, 0xffffffff, 0x00000100,
1131 0x3c2b4, 0xffffffff, 0x00000100,
1132 0x3c2b0, 0xffffffff, 0x00000100,
1133 0x3c270, 0xffffffff, 0x00000100,
1134 0x30800, 0xffffffff, 0xe0000000,
1135 0x3c020, 0xffffffff, 0x00010000,
1136 0x3c024, 0xffffffff, 0x00030002,
1137 0x3c028, 0xffffffff, 0x00040007,
1138 0x3c02c, 0xffffffff, 0x00060005,
1139 0x3c030, 0xffffffff, 0x00090008,
1140 0x3c034, 0xffffffff, 0x00010000,
1141 0x3c038, 0xffffffff, 0x00030002,
1142 0x3c03c, 0xffffffff, 0x00040007,
1143 0x3c040, 0xffffffff, 0x00060005,
1144 0x3c044, 0xffffffff, 0x00090008,
1145 0x3c048, 0xffffffff, 0x00010000,
1146 0x3c04c, 0xffffffff, 0x00030002,
1147 0x3c050, 0xffffffff, 0x00040007,
1148 0x3c054, 0xffffffff, 0x00060005,
1149 0x3c058, 0xffffffff, 0x00090008,
1150 0x3c05c, 0xffffffff, 0x00010000,
1151 0x3c060, 0xffffffff, 0x00030002,
1152 0x3c064, 0xffffffff, 0x00040007,
1153 0x3c068, 0xffffffff, 0x00060005,
1154 0x3c06c, 0xffffffff, 0x00090008,
1155 0x3c070, 0xffffffff, 0x00010000,
1156 0x3c074, 0xffffffff, 0x00030002,
1157 0x3c078, 0xffffffff, 0x00040007,
1158 0x3c07c, 0xffffffff, 0x00060005,
1159 0x3c080, 0xffffffff, 0x00090008,
1160 0x3c084, 0xffffffff, 0x00010000,
1161 0x3c088, 0xffffffff, 0x00030002,
1162 0x3c08c, 0xffffffff, 0x00040007,
1163 0x3c090, 0xffffffff, 0x00060005,
1164 0x3c094, 0xffffffff, 0x00090008,
1165 0x3c098, 0xffffffff, 0x00010000,
1166 0x3c09c, 0xffffffff, 0x00030002,
1167 0x3c0a0, 0xffffffff, 0x00040007,
1168 0x3c0a4, 0xffffffff, 0x00060005,
1169 0x3c0a8, 0xffffffff, 0x00090008,
1170 0x3c000, 0xffffffff, 0x96e00200,
1171 0x8708, 0xffffffff, 0x00900100,
1172 0xc424, 0xffffffff, 0x0020003f,
1173 0x38, 0xffffffff, 0x0140001c,
1174 0x3c, 0x000f0000, 0x000f0000,
1175 0x220, 0xffffffff, 0xC060000C,
1176 0x224, 0xc0000fff, 0x00000100,
1177 0xf90, 0xffffffff, 0x00000100,
1178 0xf98, 0x00000101, 0x00000000,
1179 0x20a8, 0xffffffff, 0x00000104,
1180 0x55e4, 0xff000fff, 0x00000100,
1181 0x30cc, 0xc0000fff, 0x00000104,
1182 0xc1e4, 0x00000001, 0x00000001,
1183 0xd00c, 0xff000ff0, 0x00000100,
1184 0xd80c, 0xff000ff0, 0x00000100
1185};
1186
1187static const u32 spectre_golden_spm_registers[] =
1188{
1189 0x30800, 0xe0ffffff, 0xe0000000
1190};
1191
1192static const u32 spectre_golden_common_registers[] =
1193{
1194 0xc770, 0xffffffff, 0x00000800,
1195 0xc774, 0xffffffff, 0x00000800,
1196 0xc798, 0xffffffff, 0x00007fbf,
1197 0xc79c, 0xffffffff, 0x00007faf
1198};
1199
1200static const u32 spectre_golden_registers[] =
1201{
1202 0x3c000, 0xffff1fff, 0x96940200,
1203 0x3c00c, 0xffff0001, 0xff000000,
1204 0x3c200, 0xfffc0fff, 0x00000100,
1205 0x6ed8, 0x00010101, 0x00010000,
1206 0x9834, 0xf00fffff, 0x00000400,
1207 0x9838, 0xfffffffc, 0x00020200,
1208 0x5bb0, 0x000000f0, 0x00000070,
1209 0x5bc0, 0xf0311fff, 0x80300000,
1210 0x98f8, 0x73773777, 0x12010001,
1211 0x9b7c, 0x00ff0000, 0x00fc0000,
1212 0x2f48, 0x73773777, 0x12010001,
1213 0x8a14, 0xf000003f, 0x00000007,
1214 0x8b24, 0xffffffff, 0x00ffffff,
1215 0x28350, 0x3f3f3fff, 0x00000082,
1216 0x28354, 0x0000003f, 0x00000000,
1217 0x3e78, 0x00000001, 0x00000002,
1218 0x913c, 0xffff03df, 0x00000004,
1219 0xc768, 0x00000008, 0x00000008,
1220 0x8c00, 0x000008ff, 0x00000800,
1221 0x9508, 0x00010000, 0x00010000,
1222 0xac0c, 0xffffffff, 0x54763210,
1223 0x214f8, 0x01ff01ff, 0x00000002,
1224 0x21498, 0x007ff800, 0x00200000,
1225 0x2015c, 0xffffffff, 0x00000f40,
1226 0x30934, 0xffffffff, 0x00000001
1227};
1228
1229static const u32 spectre_mgcg_cgcg_init[] =
1230{
1231 0xc420, 0xffffffff, 0xfffffffc,
1232 0x30800, 0xffffffff, 0xe0000000,
1233 0x3c2a0, 0xffffffff, 0x00000100,
1234 0x3c208, 0xffffffff, 0x00000100,
1235 0x3c2c0, 0xffffffff, 0x00000100,
1236 0x3c2c8, 0xffffffff, 0x00000100,
1237 0x3c2c4, 0xffffffff, 0x00000100,
1238 0x55e4, 0xffffffff, 0x00600100,
1239 0x3c280, 0xffffffff, 0x00000100,
1240 0x3c214, 0xffffffff, 0x06000100,
1241 0x3c220, 0xffffffff, 0x00000100,
1242 0x3c218, 0xffffffff, 0x06000100,
1243 0x3c204, 0xffffffff, 0x00000100,
1244 0x3c2e0, 0xffffffff, 0x00000100,
1245 0x3c224, 0xffffffff, 0x00000100,
1246 0x3c200, 0xffffffff, 0x00000100,
1247 0x3c230, 0xffffffff, 0x00000100,
1248 0x3c234, 0xffffffff, 0x00000100,
1249 0x3c250, 0xffffffff, 0x00000100,
1250 0x3c254, 0xffffffff, 0x00000100,
1251 0x3c258, 0xffffffff, 0x00000100,
1252 0x3c25c, 0xffffffff, 0x00000100,
1253 0x3c260, 0xffffffff, 0x00000100,
1254 0x3c27c, 0xffffffff, 0x00000100,
1255 0x3c278, 0xffffffff, 0x00000100,
1256 0x3c210, 0xffffffff, 0x06000100,
1257 0x3c290, 0xffffffff, 0x00000100,
1258 0x3c274, 0xffffffff, 0x00000100,
1259 0x3c2b4, 0xffffffff, 0x00000100,
1260 0x3c2b0, 0xffffffff, 0x00000100,
1261 0x3c270, 0xffffffff, 0x00000100,
1262 0x30800, 0xffffffff, 0xe0000000,
1263 0x3c020, 0xffffffff, 0x00010000,
1264 0x3c024, 0xffffffff, 0x00030002,
1265 0x3c028, 0xffffffff, 0x00040007,
1266 0x3c02c, 0xffffffff, 0x00060005,
1267 0x3c030, 0xffffffff, 0x00090008,
1268 0x3c034, 0xffffffff, 0x00010000,
1269 0x3c038, 0xffffffff, 0x00030002,
1270 0x3c03c, 0xffffffff, 0x00040007,
1271 0x3c040, 0xffffffff, 0x00060005,
1272 0x3c044, 0xffffffff, 0x00090008,
1273 0x3c048, 0xffffffff, 0x00010000,
1274 0x3c04c, 0xffffffff, 0x00030002,
1275 0x3c050, 0xffffffff, 0x00040007,
1276 0x3c054, 0xffffffff, 0x00060005,
1277 0x3c058, 0xffffffff, 0x00090008,
1278 0x3c05c, 0xffffffff, 0x00010000,
1279 0x3c060, 0xffffffff, 0x00030002,
1280 0x3c064, 0xffffffff, 0x00040007,
1281 0x3c068, 0xffffffff, 0x00060005,
1282 0x3c06c, 0xffffffff, 0x00090008,
1283 0x3c070, 0xffffffff, 0x00010000,
1284 0x3c074, 0xffffffff, 0x00030002,
1285 0x3c078, 0xffffffff, 0x00040007,
1286 0x3c07c, 0xffffffff, 0x00060005,
1287 0x3c080, 0xffffffff, 0x00090008,
1288 0x3c084, 0xffffffff, 0x00010000,
1289 0x3c088, 0xffffffff, 0x00030002,
1290 0x3c08c, 0xffffffff, 0x00040007,
1291 0x3c090, 0xffffffff, 0x00060005,
1292 0x3c094, 0xffffffff, 0x00090008,
1293 0x3c098, 0xffffffff, 0x00010000,
1294 0x3c09c, 0xffffffff, 0x00030002,
1295 0x3c0a0, 0xffffffff, 0x00040007,
1296 0x3c0a4, 0xffffffff, 0x00060005,
1297 0x3c0a8, 0xffffffff, 0x00090008,
1298 0x3c0ac, 0xffffffff, 0x00010000,
1299 0x3c0b0, 0xffffffff, 0x00030002,
1300 0x3c0b4, 0xffffffff, 0x00040007,
1301 0x3c0b8, 0xffffffff, 0x00060005,
1302 0x3c0bc, 0xffffffff, 0x00090008,
1303 0x3c000, 0xffffffff, 0x96e00200,
1304 0x8708, 0xffffffff, 0x00900100,
1305 0xc424, 0xffffffff, 0x0020003f,
1306 0x38, 0xffffffff, 0x0140001c,
1307 0x3c, 0x000f0000, 0x000f0000,
1308 0x220, 0xffffffff, 0xC060000C,
1309 0x224, 0xc0000fff, 0x00000100,
1310 0xf90, 0xffffffff, 0x00000100,
1311 0xf98, 0x00000101, 0x00000000,
1312 0x20a8, 0xffffffff, 0x00000104,
1313 0x55e4, 0xff000fff, 0x00000100,
1314 0x30cc, 0xc0000fff, 0x00000104,
1315 0xc1e4, 0x00000001, 0x00000001,
1316 0xd00c, 0xff000ff0, 0x00000100,
1317 0xd80c, 0xff000ff0, 0x00000100
1318};
1319
1320static const u32 kalindi_golden_spm_registers[] =
1321{
1322 0x30800, 0xe0ffffff, 0xe0000000
1323};
1324
1325static const u32 kalindi_golden_common_registers[] =
1326{
1327 0xc770, 0xffffffff, 0x00000800,
1328 0xc774, 0xffffffff, 0x00000800,
1329 0xc798, 0xffffffff, 0x00007fbf,
1330 0xc79c, 0xffffffff, 0x00007faf
1331};
1332
1333static const u32 kalindi_golden_registers[] =
1334{
1335 0x3c000, 0xffffdfff, 0x6e944040,
1336 0x55e4, 0xff607fff, 0xfc000100,
1337 0x3c220, 0xff000fff, 0x00000100,
1338 0x3c224, 0xff000fff, 0x00000100,
1339 0x3c200, 0xfffc0fff, 0x00000100,
1340 0x6ed8, 0x00010101, 0x00010000,
1341 0x9830, 0xffffffff, 0x00000000,
1342 0x9834, 0xf00fffff, 0x00000400,
1343 0x5bb0, 0x000000f0, 0x00000070,
1344 0x5bc0, 0xf0311fff, 0x80300000,
1345 0x98f8, 0x73773777, 0x12010001,
1346 0x98fc, 0xffffffff, 0x00000010,
1347 0x9b7c, 0x00ff0000, 0x00fc0000,
1348 0x8030, 0x00001f0f, 0x0000100a,
1349 0x2f48, 0x73773777, 0x12010001,
1350 0x2408, 0x000fffff, 0x000c007f,
1351 0x8a14, 0xf000003f, 0x00000007,
1352 0x8b24, 0x3fff3fff, 0x00ffcfff,
1353 0x30a04, 0x0000ff0f, 0x00000000,
1354 0x28a4c, 0x07ffffff, 0x06000000,
1355 0x4d8, 0x00000fff, 0x00000100,
1356 0x3e78, 0x00000001, 0x00000002,
1357 0xc768, 0x00000008, 0x00000008,
1358 0x8c00, 0x000000ff, 0x00000003,
1359 0x214f8, 0x01ff01ff, 0x00000002,
1360 0x21498, 0x007ff800, 0x00200000,
1361 0x2015c, 0xffffffff, 0x00000f40,
1362 0x88c4, 0x001f3ae3, 0x00000082,
1363 0x88d4, 0x0000001f, 0x00000010,
1364 0x30934, 0xffffffff, 0x00000000
1365};
1366
1367static const u32 kalindi_mgcg_cgcg_init[] =
1368{
1369 0xc420, 0xffffffff, 0xfffffffc,
1370 0x30800, 0xffffffff, 0xe0000000,
1371 0x3c2a0, 0xffffffff, 0x00000100,
1372 0x3c208, 0xffffffff, 0x00000100,
1373 0x3c2c0, 0xffffffff, 0x00000100,
1374 0x3c2c8, 0xffffffff, 0x00000100,
1375 0x3c2c4, 0xffffffff, 0x00000100,
1376 0x55e4, 0xffffffff, 0x00600100,
1377 0x3c280, 0xffffffff, 0x00000100,
1378 0x3c214, 0xffffffff, 0x06000100,
1379 0x3c220, 0xffffffff, 0x00000100,
1380 0x3c218, 0xffffffff, 0x06000100,
1381 0x3c204, 0xffffffff, 0x00000100,
1382 0x3c2e0, 0xffffffff, 0x00000100,
1383 0x3c224, 0xffffffff, 0x00000100,
1384 0x3c200, 0xffffffff, 0x00000100,
1385 0x3c230, 0xffffffff, 0x00000100,
1386 0x3c234, 0xffffffff, 0x00000100,
1387 0x3c250, 0xffffffff, 0x00000100,
1388 0x3c254, 0xffffffff, 0x00000100,
1389 0x3c258, 0xffffffff, 0x00000100,
1390 0x3c25c, 0xffffffff, 0x00000100,
1391 0x3c260, 0xffffffff, 0x00000100,
1392 0x3c27c, 0xffffffff, 0x00000100,
1393 0x3c278, 0xffffffff, 0x00000100,
1394 0x3c210, 0xffffffff, 0x06000100,
1395 0x3c290, 0xffffffff, 0x00000100,
1396 0x3c274, 0xffffffff, 0x00000100,
1397 0x3c2b4, 0xffffffff, 0x00000100,
1398 0x3c2b0, 0xffffffff, 0x00000100,
1399 0x3c270, 0xffffffff, 0x00000100,
1400 0x30800, 0xffffffff, 0xe0000000,
1401 0x3c020, 0xffffffff, 0x00010000,
1402 0x3c024, 0xffffffff, 0x00030002,
1403 0x3c028, 0xffffffff, 0x00040007,
1404 0x3c02c, 0xffffffff, 0x00060005,
1405 0x3c030, 0xffffffff, 0x00090008,
1406 0x3c034, 0xffffffff, 0x00010000,
1407 0x3c038, 0xffffffff, 0x00030002,
1408 0x3c03c, 0xffffffff, 0x00040007,
1409 0x3c040, 0xffffffff, 0x00060005,
1410 0x3c044, 0xffffffff, 0x00090008,
1411 0x3c000, 0xffffffff, 0x96e00200,
1412 0x8708, 0xffffffff, 0x00900100,
1413 0xc424, 0xffffffff, 0x0020003f,
1414 0x38, 0xffffffff, 0x0140001c,
1415 0x3c, 0x000f0000, 0x000f0000,
1416 0x220, 0xffffffff, 0xC060000C,
1417 0x224, 0xc0000fff, 0x00000100,
1418 0x20a8, 0xffffffff, 0x00000104,
1419 0x55e4, 0xff000fff, 0x00000100,
1420 0x30cc, 0xc0000fff, 0x00000104,
1421 0xc1e4, 0x00000001, 0x00000001,
1422 0xd00c, 0xff000ff0, 0x00000100,
1423 0xd80c, 0xff000ff0, 0x00000100
1424};
1425
1426static const u32 hawaii_golden_spm_registers[] =
1427{
1428 0x30800, 0xe0ffffff, 0xe0000000
1429};
1430
1431static const u32 hawaii_golden_common_registers[] =
1432{
1433 0x30800, 0xffffffff, 0xe0000000,
1434 0x28350, 0xffffffff, 0x3a00161a,
1435 0x28354, 0xffffffff, 0x0000002e,
1436 0x9a10, 0xffffffff, 0x00018208,
1437 0x98f8, 0xffffffff, 0x12011003
1438};
1439
1440static const u32 hawaii_golden_registers[] =
1441{
1442 0x3354, 0x00000333, 0x00000333,
1443 0x9a10, 0x00010000, 0x00058208,
1444 0x9830, 0xffffffff, 0x00000000,
1445 0x9834, 0xf00fffff, 0x00000400,
1446 0x9838, 0x0002021c, 0x00020200,
1447 0xc78, 0x00000080, 0x00000000,
1448 0x5bb0, 0x000000f0, 0x00000070,
1449 0x5bc0, 0xf0311fff, 0x80300000,
1450 0x350c, 0x00810000, 0x408af000,
1451 0x7030, 0x31000111, 0x00000011,
1452 0x2f48, 0x73773777, 0x12010001,
1453 0x2120, 0x0000007f, 0x0000001b,
1454 0x21dc, 0x00007fb6, 0x00002191,
1455 0x3628, 0x0000003f, 0x0000000a,
1456 0x362c, 0x0000003f, 0x0000000a,
1457 0x2ae4, 0x00073ffe, 0x000022a2,
1458 0x240c, 0x000007ff, 0x00000000,
1459 0x8bf0, 0x00002001, 0x00000001,
1460 0x8b24, 0xffffffff, 0x00ffffff,
1461 0x30a04, 0x0000ff0f, 0x00000000,
1462 0x28a4c, 0x07ffffff, 0x06000000,
1463 0x3e78, 0x00000001, 0x00000002,
1464 0xc768, 0x00000008, 0x00000008,
1465 0xc770, 0x00000f00, 0x00000800,
1466 0xc774, 0x00000f00, 0x00000800,
1467 0xc798, 0x00ffffff, 0x00ff7fbf,
1468 0xc79c, 0x00ffffff, 0x00ff7faf,
1469 0x8c00, 0x000000ff, 0x00000800,
1470 0xe40, 0x00001fff, 0x00001fff,
1471 0x9060, 0x0000007f, 0x00000020,
1472 0x9508, 0x00010000, 0x00010000,
1473 0xae00, 0x00100000, 0x000ff07c,
1474 0xac14, 0x000003ff, 0x0000000f,
1475 0xac10, 0xffffffff, 0x7564fdec,
1476 0xac0c, 0xffffffff, 0x3120b9a8,
1477 0xac08, 0x20000000, 0x0f9c0000
1478};
1479
1480static const u32 hawaii_mgcg_cgcg_init[] =
1481{
1482 0xc420, 0xffffffff, 0xfffffffd,
1483 0x30800, 0xffffffff, 0xe0000000,
1484 0x3c2a0, 0xffffffff, 0x00000100,
1485 0x3c208, 0xffffffff, 0x00000100,
1486 0x3c2c0, 0xffffffff, 0x00000100,
1487 0x3c2c8, 0xffffffff, 0x00000100,
1488 0x3c2c4, 0xffffffff, 0x00000100,
1489 0x55e4, 0xffffffff, 0x00200100,
1490 0x3c280, 0xffffffff, 0x00000100,
1491 0x3c214, 0xffffffff, 0x06000100,
1492 0x3c220, 0xffffffff, 0x00000100,
1493 0x3c218, 0xffffffff, 0x06000100,
1494 0x3c204, 0xffffffff, 0x00000100,
1495 0x3c2e0, 0xffffffff, 0x00000100,
1496 0x3c224, 0xffffffff, 0x00000100,
1497 0x3c200, 0xffffffff, 0x00000100,
1498 0x3c230, 0xffffffff, 0x00000100,
1499 0x3c234, 0xffffffff, 0x00000100,
1500 0x3c250, 0xffffffff, 0x00000100,
1501 0x3c254, 0xffffffff, 0x00000100,
1502 0x3c258, 0xffffffff, 0x00000100,
1503 0x3c25c, 0xffffffff, 0x00000100,
1504 0x3c260, 0xffffffff, 0x00000100,
1505 0x3c27c, 0xffffffff, 0x00000100,
1506 0x3c278, 0xffffffff, 0x00000100,
1507 0x3c210, 0xffffffff, 0x06000100,
1508 0x3c290, 0xffffffff, 0x00000100,
1509 0x3c274, 0xffffffff, 0x00000100,
1510 0x3c2b4, 0xffffffff, 0x00000100,
1511 0x3c2b0, 0xffffffff, 0x00000100,
1512 0x3c270, 0xffffffff, 0x00000100,
1513 0x30800, 0xffffffff, 0xe0000000,
1514 0x3c020, 0xffffffff, 0x00010000,
1515 0x3c024, 0xffffffff, 0x00030002,
1516 0x3c028, 0xffffffff, 0x00040007,
1517 0x3c02c, 0xffffffff, 0x00060005,
1518 0x3c030, 0xffffffff, 0x00090008,
1519 0x3c034, 0xffffffff, 0x00010000,
1520 0x3c038, 0xffffffff, 0x00030002,
1521 0x3c03c, 0xffffffff, 0x00040007,
1522 0x3c040, 0xffffffff, 0x00060005,
1523 0x3c044, 0xffffffff, 0x00090008,
1524 0x3c048, 0xffffffff, 0x00010000,
1525 0x3c04c, 0xffffffff, 0x00030002,
1526 0x3c050, 0xffffffff, 0x00040007,
1527 0x3c054, 0xffffffff, 0x00060005,
1528 0x3c058, 0xffffffff, 0x00090008,
1529 0x3c05c, 0xffffffff, 0x00010000,
1530 0x3c060, 0xffffffff, 0x00030002,
1531 0x3c064, 0xffffffff, 0x00040007,
1532 0x3c068, 0xffffffff, 0x00060005,
1533 0x3c06c, 0xffffffff, 0x00090008,
1534 0x3c070, 0xffffffff, 0x00010000,
1535 0x3c074, 0xffffffff, 0x00030002,
1536 0x3c078, 0xffffffff, 0x00040007,
1537 0x3c07c, 0xffffffff, 0x00060005,
1538 0x3c080, 0xffffffff, 0x00090008,
1539 0x3c084, 0xffffffff, 0x00010000,
1540 0x3c088, 0xffffffff, 0x00030002,
1541 0x3c08c, 0xffffffff, 0x00040007,
1542 0x3c090, 0xffffffff, 0x00060005,
1543 0x3c094, 0xffffffff, 0x00090008,
1544 0x3c098, 0xffffffff, 0x00010000,
1545 0x3c09c, 0xffffffff, 0x00030002,
1546 0x3c0a0, 0xffffffff, 0x00040007,
1547 0x3c0a4, 0xffffffff, 0x00060005,
1548 0x3c0a8, 0xffffffff, 0x00090008,
1549 0x3c0ac, 0xffffffff, 0x00010000,
1550 0x3c0b0, 0xffffffff, 0x00030002,
1551 0x3c0b4, 0xffffffff, 0x00040007,
1552 0x3c0b8, 0xffffffff, 0x00060005,
1553 0x3c0bc, 0xffffffff, 0x00090008,
1554 0x3c0c0, 0xffffffff, 0x00010000,
1555 0x3c0c4, 0xffffffff, 0x00030002,
1556 0x3c0c8, 0xffffffff, 0x00040007,
1557 0x3c0cc, 0xffffffff, 0x00060005,
1558 0x3c0d0, 0xffffffff, 0x00090008,
1559 0x3c0d4, 0xffffffff, 0x00010000,
1560 0x3c0d8, 0xffffffff, 0x00030002,
1561 0x3c0dc, 0xffffffff, 0x00040007,
1562 0x3c0e0, 0xffffffff, 0x00060005,
1563 0x3c0e4, 0xffffffff, 0x00090008,
1564 0x3c0e8, 0xffffffff, 0x00010000,
1565 0x3c0ec, 0xffffffff, 0x00030002,
1566 0x3c0f0, 0xffffffff, 0x00040007,
1567 0x3c0f4, 0xffffffff, 0x00060005,
1568 0x3c0f8, 0xffffffff, 0x00090008,
1569 0xc318, 0xffffffff, 0x00020200,
1570 0x3350, 0xffffffff, 0x00000200,
1571 0x15c0, 0xffffffff, 0x00000400,
1572 0x55e8, 0xffffffff, 0x00000000,
1573 0x2f50, 0xffffffff, 0x00000902,
1574 0x3c000, 0xffffffff, 0x96940200,
1575 0x8708, 0xffffffff, 0x00900100,
1576 0xc424, 0xffffffff, 0x0020003f,
1577 0x38, 0xffffffff, 0x0140001c,
1578 0x3c, 0x000f0000, 0x000f0000,
1579 0x220, 0xffffffff, 0xc060000c,
1580 0x224, 0xc0000fff, 0x00000100,
1581 0xf90, 0xffffffff, 0x00000100,
1582 0xf98, 0x00000101, 0x00000000,
1583 0x20a8, 0xffffffff, 0x00000104,
1584 0x55e4, 0xff000fff, 0x00000100,
1585 0x30cc, 0xc0000fff, 0x00000104,
1586 0xc1e4, 0x00000001, 0x00000001,
1587 0xd00c, 0xff000ff0, 0x00000100,
1588 0xd80c, 0xff000ff0, 0x00000100
1589};
1590
1591static const u32 godavari_golden_registers[] =
1592{
1593 0x55e4, 0xff607fff, 0xfc000100,
1594 0x6ed8, 0x00010101, 0x00010000,
1595 0x9830, 0xffffffff, 0x00000000,
1596 0x98302, 0xf00fffff, 0x00000400,
1597 0x6130, 0xffffffff, 0x00010000,
1598 0x5bb0, 0x000000f0, 0x00000070,
1599 0x5bc0, 0xf0311fff, 0x80300000,
1600 0x98f8, 0x73773777, 0x12010001,
1601 0x98fc, 0xffffffff, 0x00000010,
1602 0x8030, 0x00001f0f, 0x0000100a,
1603 0x2f48, 0x73773777, 0x12010001,
1604 0x2408, 0x000fffff, 0x000c007f,
1605 0x8a14, 0xf000003f, 0x00000007,
1606 0x8b24, 0xffffffff, 0x00ff0fff,
1607 0x30a04, 0x0000ff0f, 0x00000000,
1608 0x28a4c, 0x07ffffff, 0x06000000,
1609 0x4d8, 0x00000fff, 0x00000100,
1610 0xd014, 0x00010000, 0x00810001,
1611 0xd814, 0x00010000, 0x00810001,
1612 0x3e78, 0x00000001, 0x00000002,
1613 0xc768, 0x00000008, 0x00000008,
1614 0xc770, 0x00000f00, 0x00000800,
1615 0xc774, 0x00000f00, 0x00000800,
1616 0xc798, 0x00ffffff, 0x00ff7fbf,
1617 0xc79c, 0x00ffffff, 0x00ff7faf,
1618 0x8c00, 0x000000ff, 0x00000001,
1619 0x214f8, 0x01ff01ff, 0x00000002,
1620 0x21498, 0x007ff800, 0x00200000,
1621 0x2015c, 0xffffffff, 0x00000f40,
1622 0x88c4, 0x001f3ae3, 0x00000082,
1623 0x88d4, 0x0000001f, 0x00000010,
1624 0x30934, 0xffffffff, 0x00000000
1625};
1626
1627
1628static void cik_init_golden_registers(struct radeon_device *rdev)
1629{
1630 switch (rdev->family) {
1631 case CHIP_BONAIRE:
1632 radeon_program_register_sequence(rdev,
1633 bonaire_mgcg_cgcg_init,
1634 (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
1635 radeon_program_register_sequence(rdev,
1636 bonaire_golden_registers,
1637 (const u32)ARRAY_SIZE(bonaire_golden_registers));
1638 radeon_program_register_sequence(rdev,
1639 bonaire_golden_common_registers,
1640 (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
1641 radeon_program_register_sequence(rdev,
1642 bonaire_golden_spm_registers,
1643 (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
1644 break;
1645 case CHIP_KABINI:
1646 radeon_program_register_sequence(rdev,
1647 kalindi_mgcg_cgcg_init,
1648 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
1649 radeon_program_register_sequence(rdev,
1650 kalindi_golden_registers,
1651 (const u32)ARRAY_SIZE(kalindi_golden_registers));
1652 radeon_program_register_sequence(rdev,
1653 kalindi_golden_common_registers,
1654 (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
1655 radeon_program_register_sequence(rdev,
1656 kalindi_golden_spm_registers,
1657 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
1658 break;
1659 case CHIP_MULLINS:
1660 radeon_program_register_sequence(rdev,
1661 kalindi_mgcg_cgcg_init,
1662 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
1663 radeon_program_register_sequence(rdev,
1664 godavari_golden_registers,
1665 (const u32)ARRAY_SIZE(godavari_golden_registers));
1666 radeon_program_register_sequence(rdev,
1667 kalindi_golden_common_registers,
1668 (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
1669 radeon_program_register_sequence(rdev,
1670 kalindi_golden_spm_registers,
1671 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
1672 break;
1673 case CHIP_KAVERI:
1674 radeon_program_register_sequence(rdev,
1675 spectre_mgcg_cgcg_init,
1676 (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
1677 radeon_program_register_sequence(rdev,
1678 spectre_golden_registers,
1679 (const u32)ARRAY_SIZE(spectre_golden_registers));
1680 radeon_program_register_sequence(rdev,
1681 spectre_golden_common_registers,
1682 (const u32)ARRAY_SIZE(spectre_golden_common_registers));
1683 radeon_program_register_sequence(rdev,
1684 spectre_golden_spm_registers,
1685 (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
1686 break;
1687 case CHIP_HAWAII:
1688 radeon_program_register_sequence(rdev,
1689 hawaii_mgcg_cgcg_init,
1690 (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
1691 radeon_program_register_sequence(rdev,
1692 hawaii_golden_registers,
1693 (const u32)ARRAY_SIZE(hawaii_golden_registers));
1694 radeon_program_register_sequence(rdev,
1695 hawaii_golden_common_registers,
1696 (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
1697 radeon_program_register_sequence(rdev,
1698 hawaii_golden_spm_registers,
1699 (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
1700 break;
1701 default:
1702 break;
1703 }
1704}
1705
1706/**
1707 * cik_get_xclk - get the xclk
1708 *
1709 * @rdev: radeon_device pointer
1710 *
1711 * Returns the reference clock used by the gfx engine
1712 * (CIK).
1713 */
1714u32 cik_get_xclk(struct radeon_device *rdev)
1715{
1716 u32 reference_clock = rdev->clock.spll.reference_freq;
1717
1718 if (rdev->flags & RADEON_IS_IGP) {
1719 if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK)
1720 return reference_clock / 2;
1721 } else {
1722 if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE)
1723 return reference_clock / 4;
1724 }
1725 return reference_clock;
1726}
1727
1728/**
1729 * cik_mm_rdoorbell - read a doorbell dword
1730 *
1731 * @rdev: radeon_device pointer
1732 * @index: doorbell index
1733 *
1734 * Returns the value in the doorbell aperture at the
1735 * requested doorbell index (CIK).
1736 */
1737u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index)
1738{
1739 if (index < rdev->doorbell.num_doorbells) {
1740 return readl(rdev->doorbell.ptr + index);
1741 } else {
1742 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
1743 return 0;
1744 }
1745}
1746
1747/**
1748 * cik_mm_wdoorbell - write a doorbell dword
1749 *
1750 * @rdev: radeon_device pointer
1751 * @index: doorbell index
1752 * @v: value to write
1753 *
1754 * Writes @v to the doorbell aperture at the
1755 * requested doorbell index (CIK).
1756 */
1757void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v)
1758{
1759 if (index < rdev->doorbell.num_doorbells) {
1760 writel(v, rdev->doorbell.ptr + index);
1761 } else {
1762 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
1763 }
1764}
1765
1766#define BONAIRE_IO_MC_REGS_SIZE 36
1767
1768static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =
1769{
1770 {0x00000070, 0x04400000},
1771 {0x00000071, 0x80c01803},
1772 {0x00000072, 0x00004004},
1773 {0x00000073, 0x00000100},
1774 {0x00000074, 0x00ff0000},
1775 {0x00000075, 0x34000000},
1776 {0x00000076, 0x08000014},
1777 {0x00000077, 0x00cc08ec},
1778 {0x00000078, 0x00000400},
1779 {0x00000079, 0x00000000},
1780 {0x0000007a, 0x04090000},
1781 {0x0000007c, 0x00000000},
1782 {0x0000007e, 0x4408a8e8},
1783 {0x0000007f, 0x00000304},
1784 {0x00000080, 0x00000000},
1785 {0x00000082, 0x00000001},
1786 {0x00000083, 0x00000002},
1787 {0x00000084, 0xf3e4f400},
1788 {0x00000085, 0x052024e3},
1789 {0x00000087, 0x00000000},
1790 {0x00000088, 0x01000000},
1791 {0x0000008a, 0x1c0a0000},
1792 {0x0000008b, 0xff010000},
1793 {0x0000008d, 0xffffefff},
1794 {0x0000008e, 0xfff3efff},
1795 {0x0000008f, 0xfff3efbf},
1796 {0x00000092, 0xf7ffffff},
1797 {0x00000093, 0xffffff7f},
1798 {0x00000095, 0x00101101},
1799 {0x00000096, 0x00000fff},
1800 {0x00000097, 0x00116fff},
1801 {0x00000098, 0x60010000},
1802 {0x00000099, 0x10010000},
1803 {0x0000009a, 0x00006000},
1804 {0x0000009b, 0x00001000},
1805 {0x0000009f, 0x00b48000}
1806};
1807
1808#define HAWAII_IO_MC_REGS_SIZE 22
1809
1810static const u32 hawaii_io_mc_regs[HAWAII_IO_MC_REGS_SIZE][2] =
1811{
1812 {0x0000007d, 0x40000000},
1813 {0x0000007e, 0x40180304},
1814 {0x0000007f, 0x0000ff00},
1815 {0x00000081, 0x00000000},
1816 {0x00000083, 0x00000800},
1817 {0x00000086, 0x00000000},
1818 {0x00000087, 0x00000100},
1819 {0x00000088, 0x00020100},
1820 {0x00000089, 0x00000000},
1821 {0x0000008b, 0x00040000},
1822 {0x0000008c, 0x00000100},
1823 {0x0000008e, 0xff010000},
1824 {0x00000090, 0xffffefff},
1825 {0x00000091, 0xfff3efff},
1826 {0x00000092, 0xfff3efbf},
1827 {0x00000093, 0xf7ffffff},
1828 {0x00000094, 0xffffff7f},
1829 {0x00000095, 0x00000fff},
1830 {0x00000096, 0x00116fff},
1831 {0x00000097, 0x60010000},
1832 {0x00000098, 0x10010000},
1833 {0x0000009f, 0x00c79000}
1834};
1835
1836
1837/**
1838 * cik_srbm_select - select specific register instances
1839 *
1840 * @rdev: radeon_device pointer
1841 * @me: selected ME (micro engine)
1842 * @pipe: pipe
1843 * @queue: queue
1844 * @vmid: VMID
1845 *
1846 * Switches the currently active registers instances. Some
1847 * registers are instanced per VMID, others are instanced per
1848 * me/pipe/queue combination.
1849 */
1850static void cik_srbm_select(struct radeon_device *rdev,
1851 u32 me, u32 pipe, u32 queue, u32 vmid)
1852{
1853 u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) |
1854 MEID(me & 0x3) |
1855 VMID(vmid & 0xf) |
1856 QUEUEID(queue & 0x7));
1857 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl);
1858}
1859
1860/* ucode loading */
1861/**
1862 * ci_mc_load_microcode - load MC ucode into the hw
1863 *
1864 * @rdev: radeon_device pointer
1865 *
1866 * Load the GDDR MC ucode into the hw (CIK).
1867 * Returns 0 on success, error on failure.
1868 */
1869int ci_mc_load_microcode(struct radeon_device *rdev)
1870{
1871 const __be32 *fw_data = NULL;
1872 const __le32 *new_fw_data = NULL;
1873 u32 running, tmp;
1874 u32 *io_mc_regs = NULL;
1875 const __le32 *new_io_mc_regs = NULL;
1876 int i, regs_size, ucode_size;
1877
1878 if (!rdev->mc_fw)
1879 return -EINVAL;
1880
1881 if (rdev->new_fw) {
1882 const struct mc_firmware_header_v1_0 *hdr =
1883 (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data;
1884
1885 radeon_ucode_print_mc_hdr(&hdr->header);
1886
1887 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
1888 new_io_mc_regs = (const __le32 *)
1889 (rdev->mc_fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
1890 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1891 new_fw_data = (const __le32 *)
1892 (rdev->mc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1893 } else {
1894 ucode_size = rdev->mc_fw->size / 4;
1895
1896 switch (rdev->family) {
1897 case CHIP_BONAIRE:
1898 io_mc_regs = (u32 *)&bonaire_io_mc_regs;
1899 regs_size = BONAIRE_IO_MC_REGS_SIZE;
1900 break;
1901 case CHIP_HAWAII:
1902 io_mc_regs = (u32 *)&hawaii_io_mc_regs;
1903 regs_size = HAWAII_IO_MC_REGS_SIZE;
1904 break;
1905 default:
1906 return -EINVAL;
1907 }
1908 fw_data = (const __be32 *)rdev->mc_fw->data;
1909 }
1910
1911 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
1912
1913 if (running == 0) {
1914 /* reset the engine and set to writable */
1915 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1916 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
1917
1918 /* load mc io regs */
1919 for (i = 0; i < regs_size; i++) {
1920 if (rdev->new_fw) {
1921 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
1922 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
1923 } else {
1924 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
1925 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
1926 }
1927 }
1928
1929 tmp = RREG32(MC_SEQ_MISC0);
1930 if ((rdev->pdev->device == 0x6649) && ((tmp & 0xff00) == 0x5600)) {
1931 WREG32(MC_SEQ_IO_DEBUG_INDEX, 5);
1932 WREG32(MC_SEQ_IO_DEBUG_DATA, 0x00000023);
1933 WREG32(MC_SEQ_IO_DEBUG_INDEX, 9);
1934 WREG32(MC_SEQ_IO_DEBUG_DATA, 0x000001f0);
1935 }
1936
1937 /* load the MC ucode */
1938 for (i = 0; i < ucode_size; i++) {
1939 if (rdev->new_fw)
1940 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
1941 else
1942 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
1943 }
1944
1945 /* put the engine back into the active state */
1946 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1947 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
1948 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
1949
1950 /* wait for training to complete */
1951 for (i = 0; i < rdev->usec_timeout; i++) {
1952 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
1953 break;
1954 udelay(1);
1955 }
1956 for (i = 0; i < rdev->usec_timeout; i++) {
1957 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
1958 break;
1959 udelay(1);
1960 }
1961 }
1962
1963 return 0;
1964}
1965
1966/**
1967 * cik_init_microcode - load ucode images from disk
1968 *
1969 * @rdev: radeon_device pointer
1970 *
1971 * Use the firmware interface to load the ucode images into
1972 * the driver (not loaded into hw).
1973 * Returns 0 on success, error on failure.
1974 */
1975static int cik_init_microcode(struct radeon_device *rdev)
1976{
1977 const char *chip_name;
1978 const char *new_chip_name;
1979 size_t pfp_req_size, me_req_size, ce_req_size,
1980 mec_req_size, rlc_req_size, mc_req_size = 0,
1981 sdma_req_size, smc_req_size = 0, mc2_req_size = 0;
1982 char fw_name[30];
1983 int new_fw = 0;
1984 int err;
1985 int num_fw;
1986 bool new_smc = false;
1987
1988 DRM_DEBUG("\n");
1989
1990 switch (rdev->family) {
1991 case CHIP_BONAIRE:
1992 chip_name = "BONAIRE";
1993 if ((rdev->pdev->revision == 0x80) ||
1994 (rdev->pdev->revision == 0x81) ||
1995 (rdev->pdev->device == 0x665f))
1996 new_smc = true;
1997 new_chip_name = "bonaire";
1998 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1999 me_req_size = CIK_ME_UCODE_SIZE * 4;
2000 ce_req_size = CIK_CE_UCODE_SIZE * 4;
2001 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2002 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
2003 mc_req_size = BONAIRE_MC_UCODE_SIZE * 4;
2004 mc2_req_size = BONAIRE_MC2_UCODE_SIZE * 4;
2005 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2006 smc_req_size = ALIGN(BONAIRE_SMC_UCODE_SIZE, 4);
2007 num_fw = 8;
2008 break;
2009 case CHIP_HAWAII:
2010 chip_name = "HAWAII";
2011 if (rdev->pdev->revision == 0x80)
2012 new_smc = true;
2013 new_chip_name = "hawaii";
2014 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
2015 me_req_size = CIK_ME_UCODE_SIZE * 4;
2016 ce_req_size = CIK_CE_UCODE_SIZE * 4;
2017 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2018 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
2019 mc_req_size = HAWAII_MC_UCODE_SIZE * 4;
2020 mc2_req_size = HAWAII_MC2_UCODE_SIZE * 4;
2021 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2022 smc_req_size = ALIGN(HAWAII_SMC_UCODE_SIZE, 4);
2023 num_fw = 8;
2024 break;
2025 case CHIP_KAVERI:
2026 chip_name = "KAVERI";
2027 new_chip_name = "kaveri";
2028 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
2029 me_req_size = CIK_ME_UCODE_SIZE * 4;
2030 ce_req_size = CIK_CE_UCODE_SIZE * 4;
2031 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2032 rlc_req_size = KV_RLC_UCODE_SIZE * 4;
2033 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2034 num_fw = 7;
2035 break;
2036 case CHIP_KABINI:
2037 chip_name = "KABINI";
2038 new_chip_name = "kabini";
2039 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
2040 me_req_size = CIK_ME_UCODE_SIZE * 4;
2041 ce_req_size = CIK_CE_UCODE_SIZE * 4;
2042 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2043 rlc_req_size = KB_RLC_UCODE_SIZE * 4;
2044 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2045 num_fw = 6;
2046 break;
2047 case CHIP_MULLINS:
2048 chip_name = "MULLINS";
2049 new_chip_name = "mullins";
2050 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
2051 me_req_size = CIK_ME_UCODE_SIZE * 4;
2052 ce_req_size = CIK_CE_UCODE_SIZE * 4;
2053 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2054 rlc_req_size = ML_RLC_UCODE_SIZE * 4;
2055 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2056 num_fw = 6;
2057 break;
2058 default: BUG();
2059 }
2060
2061 DRM_INFO("Loading %s Microcode\n", new_chip_name);
2062
2063 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", new_chip_name);
2064 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2065 if (err) {
2066 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2067 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2068 if (err)
2069 goto out;
2070 if (rdev->pfp_fw->size != pfp_req_size) {
2071 pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n",
2072 rdev->pfp_fw->size, fw_name);
2073 err = -EINVAL;
2074 goto out;
2075 }
2076 } else {
2077 err = radeon_ucode_validate(rdev->pfp_fw);
2078 if (err) {
2079 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2080 fw_name);
2081 goto out;
2082 } else {
2083 new_fw++;
2084 }
2085 }
2086
2087 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", new_chip_name);
2088 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
2089 if (err) {
2090 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2091 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
2092 if (err)
2093 goto out;
2094 if (rdev->me_fw->size != me_req_size) {
2095 pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n",
2096 rdev->me_fw->size, fw_name);
2097 err = -EINVAL;
2098 }
2099 } else {
2100 err = radeon_ucode_validate(rdev->me_fw);
2101 if (err) {
2102 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2103 fw_name);
2104 goto out;
2105 } else {
2106 new_fw++;
2107 }
2108 }
2109
2110 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", new_chip_name);
2111 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
2112 if (err) {
2113 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
2114 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
2115 if (err)
2116 goto out;
2117 if (rdev->ce_fw->size != ce_req_size) {
2118 pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n",
2119 rdev->ce_fw->size, fw_name);
2120 err = -EINVAL;
2121 }
2122 } else {
2123 err = radeon_ucode_validate(rdev->ce_fw);
2124 if (err) {
2125 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2126 fw_name);
2127 goto out;
2128 } else {
2129 new_fw++;
2130 }
2131 }
2132
2133 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", new_chip_name);
2134 err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev);
2135 if (err) {
2136 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
2137 err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev);
2138 if (err)
2139 goto out;
2140 if (rdev->mec_fw->size != mec_req_size) {
2141 pr_err("cik_cp: Bogus length %zu in firmware \"%s\"\n",
2142 rdev->mec_fw->size, fw_name);
2143 err = -EINVAL;
2144 }
2145 } else {
2146 err = radeon_ucode_validate(rdev->mec_fw);
2147 if (err) {
2148 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2149 fw_name);
2150 goto out;
2151 } else {
2152 new_fw++;
2153 }
2154 }
2155
2156 if (rdev->family == CHIP_KAVERI) {
2157 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", new_chip_name);
2158 err = request_firmware(&rdev->mec2_fw, fw_name, rdev->dev);
2159 if (err) {
2160 goto out;
2161 } else {
2162 err = radeon_ucode_validate(rdev->mec2_fw);
2163 if (err) {
2164 goto out;
2165 } else {
2166 new_fw++;
2167 }
2168 }
2169 }
2170
2171 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", new_chip_name);
2172 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2173 if (err) {
2174 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
2175 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2176 if (err)
2177 goto out;
2178 if (rdev->rlc_fw->size != rlc_req_size) {
2179 pr_err("cik_rlc: Bogus length %zu in firmware \"%s\"\n",
2180 rdev->rlc_fw->size, fw_name);
2181 err = -EINVAL;
2182 }
2183 } else {
2184 err = radeon_ucode_validate(rdev->rlc_fw);
2185 if (err) {
2186 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2187 fw_name);
2188 goto out;
2189 } else {
2190 new_fw++;
2191 }
2192 }
2193
2194 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", new_chip_name);
2195 err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev);
2196 if (err) {
2197 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
2198 err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev);
2199 if (err)
2200 goto out;
2201 if (rdev->sdma_fw->size != sdma_req_size) {
2202 pr_err("cik_sdma: Bogus length %zu in firmware \"%s\"\n",
2203 rdev->sdma_fw->size, fw_name);
2204 err = -EINVAL;
2205 }
2206 } else {
2207 err = radeon_ucode_validate(rdev->sdma_fw);
2208 if (err) {
2209 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2210 fw_name);
2211 goto out;
2212 } else {
2213 new_fw++;
2214 }
2215 }
2216
2217 /* No SMC, MC ucode on APUs */
2218 if (!(rdev->flags & RADEON_IS_IGP)) {
2219 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", new_chip_name);
2220 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
2221 if (err) {
2222 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name);
2223 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
2224 if (err) {
2225 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
2226 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
2227 if (err)
2228 goto out;
2229 }
2230 if ((rdev->mc_fw->size != mc_req_size) &&
2231 (rdev->mc_fw->size != mc2_req_size)){
2232 pr_err("cik_mc: Bogus length %zu in firmware \"%s\"\n",
2233 rdev->mc_fw->size, fw_name);
2234 err = -EINVAL;
2235 }
2236 DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
2237 } else {
2238 err = radeon_ucode_validate(rdev->mc_fw);
2239 if (err) {
2240 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2241 fw_name);
2242 goto out;
2243 } else {
2244 new_fw++;
2245 }
2246 }
2247
2248 if (new_smc)
2249 snprintf(fw_name, sizeof(fw_name), "radeon/%s_k_smc.bin", new_chip_name);
2250 else
2251 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", new_chip_name);
2252 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2253 if (err) {
2254 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
2255 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2256 if (err) {
2257 pr_err("smc: error loading firmware \"%s\"\n",
2258 fw_name);
2259 release_firmware(rdev->smc_fw);
2260 rdev->smc_fw = NULL;
2261 err = 0;
2262 } else if (rdev->smc_fw->size != smc_req_size) {
2263 pr_err("cik_smc: Bogus length %zu in firmware \"%s\"\n",
2264 rdev->smc_fw->size, fw_name);
2265 err = -EINVAL;
2266 }
2267 } else {
2268 err = radeon_ucode_validate(rdev->smc_fw);
2269 if (err) {
2270 pr_err("cik_fw: validation failed for firmware \"%s\"\n",
2271 fw_name);
2272 goto out;
2273 } else {
2274 new_fw++;
2275 }
2276 }
2277 }
2278
2279 if (new_fw == 0) {
2280 rdev->new_fw = false;
2281 } else if (new_fw < num_fw) {
2282 pr_err("ci_fw: mixing new and old firmware!\n");
2283 err = -EINVAL;
2284 } else {
2285 rdev->new_fw = true;
2286 }
2287
2288out:
2289 if (err) {
2290 if (err != -EINVAL)
2291 pr_err("cik_cp: Failed to load firmware \"%s\"\n",
2292 fw_name);
2293 release_firmware(rdev->pfp_fw);
2294 rdev->pfp_fw = NULL;
2295 release_firmware(rdev->me_fw);
2296 rdev->me_fw = NULL;
2297 release_firmware(rdev->ce_fw);
2298 rdev->ce_fw = NULL;
2299 release_firmware(rdev->mec_fw);
2300 rdev->mec_fw = NULL;
2301 release_firmware(rdev->mec2_fw);
2302 rdev->mec2_fw = NULL;
2303 release_firmware(rdev->rlc_fw);
2304 rdev->rlc_fw = NULL;
2305 release_firmware(rdev->sdma_fw);
2306 rdev->sdma_fw = NULL;
2307 release_firmware(rdev->mc_fw);
2308 rdev->mc_fw = NULL;
2309 release_firmware(rdev->smc_fw);
2310 rdev->smc_fw = NULL;
2311 }
2312 return err;
2313}
2314
2315/*
2316 * Core functions
2317 */
2318/**
2319 * cik_tiling_mode_table_init - init the hw tiling table
2320 *
2321 * @rdev: radeon_device pointer
2322 *
2323 * Starting with SI, the tiling setup is done globally in a
2324 * set of 32 tiling modes. Rather than selecting each set of
2325 * parameters per surface as on older asics, we just select
2326 * which index in the tiling table we want to use, and the
2327 * surface uses those parameters (CIK).
2328 */
2329static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2330{
2331 u32 *tile = rdev->config.cik.tile_mode_array;
2332 u32 *macrotile = rdev->config.cik.macrotile_mode_array;
2333 const u32 num_tile_mode_states =
2334 ARRAY_SIZE(rdev->config.cik.tile_mode_array);
2335 const u32 num_secondary_tile_mode_states =
2336 ARRAY_SIZE(rdev->config.cik.macrotile_mode_array);
2337 u32 reg_offset, split_equal_to_row_size;
2338 u32 num_pipe_configs;
2339 u32 num_rbs = rdev->config.cik.max_backends_per_se *
2340 rdev->config.cik.max_shader_engines;
2341
2342 switch (rdev->config.cik.mem_row_size_in_kb) {
2343 case 1:
2344 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
2345 break;
2346 case 2:
2347 default:
2348 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
2349 break;
2350 case 4:
2351 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
2352 break;
2353 }
2354
2355 num_pipe_configs = rdev->config.cik.max_tile_pipes;
2356 if (num_pipe_configs > 8)
2357 num_pipe_configs = 16;
2358
2359 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2360 tile[reg_offset] = 0;
2361 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2362 macrotile[reg_offset] = 0;
2363
2364 switch(num_pipe_configs) {
2365 case 16:
2366 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2367 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2368 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2369 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2370 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2371 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2372 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2373 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2374 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2375 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2376 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2377 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2378 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2379 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2380 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2381 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2382 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2383 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2384 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2385 TILE_SPLIT(split_equal_to_row_size));
2386 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2387 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2388 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2389 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2390 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2391 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2392 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2393 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2394 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2395 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2396 TILE_SPLIT(split_equal_to_row_size));
2397 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2398 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2399 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2400 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2401 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2402 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2403 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2404 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2405 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2406 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2407 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2408 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2409 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2410 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2411 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2412 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2413 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2414 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2415 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2416 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2417 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2418 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2419 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2420 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2421 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2422 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2423 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2424 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2425 tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2426 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2427 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2428 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2429 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2430 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2431 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2432 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2433 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2434 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2435 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2436 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2437 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2438 PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2439 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2440 tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2441 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2442 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2443 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2444
2445 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2446 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2447 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2448 NUM_BANKS(ADDR_SURF_16_BANK));
2449 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2450 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2451 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2452 NUM_BANKS(ADDR_SURF_16_BANK));
2453 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2454 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2455 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2456 NUM_BANKS(ADDR_SURF_16_BANK));
2457 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2458 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2459 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2460 NUM_BANKS(ADDR_SURF_16_BANK));
2461 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2462 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2463 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2464 NUM_BANKS(ADDR_SURF_8_BANK));
2465 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2466 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2467 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2468 NUM_BANKS(ADDR_SURF_4_BANK));
2469 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2470 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2471 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2472 NUM_BANKS(ADDR_SURF_2_BANK));
2473 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2474 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2475 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2476 NUM_BANKS(ADDR_SURF_16_BANK));
2477 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2478 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2479 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2480 NUM_BANKS(ADDR_SURF_16_BANK));
2481 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2482 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2483 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2484 NUM_BANKS(ADDR_SURF_16_BANK));
2485 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2486 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2487 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2488 NUM_BANKS(ADDR_SURF_8_BANK));
2489 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2490 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2491 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2492 NUM_BANKS(ADDR_SURF_4_BANK));
2493 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2496 NUM_BANKS(ADDR_SURF_2_BANK));
2497 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2498 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2499 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2500 NUM_BANKS(ADDR_SURF_2_BANK));
2501
2502 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2503 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2504 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2505 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
2506 break;
2507
2508 case 8:
2509 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2510 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2511 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2512 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2513 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2514 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2515 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2516 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2517 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2518 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2519 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2520 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2521 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2522 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2523 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2524 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2525 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2526 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2527 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2528 TILE_SPLIT(split_equal_to_row_size));
2529 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2530 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2531 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2532 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2533 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2534 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2535 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2536 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2537 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2538 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2539 TILE_SPLIT(split_equal_to_row_size));
2540 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2541 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2542 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2543 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2544 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2545 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2546 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2547 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2548 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2549 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2550 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2551 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2552 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2553 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2554 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2555 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2556 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2557 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2558 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2559 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2560 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2561 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2562 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2563 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2564 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2565 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2566 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2567 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2568 tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2569 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2570 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2571 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2572 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2573 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2574 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2575 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2576 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2577 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2578 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2579 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2580 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2581 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2582 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2583 tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2584 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2585 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2586 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2587
2588 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2589 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2590 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2591 NUM_BANKS(ADDR_SURF_16_BANK));
2592 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2593 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2594 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2595 NUM_BANKS(ADDR_SURF_16_BANK));
2596 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2597 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2598 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2599 NUM_BANKS(ADDR_SURF_16_BANK));
2600 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2601 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2602 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2603 NUM_BANKS(ADDR_SURF_16_BANK));
2604 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2605 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2606 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2607 NUM_BANKS(ADDR_SURF_8_BANK));
2608 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2609 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2610 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2611 NUM_BANKS(ADDR_SURF_4_BANK));
2612 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2613 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2614 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2615 NUM_BANKS(ADDR_SURF_2_BANK));
2616 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2617 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2618 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2619 NUM_BANKS(ADDR_SURF_16_BANK));
2620 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2621 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2622 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2623 NUM_BANKS(ADDR_SURF_16_BANK));
2624 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2625 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2626 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2627 NUM_BANKS(ADDR_SURF_16_BANK));
2628 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2629 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2630 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2631 NUM_BANKS(ADDR_SURF_16_BANK));
2632 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2633 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2634 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2635 NUM_BANKS(ADDR_SURF_8_BANK));
2636 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2637 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2638 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2639 NUM_BANKS(ADDR_SURF_4_BANK));
2640 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2641 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2642 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2643 NUM_BANKS(ADDR_SURF_2_BANK));
2644
2645 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2646 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2647 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2648 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
2649 break;
2650
2651 case 4:
2652 if (num_rbs == 4) {
2653 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2654 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2655 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2656 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2657 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2658 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2659 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2660 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2661 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2662 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2663 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2664 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2665 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2666 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2667 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2668 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2669 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2670 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2671 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2672 TILE_SPLIT(split_equal_to_row_size));
2673 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2674 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2675 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2676 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2677 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2678 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2679 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2680 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2681 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2682 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2683 TILE_SPLIT(split_equal_to_row_size));
2684 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2685 PIPE_CONFIG(ADDR_SURF_P4_16x16));
2686 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2687 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2688 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2689 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2690 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2691 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2692 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2693 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2694 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2695 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2696 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2697 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2698 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2699 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2700 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2701 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2702 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2703 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2704 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2705 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2706 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2707 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2708 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2709 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2710 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2711 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2712 tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2713 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2714 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2715 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2716 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2717 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2718 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2719 tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2720 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2721 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2722 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2723 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2724 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2725 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2726 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2727 tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2728 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2729 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2730 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2731
2732 } else if (num_rbs < 4) {
2733 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2734 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2735 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2736 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2737 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2738 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2739 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2740 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2741 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2742 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2743 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2744 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2745 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2746 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2747 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2748 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2749 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2750 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2751 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2752 TILE_SPLIT(split_equal_to_row_size));
2753 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2754 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2755 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2756 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2757 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2758 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2759 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2760 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2761 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2762 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2763 TILE_SPLIT(split_equal_to_row_size));
2764 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2765 PIPE_CONFIG(ADDR_SURF_P4_8x16));
2766 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2767 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2768 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2769 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2770 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2771 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2772 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2773 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2774 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2775 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2776 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2777 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2778 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2779 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2780 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2781 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2782 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2783 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2784 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2785 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2786 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2787 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2788 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2789 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2790 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2791 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2792 tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2793 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2794 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2795 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2796 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2797 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2798 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2799 tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2800 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2801 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2802 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2803 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2804 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2805 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2806 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2807 tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2808 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2809 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2810 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2811 }
2812
2813 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2814 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2815 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2816 NUM_BANKS(ADDR_SURF_16_BANK));
2817 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2818 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2819 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2820 NUM_BANKS(ADDR_SURF_16_BANK));
2821 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2822 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2823 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2824 NUM_BANKS(ADDR_SURF_16_BANK));
2825 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2826 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2827 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2828 NUM_BANKS(ADDR_SURF_16_BANK));
2829 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2830 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2831 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2832 NUM_BANKS(ADDR_SURF_16_BANK));
2833 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2834 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2835 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2836 NUM_BANKS(ADDR_SURF_8_BANK));
2837 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2838 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2839 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2840 NUM_BANKS(ADDR_SURF_4_BANK));
2841 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2842 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2843 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2844 NUM_BANKS(ADDR_SURF_16_BANK));
2845 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2846 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2847 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2848 NUM_BANKS(ADDR_SURF_16_BANK));
2849 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2850 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2851 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2852 NUM_BANKS(ADDR_SURF_16_BANK));
2853 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2854 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2855 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2856 NUM_BANKS(ADDR_SURF_16_BANK));
2857 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2858 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2859 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2860 NUM_BANKS(ADDR_SURF_16_BANK));
2861 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2862 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2863 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2864 NUM_BANKS(ADDR_SURF_8_BANK));
2865 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2866 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2867 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2868 NUM_BANKS(ADDR_SURF_4_BANK));
2869
2870 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2871 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2872 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2873 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
2874 break;
2875
2876 case 2:
2877 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2878 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2879 PIPE_CONFIG(ADDR_SURF_P2) |
2880 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2881 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2882 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2883 PIPE_CONFIG(ADDR_SURF_P2) |
2884 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2885 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2886 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2887 PIPE_CONFIG(ADDR_SURF_P2) |
2888 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2889 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2890 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2891 PIPE_CONFIG(ADDR_SURF_P2) |
2892 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2893 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2894 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2895 PIPE_CONFIG(ADDR_SURF_P2) |
2896 TILE_SPLIT(split_equal_to_row_size));
2897 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2898 PIPE_CONFIG(ADDR_SURF_P2) |
2899 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2900 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2901 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2902 PIPE_CONFIG(ADDR_SURF_P2) |
2903 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2904 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2905 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2906 PIPE_CONFIG(ADDR_SURF_P2) |
2907 TILE_SPLIT(split_equal_to_row_size));
2908 tile[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2909 PIPE_CONFIG(ADDR_SURF_P2);
2910 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2911 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2912 PIPE_CONFIG(ADDR_SURF_P2));
2913 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2914 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2915 PIPE_CONFIG(ADDR_SURF_P2) |
2916 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2917 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2918 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2919 PIPE_CONFIG(ADDR_SURF_P2) |
2920 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2921 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2922 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2923 PIPE_CONFIG(ADDR_SURF_P2) |
2924 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2925 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2926 PIPE_CONFIG(ADDR_SURF_P2) |
2927 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2928 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2929 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2930 PIPE_CONFIG(ADDR_SURF_P2) |
2931 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2932 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2933 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2934 PIPE_CONFIG(ADDR_SURF_P2) |
2935 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2936 tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2937 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2938 PIPE_CONFIG(ADDR_SURF_P2) |
2939 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2940 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2941 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2942 PIPE_CONFIG(ADDR_SURF_P2));
2943 tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2944 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2945 PIPE_CONFIG(ADDR_SURF_P2) |
2946 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2947 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2948 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2949 PIPE_CONFIG(ADDR_SURF_P2) |
2950 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2951 tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2952 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2953 PIPE_CONFIG(ADDR_SURF_P2) |
2954 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2955
2956 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2957 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2958 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2959 NUM_BANKS(ADDR_SURF_16_BANK));
2960 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2961 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2962 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2963 NUM_BANKS(ADDR_SURF_16_BANK));
2964 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2965 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2966 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2967 NUM_BANKS(ADDR_SURF_16_BANK));
2968 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2969 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2970 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2971 NUM_BANKS(ADDR_SURF_16_BANK));
2972 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2973 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2974 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2975 NUM_BANKS(ADDR_SURF_16_BANK));
2976 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2977 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2978 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2979 NUM_BANKS(ADDR_SURF_16_BANK));
2980 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2981 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2982 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2983 NUM_BANKS(ADDR_SURF_8_BANK));
2984 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2985 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2986 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2987 NUM_BANKS(ADDR_SURF_16_BANK));
2988 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2989 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2990 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2991 NUM_BANKS(ADDR_SURF_16_BANK));
2992 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2993 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2994 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2995 NUM_BANKS(ADDR_SURF_16_BANK));
2996 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2997 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2998 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2999 NUM_BANKS(ADDR_SURF_16_BANK));
3000 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3001 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3002 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3003 NUM_BANKS(ADDR_SURF_16_BANK));
3004 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3005 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3006 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3007 NUM_BANKS(ADDR_SURF_16_BANK));
3008 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3009 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3010 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3011 NUM_BANKS(ADDR_SURF_8_BANK));
3012
3013 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3014 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
3015 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3016 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
3017 break;
3018
3019 default:
3020 DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
3021 }
3022}
3023
3024/**
3025 * cik_select_se_sh - select which SE, SH to address
3026 *
3027 * @rdev: radeon_device pointer
3028 * @se_num: shader engine to address
3029 * @sh_num: sh block to address
3030 *
3031 * Select which SE, SH combinations to address. Certain
3032 * registers are instanced per SE or SH. 0xffffffff means
3033 * broadcast to all SEs or SHs (CIK).
3034 */
3035static void cik_select_se_sh(struct radeon_device *rdev,
3036 u32 se_num, u32 sh_num)
3037{
3038 u32 data = INSTANCE_BROADCAST_WRITES;
3039
3040 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
3041 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
3042 else if (se_num == 0xffffffff)
3043 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
3044 else if (sh_num == 0xffffffff)
3045 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
3046 else
3047 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
3048 WREG32(GRBM_GFX_INDEX, data);
3049}
3050
3051/**
3052 * cik_create_bitmask - create a bitmask
3053 *
3054 * @bit_width: length of the mask
3055 *
3056 * create a variable length bit mask (CIK).
3057 * Returns the bitmask.
3058 */
3059static u32 cik_create_bitmask(u32 bit_width)
3060{
3061 u32 i, mask = 0;
3062
3063 for (i = 0; i < bit_width; i++) {
3064 mask <<= 1;
3065 mask |= 1;
3066 }
3067 return mask;
3068}
3069
3070/**
3071 * cik_get_rb_disabled - computes the mask of disabled RBs
3072 *
3073 * @rdev: radeon_device pointer
3074 * @max_rb_num: max RBs (render backends) for the asic
3075 * @se_num: number of SEs (shader engines) for the asic
3076 * @sh_per_se: number of SH blocks per SE for the asic
3077 *
3078 * Calculates the bitmask of disabled RBs (CIK).
3079 * Returns the disabled RB bitmask.
3080 */
3081static u32 cik_get_rb_disabled(struct radeon_device *rdev,
3082 u32 max_rb_num_per_se,
3083 u32 sh_per_se)
3084{
3085 u32 data, mask;
3086
3087 data = RREG32(CC_RB_BACKEND_DISABLE);
3088 if (data & 1)
3089 data &= BACKEND_DISABLE_MASK;
3090 else
3091 data = 0;
3092 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
3093
3094 data >>= BACKEND_DISABLE_SHIFT;
3095
3096 mask = cik_create_bitmask(max_rb_num_per_se / sh_per_se);
3097
3098 return data & mask;
3099}
3100
3101/**
3102 * cik_setup_rb - setup the RBs on the asic
3103 *
3104 * @rdev: radeon_device pointer
3105 * @se_num: number of SEs (shader engines) for the asic
3106 * @sh_per_se: number of SH blocks per SE for the asic
3107 * @max_rb_num: max RBs (render backends) for the asic
3108 *
3109 * Configures per-SE/SH RB registers (CIK).
3110 */
3111static void cik_setup_rb(struct radeon_device *rdev,
3112 u32 se_num, u32 sh_per_se,
3113 u32 max_rb_num_per_se)
3114{
3115 int i, j;
3116 u32 data, mask;
3117 u32 disabled_rbs = 0;
3118 u32 enabled_rbs = 0;
3119
3120 for (i = 0; i < se_num; i++) {
3121 for (j = 0; j < sh_per_se; j++) {
3122 cik_select_se_sh(rdev, i, j);
3123 data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
3124 if (rdev->family == CHIP_HAWAII)
3125 disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
3126 else
3127 disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
3128 }
3129 }
3130 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3131
3132 mask = 1;
3133 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
3134 if (!(disabled_rbs & mask))
3135 enabled_rbs |= mask;
3136 mask <<= 1;
3137 }
3138
3139 rdev->config.cik.backend_enable_mask = enabled_rbs;
3140
3141 for (i = 0; i < se_num; i++) {
3142 cik_select_se_sh(rdev, i, 0xffffffff);
3143 data = 0;
3144 for (j = 0; j < sh_per_se; j++) {
3145 switch (enabled_rbs & 3) {
3146 case 0:
3147 if (j == 0)
3148 data |= PKR_MAP(RASTER_CONFIG_RB_MAP_3);
3149 else
3150 data |= PKR_MAP(RASTER_CONFIG_RB_MAP_0);
3151 break;
3152 case 1:
3153 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
3154 break;
3155 case 2:
3156 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
3157 break;
3158 case 3:
3159 default:
3160 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
3161 break;
3162 }
3163 enabled_rbs >>= 2;
3164 }
3165 WREG32(PA_SC_RASTER_CONFIG, data);
3166 }
3167 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3168}
3169
3170/**
3171 * cik_gpu_init - setup the 3D engine
3172 *
3173 * @rdev: radeon_device pointer
3174 *
3175 * Configures the 3D engine and tiling configuration
3176 * registers so that the 3D engine is usable.
3177 */
3178static void cik_gpu_init(struct radeon_device *rdev)
3179{
3180 u32 gb_addr_config = RREG32(GB_ADDR_CONFIG);
3181 u32 mc_shared_chmap, mc_arb_ramcfg;
3182 u32 hdp_host_path_cntl;
3183 u32 tmp;
3184 int i, j;
3185
3186 switch (rdev->family) {
3187 case CHIP_BONAIRE:
3188 rdev->config.cik.max_shader_engines = 2;
3189 rdev->config.cik.max_tile_pipes = 4;
3190 rdev->config.cik.max_cu_per_sh = 7;
3191 rdev->config.cik.max_sh_per_se = 1;
3192 rdev->config.cik.max_backends_per_se = 2;
3193 rdev->config.cik.max_texture_channel_caches = 4;
3194 rdev->config.cik.max_gprs = 256;
3195 rdev->config.cik.max_gs_threads = 32;
3196 rdev->config.cik.max_hw_contexts = 8;
3197
3198 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3199 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3200 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3201 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3202 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3203 break;
3204 case CHIP_HAWAII:
3205 rdev->config.cik.max_shader_engines = 4;
3206 rdev->config.cik.max_tile_pipes = 16;
3207 rdev->config.cik.max_cu_per_sh = 11;
3208 rdev->config.cik.max_sh_per_se = 1;
3209 rdev->config.cik.max_backends_per_se = 4;
3210 rdev->config.cik.max_texture_channel_caches = 16;
3211 rdev->config.cik.max_gprs = 256;
3212 rdev->config.cik.max_gs_threads = 32;
3213 rdev->config.cik.max_hw_contexts = 8;
3214
3215 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3216 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3217 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3218 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3219 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
3220 break;
3221 case CHIP_KAVERI:
3222 rdev->config.cik.max_shader_engines = 1;
3223 rdev->config.cik.max_tile_pipes = 4;
3224 rdev->config.cik.max_cu_per_sh = 8;
3225 rdev->config.cik.max_backends_per_se = 2;
3226 rdev->config.cik.max_sh_per_se = 1;
3227 rdev->config.cik.max_texture_channel_caches = 4;
3228 rdev->config.cik.max_gprs = 256;
3229 rdev->config.cik.max_gs_threads = 16;
3230 rdev->config.cik.max_hw_contexts = 8;
3231
3232 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3233 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3234 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3235 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3236 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3237 break;
3238 case CHIP_KABINI:
3239 case CHIP_MULLINS:
3240 default:
3241 rdev->config.cik.max_shader_engines = 1;
3242 rdev->config.cik.max_tile_pipes = 2;
3243 rdev->config.cik.max_cu_per_sh = 2;
3244 rdev->config.cik.max_sh_per_se = 1;
3245 rdev->config.cik.max_backends_per_se = 1;
3246 rdev->config.cik.max_texture_channel_caches = 2;
3247 rdev->config.cik.max_gprs = 256;
3248 rdev->config.cik.max_gs_threads = 16;
3249 rdev->config.cik.max_hw_contexts = 8;
3250
3251 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3252 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3253 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3254 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3255 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3256 break;
3257 }
3258
3259 /* Initialize HDP */
3260 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
3261 WREG32((0x2c14 + j), 0x00000000);
3262 WREG32((0x2c18 + j), 0x00000000);
3263 WREG32((0x2c1c + j), 0x00000000);
3264 WREG32((0x2c20 + j), 0x00000000);
3265 WREG32((0x2c24 + j), 0x00000000);
3266 }
3267
3268 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3269 WREG32(SRBM_INT_CNTL, 0x1);
3270 WREG32(SRBM_INT_ACK, 0x1);
3271
3272 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
3273
3274 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
3275 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
3276
3277 rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes;
3278 rdev->config.cik.mem_max_burst_length_bytes = 256;
3279 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3280 rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
3281 if (rdev->config.cik.mem_row_size_in_kb > 4)
3282 rdev->config.cik.mem_row_size_in_kb = 4;
3283 /* XXX use MC settings? */
3284 rdev->config.cik.shader_engine_tile_size = 32;
3285 rdev->config.cik.num_gpus = 1;
3286 rdev->config.cik.multi_gpu_tile_size = 64;
3287
3288 /* fix up row size */
3289 gb_addr_config &= ~ROW_SIZE_MASK;
3290 switch (rdev->config.cik.mem_row_size_in_kb) {
3291 case 1:
3292 default:
3293 gb_addr_config |= ROW_SIZE(0);
3294 break;
3295 case 2:
3296 gb_addr_config |= ROW_SIZE(1);
3297 break;
3298 case 4:
3299 gb_addr_config |= ROW_SIZE(2);
3300 break;
3301 }
3302
3303 /* setup tiling info dword. gb_addr_config is not adequate since it does
3304 * not have bank info, so create a custom tiling dword.
3305 * bits 3:0 num_pipes
3306 * bits 7:4 num_banks
3307 * bits 11:8 group_size
3308 * bits 15:12 row_size
3309 */
3310 rdev->config.cik.tile_config = 0;
3311 switch (rdev->config.cik.num_tile_pipes) {
3312 case 1:
3313 rdev->config.cik.tile_config |= (0 << 0);
3314 break;
3315 case 2:
3316 rdev->config.cik.tile_config |= (1 << 0);
3317 break;
3318 case 4:
3319 rdev->config.cik.tile_config |= (2 << 0);
3320 break;
3321 case 8:
3322 default:
3323 /* XXX what about 12? */
3324 rdev->config.cik.tile_config |= (3 << 0);
3325 break;
3326 }
3327 rdev->config.cik.tile_config |=
3328 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
3329 rdev->config.cik.tile_config |=
3330 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
3331 rdev->config.cik.tile_config |=
3332 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
3333
3334 WREG32(GB_ADDR_CONFIG, gb_addr_config);
3335 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
3336 WREG32(DMIF_ADDR_CALC, gb_addr_config);
3337 WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);
3338 WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);
3339 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
3340 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
3341 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
3342
3343 cik_tiling_mode_table_init(rdev);
3344
3345 cik_setup_rb(rdev, rdev->config.cik.max_shader_engines,
3346 rdev->config.cik.max_sh_per_se,
3347 rdev->config.cik.max_backends_per_se);
3348
3349 rdev->config.cik.active_cus = 0;
3350 for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
3351 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
3352 rdev->config.cik.active_cus +=
3353 hweight32(cik_get_cu_active_bitmap(rdev, i, j));
3354 }
3355 }
3356
3357 /* set HW defaults for 3D engine */
3358 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
3359
3360 WREG32(SX_DEBUG_1, 0x20);
3361
3362 WREG32(TA_CNTL_AUX, 0x00010000);
3363
3364 tmp = RREG32(SPI_CONFIG_CNTL);
3365 tmp |= 0x03000000;
3366 WREG32(SPI_CONFIG_CNTL, tmp);
3367
3368 WREG32(SQ_CONFIG, 1);
3369
3370 WREG32(DB_DEBUG, 0);
3371
3372 tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;
3373 tmp |= 0x00000400;
3374 WREG32(DB_DEBUG2, tmp);
3375
3376 tmp = RREG32(DB_DEBUG3) & ~0x0002021c;
3377 tmp |= 0x00020200;
3378 WREG32(DB_DEBUG3, tmp);
3379
3380 tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;
3381 tmp |= 0x00018208;
3382 WREG32(CB_HW_CONTROL, tmp);
3383
3384 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
3385
3386 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |
3387 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) |
3388 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) |
3389 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size)));
3390
3391 WREG32(VGT_NUM_INSTANCES, 1);
3392
3393 WREG32(CP_PERFMON_CNTL, 0);
3394
3395 WREG32(SQ_CONFIG, 0);
3396
3397 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
3398 FORCE_EOV_MAX_REZ_CNT(255)));
3399
3400 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
3401 AUTO_INVLD_EN(ES_AND_GS_AUTO));
3402
3403 WREG32(VGT_GS_VERTEX_REUSE, 16);
3404 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
3405
3406 tmp = RREG32(HDP_MISC_CNTL);
3407 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3408 WREG32(HDP_MISC_CNTL, tmp);
3409
3410 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
3411 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
3412
3413 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
3414 WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER);
3415
3416 udelay(50);
3417}
3418
3419/*
3420 * GPU scratch registers helpers function.
3421 */
3422/**
3423 * cik_scratch_init - setup driver info for CP scratch regs
3424 *
3425 * @rdev: radeon_device pointer
3426 *
3427 * Set up the number and offset of the CP scratch registers.
3428 * NOTE: use of CP scratch registers is a legacy inferface and
3429 * is not used by default on newer asics (r6xx+). On newer asics,
3430 * memory buffers are used for fences rather than scratch regs.
3431 */
3432static void cik_scratch_init(struct radeon_device *rdev)
3433{
3434 int i;
3435
3436 rdev->scratch.num_reg = 7;
3437 rdev->scratch.reg_base = SCRATCH_REG0;
3438 for (i = 0; i < rdev->scratch.num_reg; i++) {
3439 rdev->scratch.free[i] = true;
3440 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3441 }
3442}
3443
3444/**
3445 * cik_ring_test - basic gfx ring test
3446 *
3447 * @rdev: radeon_device pointer
3448 * @ring: radeon_ring structure holding ring information
3449 *
3450 * Allocate a scratch register and write to it using the gfx ring (CIK).
3451 * Provides a basic gfx ring test to verify that the ring is working.
3452 * Used by cik_cp_gfx_resume();
3453 * Returns 0 on success, error on failure.
3454 */
3455int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3456{
3457 uint32_t scratch;
3458 uint32_t tmp = 0;
3459 unsigned i;
3460 int r;
3461
3462 r = radeon_scratch_get(rdev, &scratch);
3463 if (r) {
3464 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3465 return r;
3466 }
3467 WREG32(scratch, 0xCAFEDEAD);
3468 r = radeon_ring_lock(rdev, ring, 3);
3469 if (r) {
3470 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
3471 radeon_scratch_free(rdev, scratch);
3472 return r;
3473 }
3474 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3475 radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));
3476 radeon_ring_write(ring, 0xDEADBEEF);
3477 radeon_ring_unlock_commit(rdev, ring, false);
3478
3479 for (i = 0; i < rdev->usec_timeout; i++) {
3480 tmp = RREG32(scratch);
3481 if (tmp == 0xDEADBEEF)
3482 break;
3483 DRM_UDELAY(1);
3484 }
3485 if (i < rdev->usec_timeout) {
3486 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
3487 } else {
3488 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
3489 ring->idx, scratch, tmp);
3490 r = -EINVAL;
3491 }
3492 radeon_scratch_free(rdev, scratch);
3493 return r;
3494}
3495
3496/**
3497 * cik_hdp_flush_cp_ring_emit - emit an hdp flush on the cp
3498 *
3499 * @rdev: radeon_device pointer
3500 * @ridx: radeon ring index
3501 *
3502 * Emits an hdp flush on the cp.
3503 */
3504static void cik_hdp_flush_cp_ring_emit(struct radeon_device *rdev,
3505 int ridx)
3506{
3507 struct radeon_ring *ring = &rdev->ring[ridx];
3508 u32 ref_and_mask;
3509
3510 switch (ring->idx) {
3511 case CAYMAN_RING_TYPE_CP1_INDEX:
3512 case CAYMAN_RING_TYPE_CP2_INDEX:
3513 default:
3514 switch (ring->me) {
3515 case 0:
3516 ref_and_mask = CP2 << ring->pipe;
3517 break;
3518 case 1:
3519 ref_and_mask = CP6 << ring->pipe;
3520 break;
3521 default:
3522 return;
3523 }
3524 break;
3525 case RADEON_RING_TYPE_GFX_INDEX:
3526 ref_and_mask = CP0;
3527 break;
3528 }
3529
3530 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3531 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3532 WAIT_REG_MEM_FUNCTION(3) | /* == */
3533 WAIT_REG_MEM_ENGINE(1))); /* pfp */
3534 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2);
3535 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2);
3536 radeon_ring_write(ring, ref_and_mask);
3537 radeon_ring_write(ring, ref_and_mask);
3538 radeon_ring_write(ring, 0x20); /* poll interval */
3539}
3540
3541/**
3542 * cik_fence_gfx_ring_emit - emit a fence on the gfx ring
3543 *
3544 * @rdev: radeon_device pointer
3545 * @fence: radeon fence object
3546 *
3547 * Emits a fence sequnce number on the gfx ring and flushes
3548 * GPU caches.
3549 */
3550void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
3551 struct radeon_fence *fence)
3552{
3553 struct radeon_ring *ring = &rdev->ring[fence->ring];
3554 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3555
3556 /* Workaround for cache flush problems. First send a dummy EOP
3557 * event down the pipe with seq one below.
3558 */
3559 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3560 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
3561 EOP_TC_ACTION_EN |
3562 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3563 EVENT_INDEX(5)));
3564 radeon_ring_write(ring, addr & 0xfffffffc);
3565 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
3566 DATA_SEL(1) | INT_SEL(0));
3567 radeon_ring_write(ring, fence->seq - 1);
3568 radeon_ring_write(ring, 0);
3569
3570 /* Then send the real EOP event down the pipe. */
3571 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3572 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
3573 EOP_TC_ACTION_EN |
3574 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3575 EVENT_INDEX(5)));
3576 radeon_ring_write(ring, addr & 0xfffffffc);
3577 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2));
3578 radeon_ring_write(ring, fence->seq);
3579 radeon_ring_write(ring, 0);
3580}
3581
3582/**
3583 * cik_fence_compute_ring_emit - emit a fence on the compute ring
3584 *
3585 * @rdev: radeon_device pointer
3586 * @fence: radeon fence object
3587 *
3588 * Emits a fence sequnce number on the compute ring and flushes
3589 * GPU caches.
3590 */
3591void cik_fence_compute_ring_emit(struct radeon_device *rdev,
3592 struct radeon_fence *fence)
3593{
3594 struct radeon_ring *ring = &rdev->ring[fence->ring];
3595 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3596
3597 /* RELEASE_MEM - flush caches, send int */
3598 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
3599 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
3600 EOP_TC_ACTION_EN |
3601 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3602 EVENT_INDEX(5)));
3603 radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2));
3604 radeon_ring_write(ring, addr & 0xfffffffc);
3605 radeon_ring_write(ring, upper_32_bits(addr));
3606 radeon_ring_write(ring, fence->seq);
3607 radeon_ring_write(ring, 0);
3608}
3609
3610/**
3611 * cik_semaphore_ring_emit - emit a semaphore on the CP ring
3612 *
3613 * @rdev: radeon_device pointer
3614 * @ring: radeon ring buffer object
3615 * @semaphore: radeon semaphore object
3616 * @emit_wait: Is this a sempahore wait?
3617 *
3618 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
3619 * from running ahead of semaphore waits.
3620 */
3621bool cik_semaphore_ring_emit(struct radeon_device *rdev,
3622 struct radeon_ring *ring,
3623 struct radeon_semaphore *semaphore,
3624 bool emit_wait)
3625{
3626 uint64_t addr = semaphore->gpu_addr;
3627 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3628
3629 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
3630 radeon_ring_write(ring, lower_32_bits(addr));
3631 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
3632
3633 if (emit_wait && ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
3634 /* Prevent the PFP from running ahead of the semaphore wait */
3635 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3636 radeon_ring_write(ring, 0x0);
3637 }
3638
3639 return true;
3640}
3641
3642/**
3643 * cik_copy_cpdma - copy pages using the CP DMA engine
3644 *
3645 * @rdev: radeon_device pointer
3646 * @src_offset: src GPU address
3647 * @dst_offset: dst GPU address
3648 * @num_gpu_pages: number of GPU pages to xfer
3649 * @resv: reservation object to sync to
3650 *
3651 * Copy GPU paging using the CP DMA engine (CIK+).
3652 * Used by the radeon ttm implementation to move pages if
3653 * registered as the asic copy callback.
3654 */
3655struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev,
3656 uint64_t src_offset, uint64_t dst_offset,
3657 unsigned num_gpu_pages,
3658 struct reservation_object *resv)
3659{
3660 struct radeon_fence *fence;
3661 struct radeon_sync sync;
3662 int ring_index = rdev->asic->copy.blit_ring_index;
3663 struct radeon_ring *ring = &rdev->ring[ring_index];
3664 u32 size_in_bytes, cur_size_in_bytes, control;
3665 int i, num_loops;
3666 int r = 0;
3667
3668 radeon_sync_create(&sync);
3669
3670 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
3671 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
3672 r = radeon_ring_lock(rdev, ring, num_loops * 7 + 18);
3673 if (r) {
3674 DRM_ERROR("radeon: moving bo (%d).\n", r);
3675 radeon_sync_free(rdev, &sync, NULL);
3676 return ERR_PTR(r);
3677 }
3678
3679 radeon_sync_resv(rdev, &sync, resv, false);
3680 radeon_sync_rings(rdev, &sync, ring->idx);
3681
3682 for (i = 0; i < num_loops; i++) {
3683 cur_size_in_bytes = size_in_bytes;
3684 if (cur_size_in_bytes > 0x1fffff)
3685 cur_size_in_bytes = 0x1fffff;
3686 size_in_bytes -= cur_size_in_bytes;
3687 control = 0;
3688 if (size_in_bytes == 0)
3689 control |= PACKET3_DMA_DATA_CP_SYNC;
3690 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
3691 radeon_ring_write(ring, control);
3692 radeon_ring_write(ring, lower_32_bits(src_offset));
3693 radeon_ring_write(ring, upper_32_bits(src_offset));
3694 radeon_ring_write(ring, lower_32_bits(dst_offset));
3695 radeon_ring_write(ring, upper_32_bits(dst_offset));
3696 radeon_ring_write(ring, cur_size_in_bytes);
3697 src_offset += cur_size_in_bytes;
3698 dst_offset += cur_size_in_bytes;
3699 }
3700
3701 r = radeon_fence_emit(rdev, &fence, ring->idx);
3702 if (r) {
3703 radeon_ring_unlock_undo(rdev, ring);
3704 radeon_sync_free(rdev, &sync, NULL);
3705 return ERR_PTR(r);
3706 }
3707
3708 radeon_ring_unlock_commit(rdev, ring, false);
3709 radeon_sync_free(rdev, &sync, fence);
3710
3711 return fence;
3712}
3713
3714/*
3715 * IB stuff
3716 */
3717/**
3718 * cik_ring_ib_execute - emit an IB (Indirect Buffer) on the gfx ring
3719 *
3720 * @rdev: radeon_device pointer
3721 * @ib: radeon indirect buffer object
3722 *
3723 * Emits a DE (drawing engine) or CE (constant engine) IB
3724 * on the gfx ring. IBs are usually generated by userspace
3725 * acceleration drivers and submitted to the kernel for
3726 * scheduling on the ring. This function schedules the IB
3727 * on the gfx ring for execution by the GPU.
3728 */
3729void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3730{
3731 struct radeon_ring *ring = &rdev->ring[ib->ring];
3732 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
3733 u32 header, control = INDIRECT_BUFFER_VALID;
3734
3735 if (ib->is_const_ib) {
3736 /* set switch buffer packet before const IB */
3737 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3738 radeon_ring_write(ring, 0);
3739
3740 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3741 } else {
3742 u32 next_rptr;
3743 if (ring->rptr_save_reg) {
3744 next_rptr = ring->wptr + 3 + 4;
3745 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3746 radeon_ring_write(ring, ((ring->rptr_save_reg -
3747 PACKET3_SET_UCONFIG_REG_START) >> 2));
3748 radeon_ring_write(ring, next_rptr);
3749 } else if (rdev->wb.enabled) {
3750 next_rptr = ring->wptr + 5 + 4;
3751 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3752 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1));
3753 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3754 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
3755 radeon_ring_write(ring, next_rptr);
3756 }
3757
3758 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3759 }
3760
3761 control |= ib->length_dw | (vm_id << 24);
3762
3763 radeon_ring_write(ring, header);
3764 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFFC));
3765 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3766 radeon_ring_write(ring, control);
3767}
3768
3769/**
3770 * cik_ib_test - basic gfx ring IB test
3771 *
3772 * @rdev: radeon_device pointer
3773 * @ring: radeon_ring structure holding ring information
3774 *
3775 * Allocate an IB and execute it on the gfx ring (CIK).
3776 * Provides a basic gfx ring test to verify that IBs are working.
3777 * Returns 0 on success, error on failure.
3778 */
3779int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3780{
3781 struct radeon_ib ib;
3782 uint32_t scratch;
3783 uint32_t tmp = 0;
3784 unsigned i;
3785 int r;
3786
3787 r = radeon_scratch_get(rdev, &scratch);
3788 if (r) {
3789 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3790 return r;
3791 }
3792 WREG32(scratch, 0xCAFEDEAD);
3793 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3794 if (r) {
3795 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3796 radeon_scratch_free(rdev, scratch);
3797 return r;
3798 }
3799 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
3800 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2);
3801 ib.ptr[2] = 0xDEADBEEF;
3802 ib.length_dw = 3;
3803 r = radeon_ib_schedule(rdev, &ib, NULL, false);
3804 if (r) {
3805 radeon_scratch_free(rdev, scratch);
3806 radeon_ib_free(rdev, &ib);
3807 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3808 return r;
3809 }
3810 r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
3811 RADEON_USEC_IB_TEST_TIMEOUT));
3812 if (r < 0) {
3813 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3814 radeon_scratch_free(rdev, scratch);
3815 radeon_ib_free(rdev, &ib);
3816 return r;
3817 } else if (r == 0) {
3818 DRM_ERROR("radeon: fence wait timed out.\n");
3819 radeon_scratch_free(rdev, scratch);
3820 radeon_ib_free(rdev, &ib);
3821 return -ETIMEDOUT;
3822 }
3823 r = 0;
3824 for (i = 0; i < rdev->usec_timeout; i++) {
3825 tmp = RREG32(scratch);
3826 if (tmp == 0xDEADBEEF)
3827 break;
3828 DRM_UDELAY(1);
3829 }
3830 if (i < rdev->usec_timeout) {
3831 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3832 } else {
3833 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3834 scratch, tmp);
3835 r = -EINVAL;
3836 }
3837 radeon_scratch_free(rdev, scratch);
3838 radeon_ib_free(rdev, &ib);
3839 return r;
3840}
3841
3842/*
3843 * CP.
3844 * On CIK, gfx and compute now have independant command processors.
3845 *
3846 * GFX
3847 * Gfx consists of a single ring and can process both gfx jobs and
3848 * compute jobs. The gfx CP consists of three microengines (ME):
3849 * PFP - Pre-Fetch Parser
3850 * ME - Micro Engine
3851 * CE - Constant Engine
3852 * The PFP and ME make up what is considered the Drawing Engine (DE).
3853 * The CE is an asynchronous engine used for updating buffer desciptors
3854 * used by the DE so that they can be loaded into cache in parallel
3855 * while the DE is processing state update packets.
3856 *
3857 * Compute
3858 * The compute CP consists of two microengines (ME):
3859 * MEC1 - Compute MicroEngine 1
3860 * MEC2 - Compute MicroEngine 2
3861 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
3862 * The queues are exposed to userspace and are programmed directly
3863 * by the compute runtime.
3864 */
3865/**
3866 * cik_cp_gfx_enable - enable/disable the gfx CP MEs
3867 *
3868 * @rdev: radeon_device pointer
3869 * @enable: enable or disable the MEs
3870 *
3871 * Halts or unhalts the gfx MEs.
3872 */
3873static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
3874{
3875 if (enable)
3876 WREG32(CP_ME_CNTL, 0);
3877 else {
3878 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
3879 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3880 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
3881 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3882 }
3883 udelay(50);
3884}
3885
3886/**
3887 * cik_cp_gfx_load_microcode - load the gfx CP ME ucode
3888 *
3889 * @rdev: radeon_device pointer
3890 *
3891 * Loads the gfx PFP, ME, and CE ucode.
3892 * Returns 0 for success, -EINVAL if the ucode is not available.
3893 */
3894static int cik_cp_gfx_load_microcode(struct radeon_device *rdev)
3895{
3896 int i;
3897
3898 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw)
3899 return -EINVAL;
3900
3901 cik_cp_gfx_enable(rdev, false);
3902
3903 if (rdev->new_fw) {
3904 const struct gfx_firmware_header_v1_0 *pfp_hdr =
3905 (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data;
3906 const struct gfx_firmware_header_v1_0 *ce_hdr =
3907 (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data;
3908 const struct gfx_firmware_header_v1_0 *me_hdr =
3909 (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data;
3910 const __le32 *fw_data;
3911 u32 fw_size;
3912
3913 radeon_ucode_print_gfx_hdr(&pfp_hdr->header);
3914 radeon_ucode_print_gfx_hdr(&ce_hdr->header);
3915 radeon_ucode_print_gfx_hdr(&me_hdr->header);
3916
3917 /* PFP */
3918 fw_data = (const __le32 *)
3919 (rdev->pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
3920 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
3921 WREG32(CP_PFP_UCODE_ADDR, 0);
3922 for (i = 0; i < fw_size; i++)
3923 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
3924 WREG32(CP_PFP_UCODE_ADDR, le32_to_cpu(pfp_hdr->header.ucode_version));
3925
3926 /* CE */
3927 fw_data = (const __le32 *)
3928 (rdev->ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
3929 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
3930 WREG32(CP_CE_UCODE_ADDR, 0);
3931 for (i = 0; i < fw_size; i++)
3932 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
3933 WREG32(CP_CE_UCODE_ADDR, le32_to_cpu(ce_hdr->header.ucode_version));
3934
3935 /* ME */
3936 fw_data = (const __be32 *)
3937 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
3938 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
3939 WREG32(CP_ME_RAM_WADDR, 0);
3940 for (i = 0; i < fw_size; i++)
3941 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
3942 WREG32(CP_ME_RAM_WADDR, le32_to_cpu(me_hdr->header.ucode_version));
3943 WREG32(CP_ME_RAM_RADDR, le32_to_cpu(me_hdr->header.ucode_version));
3944 } else {
3945 const __be32 *fw_data;
3946
3947 /* PFP */
3948 fw_data = (const __be32 *)rdev->pfp_fw->data;
3949 WREG32(CP_PFP_UCODE_ADDR, 0);
3950 for (i = 0; i < CIK_PFP_UCODE_SIZE; i++)
3951 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
3952 WREG32(CP_PFP_UCODE_ADDR, 0);
3953
3954 /* CE */
3955 fw_data = (const __be32 *)rdev->ce_fw->data;
3956 WREG32(CP_CE_UCODE_ADDR, 0);
3957 for (i = 0; i < CIK_CE_UCODE_SIZE; i++)
3958 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
3959 WREG32(CP_CE_UCODE_ADDR, 0);
3960
3961 /* ME */
3962 fw_data = (const __be32 *)rdev->me_fw->data;
3963 WREG32(CP_ME_RAM_WADDR, 0);
3964 for (i = 0; i < CIK_ME_UCODE_SIZE; i++)
3965 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
3966 WREG32(CP_ME_RAM_WADDR, 0);
3967 }
3968
3969 return 0;
3970}
3971
3972/**
3973 * cik_cp_gfx_start - start the gfx ring
3974 *
3975 * @rdev: radeon_device pointer
3976 *
3977 * Enables the ring and loads the clear state context and other
3978 * packets required to init the ring.
3979 * Returns 0 for success, error for failure.
3980 */
3981static int cik_cp_gfx_start(struct radeon_device *rdev)
3982{
3983 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3984 int r, i;
3985
3986 /* init the CP */
3987 WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1);
3988 WREG32(CP_ENDIAN_SWAP, 0);
3989 WREG32(CP_DEVICE_ID, 1);
3990
3991 cik_cp_gfx_enable(rdev, true);
3992
3993 r = radeon_ring_lock(rdev, ring, cik_default_size + 17);
3994 if (r) {
3995 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3996 return r;
3997 }
3998
3999 /* init the CE partitions. CE only used for gfx on CIK */
4000 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
4001 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
4002 radeon_ring_write(ring, 0x8000);
4003 radeon_ring_write(ring, 0x8000);
4004
4005 /* setup clear context state */
4006 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4007 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4008
4009 radeon_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4010 radeon_ring_write(ring, 0x80000000);
4011 radeon_ring_write(ring, 0x80000000);
4012
4013 for (i = 0; i < cik_default_size; i++)
4014 radeon_ring_write(ring, cik_default_state[i]);
4015
4016 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4017 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
4018
4019 /* set clear context state */
4020 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
4021 radeon_ring_write(ring, 0);
4022
4023 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4024 radeon_ring_write(ring, 0x00000316);
4025 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
4026 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
4027
4028 radeon_ring_unlock_commit(rdev, ring, false);
4029
4030 return 0;
4031}
4032
4033/**
4034 * cik_cp_gfx_fini - stop the gfx ring
4035 *
4036 * @rdev: radeon_device pointer
4037 *
4038 * Stop the gfx ring and tear down the driver ring
4039 * info.
4040 */
4041static void cik_cp_gfx_fini(struct radeon_device *rdev)
4042{
4043 cik_cp_gfx_enable(rdev, false);
4044 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
4045}
4046
4047/**
4048 * cik_cp_gfx_resume - setup the gfx ring buffer registers
4049 *
4050 * @rdev: radeon_device pointer
4051 *
4052 * Program the location and size of the gfx ring buffer
4053 * and test it to make sure it's working.
4054 * Returns 0 for success, error for failure.
4055 */
4056static int cik_cp_gfx_resume(struct radeon_device *rdev)
4057{
4058 struct radeon_ring *ring;
4059 u32 tmp;
4060 u32 rb_bufsz;
4061 u64 rb_addr;
4062 int r;
4063
4064 WREG32(CP_SEM_WAIT_TIMER, 0x0);
4065 if (rdev->family != CHIP_HAWAII)
4066 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
4067
4068 /* Set the write pointer delay */
4069 WREG32(CP_RB_WPTR_DELAY, 0);
4070
4071 /* set the RB to use vmid 0 */
4072 WREG32(CP_RB_VMID, 0);
4073
4074 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
4075
4076 /* ring 0 - compute and gfx */
4077 /* Set ring buffer size */
4078 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4079 rb_bufsz = order_base_2(ring->ring_size / 8);
4080 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
4081#ifdef __BIG_ENDIAN
4082 tmp |= BUF_SWAP_32BIT;
4083#endif
4084 WREG32(CP_RB0_CNTL, tmp);
4085
4086 /* Initialize the ring buffer's read and write pointers */
4087 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
4088 ring->wptr = 0;
4089 WREG32(CP_RB0_WPTR, ring->wptr);
4090
4091 /* set the wb address wether it's enabled or not */
4092 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
4093 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
4094
4095 /* scratch register shadowing is no longer supported */
4096 WREG32(SCRATCH_UMSK, 0);
4097
4098 if (!rdev->wb.enabled)
4099 tmp |= RB_NO_UPDATE;
4100
4101 mdelay(1);
4102 WREG32(CP_RB0_CNTL, tmp);
4103
4104 rb_addr = ring->gpu_addr >> 8;
4105 WREG32(CP_RB0_BASE, rb_addr);
4106 WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr));
4107
4108 /* start the ring */
4109 cik_cp_gfx_start(rdev);
4110 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
4111 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
4112 if (r) {
4113 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
4114 return r;
4115 }
4116
4117 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
4118 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
4119
4120 return 0;
4121}
4122
4123u32 cik_gfx_get_rptr(struct radeon_device *rdev,
4124 struct radeon_ring *ring)
4125{
4126 u32 rptr;
4127
4128 if (rdev->wb.enabled)
4129 rptr = rdev->wb.wb[ring->rptr_offs/4];
4130 else
4131 rptr = RREG32(CP_RB0_RPTR);
4132
4133 return rptr;
4134}
4135
4136u32 cik_gfx_get_wptr(struct radeon_device *rdev,
4137 struct radeon_ring *ring)
4138{
4139 return RREG32(CP_RB0_WPTR);
4140}
4141
4142void cik_gfx_set_wptr(struct radeon_device *rdev,
4143 struct radeon_ring *ring)
4144{
4145 WREG32(CP_RB0_WPTR, ring->wptr);
4146 (void)RREG32(CP_RB0_WPTR);
4147}
4148
4149u32 cik_compute_get_rptr(struct radeon_device *rdev,
4150 struct radeon_ring *ring)
4151{
4152 u32 rptr;
4153
4154 if (rdev->wb.enabled) {
4155 rptr = rdev->wb.wb[ring->rptr_offs/4];
4156 } else {
4157 mutex_lock(&rdev->srbm_mutex);
4158 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4159 rptr = RREG32(CP_HQD_PQ_RPTR);
4160 cik_srbm_select(rdev, 0, 0, 0, 0);
4161 mutex_unlock(&rdev->srbm_mutex);
4162 }
4163
4164 return rptr;
4165}
4166
4167u32 cik_compute_get_wptr(struct radeon_device *rdev,
4168 struct radeon_ring *ring)
4169{
4170 u32 wptr;
4171
4172 if (rdev->wb.enabled) {
4173 /* XXX check if swapping is necessary on BE */
4174 wptr = rdev->wb.wb[ring->wptr_offs/4];
4175 } else {
4176 mutex_lock(&rdev->srbm_mutex);
4177 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4178 wptr = RREG32(CP_HQD_PQ_WPTR);
4179 cik_srbm_select(rdev, 0, 0, 0, 0);
4180 mutex_unlock(&rdev->srbm_mutex);
4181 }
4182
4183 return wptr;
4184}
4185
4186void cik_compute_set_wptr(struct radeon_device *rdev,
4187 struct radeon_ring *ring)
4188{
4189 /* XXX check if swapping is necessary on BE */
4190 rdev->wb.wb[ring->wptr_offs/4] = ring->wptr;
4191 WDOORBELL32(ring->doorbell_index, ring->wptr);
4192}
4193
4194static void cik_compute_stop(struct radeon_device *rdev,
4195 struct radeon_ring *ring)
4196{
4197 u32 j, tmp;
4198
4199 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4200 /* Disable wptr polling. */
4201 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
4202 tmp &= ~WPTR_POLL_EN;
4203 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
4204 /* Disable HQD. */
4205 if (RREG32(CP_HQD_ACTIVE) & 1) {
4206 WREG32(CP_HQD_DEQUEUE_REQUEST, 1);
4207 for (j = 0; j < rdev->usec_timeout; j++) {
4208 if (!(RREG32(CP_HQD_ACTIVE) & 1))
4209 break;
4210 udelay(1);
4211 }
4212 WREG32(CP_HQD_DEQUEUE_REQUEST, 0);
4213 WREG32(CP_HQD_PQ_RPTR, 0);
4214 WREG32(CP_HQD_PQ_WPTR, 0);
4215 }
4216 cik_srbm_select(rdev, 0, 0, 0, 0);
4217}
4218
4219/**
4220 * cik_cp_compute_enable - enable/disable the compute CP MEs
4221 *
4222 * @rdev: radeon_device pointer
4223 * @enable: enable or disable the MEs
4224 *
4225 * Halts or unhalts the compute MEs.
4226 */
4227static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable)
4228{
4229 if (enable)
4230 WREG32(CP_MEC_CNTL, 0);
4231 else {
4232 /*
4233 * To make hibernation reliable we need to clear compute ring
4234 * configuration before halting the compute ring.
4235 */
4236 mutex_lock(&rdev->srbm_mutex);
4237 cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
4238 cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
4239 mutex_unlock(&rdev->srbm_mutex);
4240
4241 WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT));
4242 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
4243 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
4244 }
4245 udelay(50);
4246}
4247
4248/**
4249 * cik_cp_compute_load_microcode - load the compute CP ME ucode
4250 *
4251 * @rdev: radeon_device pointer
4252 *
4253 * Loads the compute MEC1&2 ucode.
4254 * Returns 0 for success, -EINVAL if the ucode is not available.
4255 */
4256static int cik_cp_compute_load_microcode(struct radeon_device *rdev)
4257{
4258 int i;
4259
4260 if (!rdev->mec_fw)
4261 return -EINVAL;
4262
4263 cik_cp_compute_enable(rdev, false);
4264
4265 if (rdev->new_fw) {
4266 const struct gfx_firmware_header_v1_0 *mec_hdr =
4267 (const struct gfx_firmware_header_v1_0 *)rdev->mec_fw->data;
4268 const __le32 *fw_data;
4269 u32 fw_size;
4270
4271 radeon_ucode_print_gfx_hdr(&mec_hdr->header);
4272
4273 /* MEC1 */
4274 fw_data = (const __le32 *)
4275 (rdev->mec_fw->data + le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4276 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
4277 WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4278 for (i = 0; i < fw_size; i++)
4279 WREG32(CP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
4280 WREG32(CP_MEC_ME1_UCODE_ADDR, le32_to_cpu(mec_hdr->header.ucode_version));
4281
4282 /* MEC2 */
4283 if (rdev->family == CHIP_KAVERI) {
4284 const struct gfx_firmware_header_v1_0 *mec2_hdr =
4285 (const struct gfx_firmware_header_v1_0 *)rdev->mec2_fw->data;
4286
4287 fw_data = (const __le32 *)
4288 (rdev->mec2_fw->data +
4289 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
4290 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
4291 WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4292 for (i = 0; i < fw_size; i++)
4293 WREG32(CP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
4294 WREG32(CP_MEC_ME2_UCODE_ADDR, le32_to_cpu(mec2_hdr->header.ucode_version));
4295 }
4296 } else {
4297 const __be32 *fw_data;
4298
4299 /* MEC1 */
4300 fw_data = (const __be32 *)rdev->mec_fw->data;
4301 WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4302 for (i = 0; i < CIK_MEC_UCODE_SIZE; i++)
4303 WREG32(CP_MEC_ME1_UCODE_DATA, be32_to_cpup(fw_data++));
4304 WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4305
4306 if (rdev->family == CHIP_KAVERI) {
4307 /* MEC2 */
4308 fw_data = (const __be32 *)rdev->mec_fw->data;
4309 WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4310 for (i = 0; i < CIK_MEC_UCODE_SIZE; i++)
4311 WREG32(CP_MEC_ME2_UCODE_DATA, be32_to_cpup(fw_data++));
4312 WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4313 }
4314 }
4315
4316 return 0;
4317}
4318
4319/**
4320 * cik_cp_compute_start - start the compute queues
4321 *
4322 * @rdev: radeon_device pointer
4323 *
4324 * Enable the compute queues.
4325 * Returns 0 for success, error for failure.
4326 */
4327static int cik_cp_compute_start(struct radeon_device *rdev)
4328{
4329 cik_cp_compute_enable(rdev, true);
4330
4331 return 0;
4332}
4333
4334/**
4335 * cik_cp_compute_fini - stop the compute queues
4336 *
4337 * @rdev: radeon_device pointer
4338 *
4339 * Stop the compute queues and tear down the driver queue
4340 * info.
4341 */
4342static void cik_cp_compute_fini(struct radeon_device *rdev)
4343{
4344 int i, idx, r;
4345
4346 cik_cp_compute_enable(rdev, false);
4347
4348 for (i = 0; i < 2; i++) {
4349 if (i == 0)
4350 idx = CAYMAN_RING_TYPE_CP1_INDEX;
4351 else
4352