1 | /* |
2 | * Copyright 2012 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
21 | * DEALINGS IN THE SOFTWARE. |
22 | * |
23 | * Authors: |
24 | * Alex Deucher <alexander.deucher@amd.com> |
25 | */ |
26 | |
27 | #ifndef CIK_BLIT_SHADERS_H |
28 | #define CIK_BLIT_SHADERS_H |
29 | |
30 | static const u32 cik_default_state[] = |
31 | { |
32 | 0xc0066900, |
33 | 0x00000000, |
34 | 0x00000060, /* DB_RENDER_CONTROL */ |
35 | 0x00000000, /* DB_COUNT_CONTROL */ |
36 | 0x00000000, /* DB_DEPTH_VIEW */ |
37 | 0x0000002a, /* DB_RENDER_OVERRIDE */ |
38 | 0x00000000, /* DB_RENDER_OVERRIDE2 */ |
39 | 0x00000000, /* DB_HTILE_DATA_BASE */ |
40 | |
41 | 0xc0046900, |
42 | 0x00000008, |
43 | 0x00000000, /* DB_DEPTH_BOUNDS_MIN */ |
44 | 0x00000000, /* DB_DEPTH_BOUNDS_MAX */ |
45 | 0x00000000, /* DB_STENCIL_CLEAR */ |
46 | 0x00000000, /* DB_DEPTH_CLEAR */ |
47 | |
48 | 0xc0036900, |
49 | 0x0000000f, |
50 | 0x00000000, /* DB_DEPTH_INFO */ |
51 | 0x00000000, /* DB_Z_INFO */ |
52 | 0x00000000, /* DB_STENCIL_INFO */ |
53 | |
54 | 0xc0016900, |
55 | 0x00000080, |
56 | 0x00000000, /* PA_SC_WINDOW_OFFSET */ |
57 | |
58 | 0xc00d6900, |
59 | 0x00000083, |
60 | 0x0000ffff, /* PA_SC_CLIPRECT_RULE */ |
61 | 0x00000000, /* PA_SC_CLIPRECT_0_TL */ |
62 | 0x20002000, /* PA_SC_CLIPRECT_0_BR */ |
63 | 0x00000000, |
64 | 0x20002000, |
65 | 0x00000000, |
66 | 0x20002000, |
67 | 0x00000000, |
68 | 0x20002000, |
69 | 0xaaaaaaaa, /* PA_SC_EDGERULE */ |
70 | 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */ |
71 | 0x0000000f, /* CB_TARGET_MASK */ |
72 | 0x0000000f, /* CB_SHADER_MASK */ |
73 | |
74 | 0xc0226900, |
75 | 0x00000094, |
76 | 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ |
77 | 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ |
78 | 0x80000000, |
79 | 0x20002000, |
80 | 0x80000000, |
81 | 0x20002000, |
82 | 0x80000000, |
83 | 0x20002000, |
84 | 0x80000000, |
85 | 0x20002000, |
86 | 0x80000000, |
87 | 0x20002000, |
88 | 0x80000000, |
89 | 0x20002000, |
90 | 0x80000000, |
91 | 0x20002000, |
92 | 0x80000000, |
93 | 0x20002000, |
94 | 0x80000000, |
95 | 0x20002000, |
96 | 0x80000000, |
97 | 0x20002000, |
98 | 0x80000000, |
99 | 0x20002000, |
100 | 0x80000000, |
101 | 0x20002000, |
102 | 0x80000000, |
103 | 0x20002000, |
104 | 0x80000000, |
105 | 0x20002000, |
106 | 0x80000000, |
107 | 0x20002000, |
108 | 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ |
109 | 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */ |
110 | |
111 | 0xc0046900, |
112 | 0x00000100, |
113 | 0xffffffff, /* VGT_MAX_VTX_INDX */ |
114 | 0x00000000, /* VGT_MIN_VTX_INDX */ |
115 | 0x00000000, /* VGT_INDX_OFFSET */ |
116 | 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ |
117 | |
118 | 0xc0046900, |
119 | 0x00000105, |
120 | 0x00000000, /* CB_BLEND_RED */ |
121 | 0x00000000, /* CB_BLEND_GREEN */ |
122 | 0x00000000, /* CB_BLEND_BLUE */ |
123 | 0x00000000, /* CB_BLEND_ALPHA */ |
124 | |
125 | 0xc0016900, |
126 | 0x000001e0, |
127 | 0x00000000, /* CB_BLEND0_CONTROL */ |
128 | |
129 | 0xc00c6900, |
130 | 0x00000200, |
131 | 0x00000000, /* DB_DEPTH_CONTROL */ |
132 | 0x00000000, /* DB_EQAA */ |
133 | 0x00cc0010, /* CB_COLOR_CONTROL */ |
134 | 0x00000210, /* DB_SHADER_CONTROL */ |
135 | 0x00010000, /* PA_CL_CLIP_CNTL */ |
136 | 0x00000004, /* PA_SU_SC_MODE_CNTL */ |
137 | 0x00000100, /* PA_CL_VTE_CNTL */ |
138 | 0x00000000, /* PA_CL_VS_OUT_CNTL */ |
139 | 0x00000000, /* PA_CL_NANINF_CNTL */ |
140 | 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */ |
141 | 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */ |
142 | 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */ |
143 | |
144 | 0xc0116900, |
145 | 0x00000280, |
146 | 0x00000000, /* PA_SU_POINT_SIZE */ |
147 | 0x00000000, /* PA_SU_POINT_MINMAX */ |
148 | 0x00000008, /* PA_SU_LINE_CNTL */ |
149 | 0x00000000, /* PA_SC_LINE_STIPPLE */ |
150 | 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ |
151 | 0x00000000, /* VGT_HOS_CNTL */ |
152 | 0x00000000, |
153 | 0x00000000, |
154 | 0x00000000, |
155 | 0x00000000, |
156 | 0x00000000, |
157 | 0x00000000, |
158 | 0x00000000, |
159 | 0x00000000, |
160 | 0x00000000, |
161 | 0x00000000, |
162 | 0x00000000, /* VGT_GS_MODE */ |
163 | |
164 | 0xc0026900, |
165 | 0x00000292, |
166 | 0x00000000, /* PA_SC_MODE_CNTL_0 */ |
167 | 0x00000000, /* PA_SC_MODE_CNTL_1 */ |
168 | |
169 | 0xc0016900, |
170 | 0x000002a1, |
171 | 0x00000000, /* VGT_PRIMITIVEID_EN */ |
172 | |
173 | 0xc0016900, |
174 | 0x000002a5, |
175 | 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */ |
176 | |
177 | 0xc0026900, |
178 | 0x000002a8, |
179 | 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ |
180 | 0x00000000, |
181 | |
182 | 0xc0026900, |
183 | 0x000002ad, |
184 | 0x00000000, /* VGT_REUSE_OFF */ |
185 | 0x00000000, |
186 | |
187 | 0xc0016900, |
188 | 0x000002d5, |
189 | 0x00000000, /* VGT_SHADER_STAGES_EN */ |
190 | |
191 | 0xc0016900, |
192 | 0x000002dc, |
193 | 0x0000aa00, /* DB_ALPHA_TO_MASK */ |
194 | |
195 | 0xc0066900, |
196 | 0x000002de, |
197 | 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ |
198 | 0x00000000, |
199 | 0x00000000, |
200 | 0x00000000, |
201 | 0x00000000, |
202 | 0x00000000, |
203 | |
204 | 0xc0026900, |
205 | 0x000002e5, |
206 | 0x00000000, /* VGT_STRMOUT_CONFIG */ |
207 | 0x00000000, |
208 | |
209 | 0xc01b6900, |
210 | 0x000002f5, |
211 | 0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */ |
212 | 0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */ |
213 | 0x00000000, /* PA_SC_LINE_CNTL */ |
214 | 0x00000000, /* PA_SC_AA_CONFIG */ |
215 | 0x00000005, /* PA_SU_VTX_CNTL */ |
216 | 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ |
217 | 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */ |
218 | 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */ |
219 | 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */ |
220 | 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */ |
221 | 0x00000000, |
222 | 0x00000000, |
223 | 0x00000000, |
224 | 0x00000000, |
225 | 0x00000000, |
226 | 0x00000000, |
227 | 0x00000000, |
228 | 0x00000000, |
229 | 0x00000000, |
230 | 0x00000000, |
231 | 0x00000000, |
232 | 0x00000000, |
233 | 0x00000000, |
234 | 0x00000000, |
235 | 0x00000000, |
236 | 0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */ |
237 | 0xffffffff, |
238 | |
239 | 0xc0026900, |
240 | 0x00000316, |
241 | 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
242 | 0x00000010, /* */ |
243 | }; |
244 | |
245 | static const u32 cik_default_size = ARRAY_SIZE(cik_default_state); |
246 | |
247 | #endif |
248 | |