1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Christian König. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Christian König |
25 | * Rafał Miłecki |
26 | */ |
27 | #include <linux/hdmi.h> |
28 | |
29 | #include <drm/radeon_drm.h> |
30 | #include "evergreen_hdmi.h" |
31 | #include "radeon.h" |
32 | #include "radeon_asic.h" |
33 | #include "radeon_audio.h" |
34 | #include "evergreend.h" |
35 | #include "atom.h" |
36 | |
37 | /* enable the audio stream */ |
38 | void dce4_audio_enable(struct radeon_device *rdev, |
39 | struct r600_audio_pin *pin, |
40 | u8 enable_mask) |
41 | { |
42 | u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); |
43 | |
44 | if (!pin) |
45 | return; |
46 | |
47 | if (enable_mask) { |
48 | tmp |= AUDIO_ENABLED; |
49 | if (enable_mask & 1) |
50 | tmp |= PIN0_AUDIO_ENABLED; |
51 | if (enable_mask & 2) |
52 | tmp |= PIN1_AUDIO_ENABLED; |
53 | if (enable_mask & 4) |
54 | tmp |= PIN2_AUDIO_ENABLED; |
55 | if (enable_mask & 8) |
56 | tmp |= PIN3_AUDIO_ENABLED; |
57 | } else { |
58 | tmp &= ~(AUDIO_ENABLED | |
59 | PIN0_AUDIO_ENABLED | |
60 | PIN1_AUDIO_ENABLED | |
61 | PIN2_AUDIO_ENABLED | |
62 | PIN3_AUDIO_ENABLED); |
63 | } |
64 | |
65 | WREG32(AZ_HOT_PLUG_CONTROL, tmp); |
66 | } |
67 | |
68 | void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset, |
69 | const struct radeon_hdmi_acr *acr) |
70 | { |
71 | struct drm_device *dev = encoder->dev; |
72 | struct radeon_device *rdev = dev->dev_private; |
73 | int bpc = 8; |
74 | |
75 | if (encoder->crtc) { |
76 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
77 | bpc = radeon_crtc->bpc; |
78 | } |
79 | |
80 | if (bpc > 8) |
81 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
82 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
83 | else |
84 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
85 | HDMI_ACR_SOURCE | /* select SW CTS value */ |
86 | HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ |
87 | |
88 | WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); |
89 | WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); |
90 | |
91 | WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); |
92 | WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); |
93 | |
94 | WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); |
95 | WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz); |
96 | } |
97 | |
98 | void dce4_afmt_write_latency_fields(struct drm_encoder *encoder, |
99 | struct drm_connector *connector, struct drm_display_mode *mode) |
100 | { |
101 | struct radeon_device *rdev = encoder->dev->dev_private; |
102 | u32 tmp = 0; |
103 | |
104 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
105 | if (connector->latency_present[1]) |
106 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | |
107 | AUDIO_LIPSYNC(connector->audio_latency[1]); |
108 | else |
109 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
110 | } else { |
111 | if (connector->latency_present[0]) |
112 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | |
113 | AUDIO_LIPSYNC(connector->audio_latency[0]); |
114 | else |
115 | tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255); |
116 | } |
117 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); |
118 | } |
119 | |
120 | void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, |
121 | u8 *sadb, int sad_count) |
122 | { |
123 | struct radeon_device *rdev = encoder->dev->dev_private; |
124 | u32 tmp; |
125 | |
126 | /* program the speaker allocation */ |
127 | tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
128 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
129 | /* set HDMI mode */ |
130 | tmp |= HDMI_CONNECTION; |
131 | if (sad_count) |
132 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
133 | else |
134 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
135 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
136 | } |
137 | |
138 | void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, |
139 | u8 *sadb, int sad_count) |
140 | { |
141 | struct radeon_device *rdev = encoder->dev->dev_private; |
142 | u32 tmp; |
143 | |
144 | /* program the speaker allocation */ |
145 | tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER); |
146 | tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK); |
147 | /* set DP mode */ |
148 | tmp |= DP_CONNECTION; |
149 | if (sad_count) |
150 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
151 | else |
152 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
153 | WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); |
154 | } |
155 | |
156 | void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder, |
157 | struct cea_sad *sads, int sad_count) |
158 | { |
159 | int i; |
160 | struct radeon_device *rdev = encoder->dev->dev_private; |
161 | static const u16 eld_reg_to_type[][2] = { |
162 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, |
163 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, |
164 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, |
165 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, |
166 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, |
167 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, |
168 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, |
169 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, |
170 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, |
171 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
172 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
173 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
174 | }; |
175 | |
176 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
177 | u32 value = 0; |
178 | u8 stereo_freqs = 0; |
179 | int max_channels = -1; |
180 | int j; |
181 | |
182 | for (j = 0; j < sad_count; j++) { |
183 | struct cea_sad *sad = &sads[j]; |
184 | |
185 | if (sad->format == eld_reg_to_type[i][1]) { |
186 | if (sad->channels > max_channels) { |
187 | value = MAX_CHANNELS(sad->channels) | |
188 | DESCRIPTOR_BYTE_2(sad->byte2) | |
189 | SUPPORTED_FREQUENCIES(sad->freq); |
190 | max_channels = sad->channels; |
191 | } |
192 | |
193 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
194 | stereo_freqs |= sad->freq; |
195 | else |
196 | break; |
197 | } |
198 | } |
199 | |
200 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); |
201 | |
202 | WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value); |
203 | } |
204 | } |
205 | |
206 | /* |
207 | * build a AVI Info Frame |
208 | */ |
209 | void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset, |
210 | unsigned char *buffer, size_t size) |
211 | { |
212 | uint8_t *frame = buffer + 3; |
213 | |
214 | WREG32(AFMT_AVI_INFO0 + offset, |
215 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
216 | WREG32(AFMT_AVI_INFO1 + offset, |
217 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
218 | WREG32(AFMT_AVI_INFO2 + offset, |
219 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
220 | WREG32(AFMT_AVI_INFO3 + offset, |
221 | frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24)); |
222 | |
223 | WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, |
224 | HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ |
225 | ~HDMI_AVI_INFO_LINE_MASK); |
226 | } |
227 | |
228 | void dce4_hdmi_audio_set_dto(struct radeon_device *rdev, |
229 | struct radeon_crtc *crtc, unsigned int clock) |
230 | { |
231 | unsigned int max_ratio = clock / 24000; |
232 | u32 dto_phase; |
233 | u32 wallclock_ratio; |
234 | u32 value; |
235 | |
236 | if (max_ratio >= 8) { |
237 | dto_phase = 192 * 1000; |
238 | wallclock_ratio = 3; |
239 | } else if (max_ratio >= 4) { |
240 | dto_phase = 96 * 1000; |
241 | wallclock_ratio = 2; |
242 | } else if (max_ratio >= 2) { |
243 | dto_phase = 48 * 1000; |
244 | wallclock_ratio = 1; |
245 | } else { |
246 | dto_phase = 24 * 1000; |
247 | wallclock_ratio = 0; |
248 | } |
249 | |
250 | value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
251 | value |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio); |
252 | value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO; |
253 | WREG32(DCCG_AUDIO_DTO0_CNTL, value); |
254 | |
255 | /* Two dtos; generally use dto0 for HDMI */ |
256 | value = 0; |
257 | |
258 | if (crtc) |
259 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
260 | |
261 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); |
262 | |
263 | /* Express [24MHz / target pixel clock] as an exact rational |
264 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
265 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
266 | */ |
267 | WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); |
268 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock); |
269 | } |
270 | |
271 | void dce4_dp_audio_set_dto(struct radeon_device *rdev, |
272 | struct radeon_crtc *crtc, unsigned int clock) |
273 | { |
274 | u32 value; |
275 | |
276 | value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK; |
277 | value |= DCCG_AUDIO_DTO1_USE_512FBR_DTO; |
278 | WREG32(DCCG_AUDIO_DTO1_CNTL, value); |
279 | |
280 | /* Two dtos; generally use dto1 for DP */ |
281 | value = 0; |
282 | value |= DCCG_AUDIO_DTO_SEL; |
283 | |
284 | if (crtc) |
285 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
286 | |
287 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); |
288 | |
289 | /* Express [24MHz / target pixel clock] as an exact rational |
290 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
291 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
292 | */ |
293 | if (ASIC_IS_DCE41(rdev)) { |
294 | unsigned int div = (RREG32(DCE41_DENTIST_DISPCLK_CNTL) & |
295 | DENTIST_DPREFCLK_WDIVIDER_MASK) >> |
296 | DENTIST_DPREFCLK_WDIVIDER_SHIFT; |
297 | div = radeon_audio_decode_dfs_div(div); |
298 | |
299 | if (div) |
300 | clock = 100 * clock / div; |
301 | } |
302 | |
303 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); |
304 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock); |
305 | } |
306 | |
307 | void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset) |
308 | { |
309 | struct drm_device *dev = encoder->dev; |
310 | struct radeon_device *rdev = dev->dev_private; |
311 | |
312 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
313 | HDMI_NULL_SEND | /* send null packets when required */ |
314 | HDMI_GC_SEND | /* send general control packets */ |
315 | HDMI_GC_CONT); /* send general control packets every frame */ |
316 | } |
317 | |
318 | void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc) |
319 | { |
320 | struct drm_device *dev = encoder->dev; |
321 | struct radeon_device *rdev = dev->dev_private; |
322 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
323 | uint32_t val; |
324 | |
325 | val = RREG32(HDMI_CONTROL + offset); |
326 | val &= ~HDMI_DEEP_COLOR_ENABLE; |
327 | val &= ~HDMI_DEEP_COLOR_DEPTH_MASK; |
328 | |
329 | switch (bpc) { |
330 | case 0: |
331 | case 6: |
332 | case 8: |
333 | case 16: |
334 | default: |
335 | DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n" , |
336 | connector->name, bpc); |
337 | break; |
338 | case 10: |
339 | val |= HDMI_DEEP_COLOR_ENABLE; |
340 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR); |
341 | DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n" , |
342 | connector->name); |
343 | break; |
344 | case 12: |
345 | val |= HDMI_DEEP_COLOR_ENABLE; |
346 | val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR); |
347 | DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n" , |
348 | connector->name); |
349 | break; |
350 | } |
351 | |
352 | WREG32(HDMI_CONTROL + offset, val); |
353 | } |
354 | |
355 | void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset) |
356 | { |
357 | struct drm_device *dev = encoder->dev; |
358 | struct radeon_device *rdev = dev->dev_private; |
359 | |
360 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, |
361 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ |
362 | |
363 | WREG32(AFMT_60958_0 + offset, |
364 | AFMT_60958_CS_CHANNEL_NUMBER_L(1)); |
365 | |
366 | WREG32(AFMT_60958_1 + offset, |
367 | AFMT_60958_CS_CHANNEL_NUMBER_R(2)); |
368 | |
369 | WREG32(AFMT_60958_2 + offset, |
370 | AFMT_60958_CS_CHANNEL_NUMBER_2(3) | |
371 | AFMT_60958_CS_CHANNEL_NUMBER_3(4) | |
372 | AFMT_60958_CS_CHANNEL_NUMBER_4(5) | |
373 | AFMT_60958_CS_CHANNEL_NUMBER_5(6) | |
374 | AFMT_60958_CS_CHANNEL_NUMBER_6(7) | |
375 | AFMT_60958_CS_CHANNEL_NUMBER_7(8)); |
376 | |
377 | WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, |
378 | AFMT_AUDIO_CHANNEL_ENABLE(0xff)); |
379 | |
380 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, |
381 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ |
382 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
383 | |
384 | /* allow 60958 channel status and send audio packets fields to be updated */ |
385 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, |
386 | AFMT_RESET_FIFO_WHEN_AUDIO_DIS | AFMT_60958_CS_UPDATE); |
387 | } |
388 | |
389 | |
390 | void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute) |
391 | { |
392 | struct drm_device *dev = encoder->dev; |
393 | struct radeon_device *rdev = dev->dev_private; |
394 | |
395 | if (mute) |
396 | WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE); |
397 | else |
398 | WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE); |
399 | } |
400 | |
401 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) |
402 | { |
403 | struct drm_device *dev = encoder->dev; |
404 | struct radeon_device *rdev = dev->dev_private; |
405 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
406 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
407 | |
408 | if (!dig || !dig->afmt) |
409 | return; |
410 | |
411 | if (enable) { |
412 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
413 | |
414 | if (connector && drm_detect_monitor_audio(edid: radeon_connector_edid(connector))) { |
415 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, |
416 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ |
417 | HDMI_AVI_INFO_CONT | /* required for audio info values to be updated */ |
418 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
419 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ |
420 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
421 | AFMT_AUDIO_SAMPLE_SEND); |
422 | } else { |
423 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, |
424 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ |
425 | HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ |
426 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
427 | ~AFMT_AUDIO_SAMPLE_SEND); |
428 | } |
429 | } else { |
430 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
431 | ~AFMT_AUDIO_SAMPLE_SEND); |
432 | WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0); |
433 | } |
434 | |
435 | dig->afmt->enabled = enable; |
436 | |
437 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n" , |
438 | enable ? "En" : "Dis" , dig->afmt->offset, radeon_encoder->encoder_id); |
439 | } |
440 | |
441 | void evergreen_dp_enable(struct drm_encoder *encoder, bool enable) |
442 | { |
443 | struct drm_device *dev = encoder->dev; |
444 | struct radeon_device *rdev = dev->dev_private; |
445 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
446 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
447 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
448 | |
449 | if (!dig || !dig->afmt) |
450 | return; |
451 | |
452 | if (enable && connector && |
453 | drm_detect_monitor_audio(edid: radeon_connector_edid(connector))) { |
454 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
455 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
456 | struct radeon_connector_atom_dig *dig_connector; |
457 | uint32_t val; |
458 | |
459 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
460 | AFMT_AUDIO_SAMPLE_SEND); |
461 | |
462 | WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset, |
463 | EVERGREEN_DP_SEC_TIMESTAMP_MODE(1)); |
464 | |
465 | if (!ASIC_IS_DCE6(rdev) && radeon_connector->con_priv) { |
466 | dig_connector = radeon_connector->con_priv; |
467 | val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset); |
468 | val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf); |
469 | |
470 | if (dig_connector->dp_clock == 162000) |
471 | val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3); |
472 | else |
473 | val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5); |
474 | |
475 | WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val); |
476 | } |
477 | |
478 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, |
479 | EVERGREEN_DP_SEC_ASP_ENABLE | /* Audio packet transmission */ |
480 | EVERGREEN_DP_SEC_ATP_ENABLE | /* Audio timestamp packet transmission */ |
481 | EVERGREEN_DP_SEC_AIP_ENABLE | /* Audio infoframe packet transmission */ |
482 | EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */ |
483 | } else { |
484 | WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0); |
485 | WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, |
486 | ~AFMT_AUDIO_SAMPLE_SEND); |
487 | } |
488 | |
489 | dig->afmt->enabled = enable; |
490 | } |
491 | |