1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #ifndef __KV_DPM_H__ |
24 | #define __KV_DPM_H__ |
25 | |
26 | #define SMU__NUM_SCLK_DPM_STATE 8 |
27 | #define SMU__NUM_MCLK_DPM_LEVELS 4 |
28 | #define SMU__NUM_LCLK_DPM_LEVELS 8 |
29 | #define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */ |
30 | #include "smu7_fusion.h" |
31 | #include "trinity_dpm.h" |
32 | #include "ppsmc.h" |
33 | |
34 | #define KV_NUM_NBPSTATES 4 |
35 | |
36 | enum kv_pt_config_reg_type { |
37 | KV_CONFIGREG_MMR = 0, |
38 | KV_CONFIGREG_SMC_IND, |
39 | KV_CONFIGREG_DIDT_IND, |
40 | KV_CONFIGREG_CACHE, |
41 | KV_CONFIGREG_MAX |
42 | }; |
43 | |
44 | struct kv_pt_config_reg { |
45 | u32 offset; |
46 | u32 mask; |
47 | u32 shift; |
48 | u32 value; |
49 | enum kv_pt_config_reg_type type; |
50 | }; |
51 | |
52 | struct kv_lcac_config_values { |
53 | u32 block_id; |
54 | u32 signal_id; |
55 | u32 t; |
56 | }; |
57 | |
58 | struct kv_lcac_config_reg { |
59 | u32 cntl; |
60 | u32 block_mask; |
61 | u32 block_shift; |
62 | u32 signal_mask; |
63 | u32 signal_shift; |
64 | u32 t_mask; |
65 | u32 t_shift; |
66 | u32 enable_mask; |
67 | u32 enable_shift; |
68 | }; |
69 | |
70 | struct kv_pl { |
71 | u32 sclk; |
72 | u8 vddc_index; |
73 | u8 ds_divider_index; |
74 | u8 ss_divider_index; |
75 | u8 allow_gnb_slow; |
76 | u8 force_nbp_state; |
77 | u8 display_wm; |
78 | u8 vce_wm; |
79 | }; |
80 | |
81 | struct kv_ps { |
82 | struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS]; |
83 | u32 num_levels; |
84 | bool need_dfs_bypass; |
85 | u8 dpm0_pg_nb_ps_lo; |
86 | u8 dpm0_pg_nb_ps_hi; |
87 | u8 dpmx_nb_ps_lo; |
88 | u8 dpmx_nb_ps_hi; |
89 | }; |
90 | |
91 | struct kv_sys_info { |
92 | u32 bootup_uma_clk; |
93 | u32 bootup_sclk; |
94 | u32 dentist_vco_freq; |
95 | u32 nb_dpm_enable; |
96 | u32 nbp_memory_clock[KV_NUM_NBPSTATES]; |
97 | u32 nbp_n_clock[KV_NUM_NBPSTATES]; |
98 | u16 bootup_nb_voltage_index; |
99 | u8 htc_tmp_lmt; |
100 | u8 htc_hyst_lmt; |
101 | struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table; |
102 | struct sumo_vid_mapping_table vid_mapping_table; |
103 | u32 uma_channel_number; |
104 | }; |
105 | |
106 | struct kv_power_info { |
107 | u32 at[SUMO_MAX_HARDWARE_POWERLEVELS]; |
108 | u32 voltage_drop_t; |
109 | struct kv_sys_info sys_info; |
110 | struct kv_pl boot_pl; |
111 | bool enable_nb_ps_policy; |
112 | bool disable_nb_ps3_in_battery; |
113 | bool video_start; |
114 | bool battery_state; |
115 | u32 lowest_valid; |
116 | u32 highest_valid; |
117 | u16 high_voltage_t; |
118 | bool cac_enabled; |
119 | bool bapm_enable; |
120 | /* smc offsets */ |
121 | u32 sram_end; |
122 | u32 dpm_table_start; |
123 | u32 soft_regs_start; |
124 | /* dpm SMU tables */ |
125 | u8 graphics_dpm_level_count; |
126 | u8 uvd_level_count; |
127 | u8 vce_level_count; |
128 | u8 acp_level_count; |
129 | u8 samu_level_count; |
130 | u16 fps_high_t; |
131 | SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE]; |
132 | SMU7_Fusion_ACPILevel acpi_level; |
133 | SMU7_Fusion_UvdLevel uvd_level[SMU7_MAX_LEVELS_UVD]; |
134 | SMU7_Fusion_ExtClkLevel vce_level[SMU7_MAX_LEVELS_VCE]; |
135 | SMU7_Fusion_ExtClkLevel acp_level[SMU7_MAX_LEVELS_ACP]; |
136 | SMU7_Fusion_ExtClkLevel samu_level[SMU7_MAX_LEVELS_SAMU]; |
137 | u8 uvd_boot_level; |
138 | u8 vce_boot_level; |
139 | u8 acp_boot_level; |
140 | u8 samu_boot_level; |
141 | u8 uvd_interval; |
142 | u8 vce_interval; |
143 | u8 acp_interval; |
144 | u8 samu_interval; |
145 | u8 graphics_boot_level; |
146 | u8 graphics_interval; |
147 | u8 graphics_therm_throttle_enable; |
148 | u8 graphics_voltage_change_enable; |
149 | u8 graphics_clk_slow_enable; |
150 | u8 graphics_clk_slow_divider; |
151 | u8 fps_low_t; |
152 | u32 low_sclk_interrupt_t; |
153 | bool uvd_power_gated; |
154 | bool vce_power_gated; |
155 | bool acp_power_gated; |
156 | bool samu_power_gated; |
157 | bool nb_dpm_enabled; |
158 | /* flags */ |
159 | bool enable_didt; |
160 | bool enable_dpm; |
161 | bool enable_auto_thermal_throttling; |
162 | bool enable_nb_dpm; |
163 | /* caps */ |
164 | bool caps_cac; |
165 | bool caps_power_containment; |
166 | bool caps_sq_ramping; |
167 | bool caps_db_ramping; |
168 | bool caps_td_ramping; |
169 | bool caps_tcp_ramping; |
170 | bool caps_sclk_throttle_low_notification; |
171 | bool caps_fps; |
172 | bool caps_uvd_dpm; |
173 | bool caps_uvd_pg; |
174 | bool caps_vce_pg; |
175 | bool caps_samu_pg; |
176 | bool caps_acp_pg; |
177 | bool caps_stable_p_state; |
178 | bool caps_enable_dfs_bypass; |
179 | bool caps_sclk_ds; |
180 | struct radeon_ps current_rps; |
181 | struct kv_ps current_ps; |
182 | struct radeon_ps requested_rps; |
183 | struct kv_ps requested_ps; |
184 | }; |
185 | |
186 | |
187 | /* kv_smc.c */ |
188 | int kv_notify_message_to_smu(struct radeon_device *rdev, u32 id); |
189 | int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask); |
190 | int kv_send_msg_to_smc_with_parameter(struct radeon_device *rdev, |
191 | PPSMC_Msg msg, u32 parameter); |
192 | int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, |
193 | u32 *value, u32 limit); |
194 | int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable); |
195 | int kv_smc_bapm_enable(struct radeon_device *rdev, bool enable); |
196 | int kv_copy_bytes_to_smc(struct radeon_device *rdev, |
197 | u32 smc_start_address, |
198 | const u8 *src, u32 byte_count, u32 limit); |
199 | |
200 | #endif |
201 | |