1 | /* |
2 | * Copyright 2012 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #ifndef __NI_DPM_H__ |
24 | #define __NI_DPM_H__ |
25 | |
26 | #include "cypress_dpm.h" |
27 | #include "btc_dpm.h" |
28 | #include "nislands_smc.h" |
29 | |
30 | struct ni_clock_registers { |
31 | u32 cg_spll_func_cntl; |
32 | u32 cg_spll_func_cntl_2; |
33 | u32 cg_spll_func_cntl_3; |
34 | u32 cg_spll_func_cntl_4; |
35 | u32 cg_spll_spread_spectrum; |
36 | u32 cg_spll_spread_spectrum_2; |
37 | u32 mclk_pwrmgt_cntl; |
38 | u32 dll_cntl; |
39 | u32 mpll_ad_func_cntl; |
40 | u32 mpll_ad_func_cntl_2; |
41 | u32 mpll_dq_func_cntl; |
42 | u32 mpll_dq_func_cntl_2; |
43 | u32 mpll_ss1; |
44 | u32 mpll_ss2; |
45 | }; |
46 | |
47 | struct ni_mc_reg_entry { |
48 | u32 mclk_max; |
49 | u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; |
50 | }; |
51 | |
52 | struct ni_mc_reg_table { |
53 | u8 last; |
54 | u8 num_entries; |
55 | u16 valid_flag; |
56 | struct ni_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; |
57 | SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; |
58 | }; |
59 | |
60 | #define NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT 2 |
61 | |
62 | enum ni_dc_cac_level |
63 | { |
64 | NISLANDS_DCCAC_LEVEL_0 = 0, |
65 | NISLANDS_DCCAC_LEVEL_1, |
66 | NISLANDS_DCCAC_LEVEL_2, |
67 | NISLANDS_DCCAC_LEVEL_3, |
68 | NISLANDS_DCCAC_LEVEL_4, |
69 | NISLANDS_DCCAC_LEVEL_5, |
70 | NISLANDS_DCCAC_LEVEL_6, |
71 | NISLANDS_DCCAC_LEVEL_7, |
72 | NISLANDS_DCCAC_MAX_LEVELS |
73 | }; |
74 | |
75 | struct ni_leakage_coeffients |
76 | { |
77 | u32 at; |
78 | u32 bt; |
79 | u32 av; |
80 | u32 bv; |
81 | s32 t_slope; |
82 | s32 t_intercept; |
83 | u32 t_ref; |
84 | }; |
85 | |
86 | struct ni_cac_data |
87 | { |
88 | struct ni_leakage_coeffients leakage_coefficients; |
89 | u32 i_leakage; |
90 | s32 leakage_minimum_temperature; |
91 | u32 pwr_const; |
92 | u32 dc_cac_value; |
93 | u32 bif_cac_value; |
94 | u32 lkge_pwr; |
95 | u8 mc_wr_weight; |
96 | u8 mc_rd_weight; |
97 | u8 allow_ovrflw; |
98 | u8 num_win_tdp; |
99 | u8 l2num_win_tdp; |
100 | u8 lts_truncate_n; |
101 | }; |
102 | |
103 | struct ni_cac_weights |
104 | { |
105 | u32 weight_tcp_sig0; |
106 | u32 weight_tcp_sig1; |
107 | u32 weight_ta_sig; |
108 | u32 weight_tcc_en0; |
109 | u32 weight_tcc_en1; |
110 | u32 weight_tcc_en2; |
111 | u32 weight_cb_en0; |
112 | u32 weight_cb_en1; |
113 | u32 weight_cb_en2; |
114 | u32 weight_cb_en3; |
115 | u32 weight_db_sig0; |
116 | u32 weight_db_sig1; |
117 | u32 weight_db_sig2; |
118 | u32 weight_db_sig3; |
119 | u32 weight_sxm_sig0; |
120 | u32 weight_sxm_sig1; |
121 | u32 weight_sxm_sig2; |
122 | u32 weight_sxs_sig0; |
123 | u32 weight_sxs_sig1; |
124 | u32 weight_xbr_0; |
125 | u32 weight_xbr_1; |
126 | u32 weight_xbr_2; |
127 | u32 weight_spi_sig0; |
128 | u32 weight_spi_sig1; |
129 | u32 weight_spi_sig2; |
130 | u32 weight_spi_sig3; |
131 | u32 weight_spi_sig4; |
132 | u32 weight_spi_sig5; |
133 | u32 weight_lds_sig0; |
134 | u32 weight_lds_sig1; |
135 | u32 weight_sc; |
136 | u32 weight_bif; |
137 | u32 weight_cp; |
138 | u32 weight_pa_sig0; |
139 | u32 weight_pa_sig1; |
140 | u32 weight_vgt_sig0; |
141 | u32 weight_vgt_sig1; |
142 | u32 weight_vgt_sig2; |
143 | u32 weight_dc_sig0; |
144 | u32 weight_dc_sig1; |
145 | u32 weight_dc_sig2; |
146 | u32 weight_dc_sig3; |
147 | u32 weight_uvd_sig0; |
148 | u32 weight_uvd_sig1; |
149 | u32 weight_spare0; |
150 | u32 weight_spare1; |
151 | u32 weight_sq_vsp; |
152 | u32 weight_sq_vsp0; |
153 | u32 weight_sq_gpr; |
154 | u32 ovr_mode_spare_0; |
155 | u32 ovr_val_spare_0; |
156 | u32 ovr_mode_spare_1; |
157 | u32 ovr_val_spare_1; |
158 | u32 vsp; |
159 | u32 vsp0; |
160 | u32 gpr; |
161 | u8 mc_read_weight; |
162 | u8 mc_write_weight; |
163 | u32 tid_cnt; |
164 | u32 tid_unit; |
165 | u32 l2_lta_window_size; |
166 | u32 lts_truncate; |
167 | u32 dc_cac[NISLANDS_DCCAC_MAX_LEVELS]; |
168 | u32 pcie_cac[SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES]; |
169 | bool enable_power_containment_by_default; |
170 | }; |
171 | |
172 | struct ni_ps { |
173 | u16 performance_level_count; |
174 | bool dc_compatible; |
175 | struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; |
176 | }; |
177 | |
178 | struct ni_power_info { |
179 | /* must be first! */ |
180 | struct evergreen_power_info eg; |
181 | struct ni_clock_registers clock_registers; |
182 | struct ni_mc_reg_table mc_reg_table; |
183 | u32 mclk_rtt_mode_threshold; |
184 | /* flags */ |
185 | bool use_power_boost_limit; |
186 | bool support_cac_long_term_average; |
187 | bool cac_enabled; |
188 | bool cac_configuration_required; |
189 | bool driver_calculate_cac_leakage; |
190 | bool pc_enabled; |
191 | bool enable_power_containment; |
192 | bool enable_cac; |
193 | bool enable_sq_ramping; |
194 | /* smc offsets */ |
195 | u16 arb_table_start; |
196 | u16 fan_table_start; |
197 | u16 cac_table_start; |
198 | u16 spll_table_start; |
199 | /* CAC stuff */ |
200 | struct ni_cac_data cac_data; |
201 | u32 dc_cac_table[NISLANDS_DCCAC_MAX_LEVELS]; |
202 | const struct ni_cac_weights *cac_weights; |
203 | u8 lta_window_size; |
204 | u8 lts_truncate; |
205 | struct ni_ps current_ps; |
206 | struct ni_ps requested_ps; |
207 | /* scratch structs */ |
208 | SMC_NIslands_MCRegisters smc_mc_reg_table; |
209 | NISLANDS_SMC_STATETABLE smc_statetable; |
210 | }; |
211 | |
212 | #define NISLANDS_INITIAL_STATE_ARB_INDEX 0 |
213 | #define NISLANDS_ACPI_STATE_ARB_INDEX 1 |
214 | #define NISLANDS_ULV_STATE_ARB_INDEX 2 |
215 | #define NISLANDS_DRIVER_STATE_ARB_INDEX 3 |
216 | |
217 | #define NISLANDS_DPM2_MAX_PULSE_SKIP 256 |
218 | |
219 | #define NISLANDS_DPM2_NEAR_TDP_DEC 10 |
220 | #define NISLANDS_DPM2_ABOVE_SAFE_INC 5 |
221 | #define NISLANDS_DPM2_BELOW_SAFE_INC 20 |
222 | |
223 | #define NISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT 80 |
224 | |
225 | #define NISLANDS_DPM2_MAXPS_PERCENT_H 90 |
226 | #define NISLANDS_DPM2_MAXPS_PERCENT_M 0 |
227 | |
228 | #define NISLANDS_DPM2_SQ_RAMP_MAX_POWER 0x3FFF |
229 | #define NISLANDS_DPM2_SQ_RAMP_MIN_POWER 0x12 |
230 | #define NISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15 |
231 | #define NISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E |
232 | #define NISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF |
233 | |
234 | int ni_copy_and_switch_arb_sets(struct radeon_device *rdev, |
235 | u32 arb_freq_src, u32 arb_freq_dest); |
236 | void ni_update_current_ps(struct radeon_device *rdev, |
237 | struct radeon_ps *rps); |
238 | void ni_update_requested_ps(struct radeon_device *rdev, |
239 | struct radeon_ps *rps); |
240 | |
241 | void ni_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, |
242 | struct radeon_ps *new_ps, |
243 | struct radeon_ps *old_ps); |
244 | void ni_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, |
245 | struct radeon_ps *new_ps, |
246 | struct radeon_ps *old_ps); |
247 | |
248 | bool ni_dpm_vblank_too_short(struct radeon_device *rdev); |
249 | |
250 | struct ni_power_info *ni_get_pi(struct radeon_device *rdev); |
251 | struct ni_ps *ni_get_ps(struct radeon_ps *rps); |
252 | |
253 | #endif |
254 | |