1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <drm/drmP.h>
25#include "radeon.h"
26#include "radeon_asic.h"
27#include "r600d.h"
28
29u32 r600_gpu_check_soft_reset(struct radeon_device *rdev);
30
31/*
32 * DMA
33 * Starting with R600, the GPU has an asynchronous
34 * DMA engine. The programming model is very similar
35 * to the 3D engine (ring buffer, IBs, etc.), but the
36 * DMA controller has it's own packet format that is
37 * different form the PM4 format used by the 3D engine.
38 * It supports copying data, writing embedded data,
39 * solid fills, and a number of other things. It also
40 * has support for tiling/detiling of buffers.
41 */
42
43/**
44 * r600_dma_get_rptr - get the current read pointer
45 *
46 * @rdev: radeon_device pointer
47 * @ring: radeon ring pointer
48 *
49 * Get the current rptr from the hardware (r6xx+).
50 */
51uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
52 struct radeon_ring *ring)
53{
54 u32 rptr;
55
56 if (rdev->wb.enabled)
57 rptr = rdev->wb.wb[ring->rptr_offs/4];
58 else
59 rptr = RREG32(DMA_RB_RPTR);
60
61 return (rptr & 0x3fffc) >> 2;
62}
63
64/**
65 * r600_dma_get_wptr - get the current write pointer
66 *
67 * @rdev: radeon_device pointer
68 * @ring: radeon ring pointer
69 *
70 * Get the current wptr from the hardware (r6xx+).
71 */
72uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
73 struct radeon_ring *ring)
74{
75 return (RREG32(DMA_RB_WPTR) & 0x3fffc) >> 2;
76}
77
78/**
79 * r600_dma_set_wptr - commit the write pointer
80 *
81 * @rdev: radeon_device pointer
82 * @ring: radeon ring pointer
83 *
84 * Write the wptr back to the hardware (r6xx+).
85 */
86void r600_dma_set_wptr(struct radeon_device *rdev,
87 struct radeon_ring *ring)
88{
89 WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc);
90}
91
92/**
93 * r600_dma_stop - stop the async dma engine
94 *
95 * @rdev: radeon_device pointer
96 *
97 * Stop the async dma engine (r6xx-evergreen).
98 */
99void r600_dma_stop(struct radeon_device *rdev)
100{
101 u32 rb_cntl = RREG32(DMA_RB_CNTL);
102
103 if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX)
104 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
105
106 rb_cntl &= ~DMA_RB_ENABLE;
107 WREG32(DMA_RB_CNTL, rb_cntl);
108
109 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
110}
111
112/**
113 * r600_dma_resume - setup and start the async dma engine
114 *
115 * @rdev: radeon_device pointer
116 *
117 * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
118 * Returns 0 for success, error for failure.
119 */
120int r600_dma_resume(struct radeon_device *rdev)
121{
122 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
123 u32 rb_cntl, dma_cntl, ib_cntl;
124 u32 rb_bufsz;
125 int r;
126
127 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
128 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
129
130 /* Set ring buffer size in dwords */
131 rb_bufsz = order_base_2(ring->ring_size / 4);
132 rb_cntl = rb_bufsz << 1;
133#ifdef __BIG_ENDIAN
134 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
135#endif
136 WREG32(DMA_RB_CNTL, rb_cntl);
137
138 /* Initialize the ring buffer's read and write pointers */
139 WREG32(DMA_RB_RPTR, 0);
140 WREG32(DMA_RB_WPTR, 0);
141
142 /* set the wb address whether it's enabled or not */
143 WREG32(DMA_RB_RPTR_ADDR_HI,
144 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
145 WREG32(DMA_RB_RPTR_ADDR_LO,
146 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
147
148 if (rdev->wb.enabled)
149 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
150
151 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
152
153 /* enable DMA IBs */
154 ib_cntl = DMA_IB_ENABLE;
155#ifdef __BIG_ENDIAN
156 ib_cntl |= DMA_IB_SWAP_ENABLE;
157#endif
158 WREG32(DMA_IB_CNTL, ib_cntl);
159
160 dma_cntl = RREG32(DMA_CNTL);
161 dma_cntl &= ~CTXEMPTY_INT_ENABLE;
162 WREG32(DMA_CNTL, dma_cntl);
163
164 if (rdev->family >= CHIP_RV770)
165 WREG32(DMA_MODE, 1);
166
167 ring->wptr = 0;
168 WREG32(DMA_RB_WPTR, ring->wptr << 2);
169
170 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
171
172 ring->ready = true;
173
174 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
175 if (r) {
176 ring->ready = false;
177 return r;
178 }
179
180 if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX)
181 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
182
183 return 0;
184}
185
186/**
187 * r600_dma_fini - tear down the async dma engine
188 *
189 * @rdev: radeon_device pointer
190 *
191 * Stop the async dma engine and free the ring (r6xx-evergreen).
192 */
193void r600_dma_fini(struct radeon_device *rdev)
194{
195 r600_dma_stop(rdev);
196 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
197}
198
199/**
200 * r600_dma_is_lockup - Check if the DMA engine is locked up
201 *
202 * @rdev: radeon_device pointer
203 * @ring: radeon_ring structure holding ring information
204 *
205 * Check if the async DMA engine is locked up.
206 * Returns true if the engine appears to be locked up, false if not.
207 */
208bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
209{
210 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
211
212 if (!(reset_mask & RADEON_RESET_DMA)) {
213 radeon_ring_lockup_update(rdev, ring);
214 return false;
215 }
216 return radeon_ring_test_lockup(rdev, ring);
217}
218
219
220/**
221 * r600_dma_ring_test - simple async dma engine test
222 *
223 * @rdev: radeon_device pointer
224 * @ring: radeon_ring structure holding ring information
225 *
226 * Test the DMA engine by writing using it to write an
227 * value to memory. (r6xx-SI).
228 * Returns 0 for success, error for failure.
229 */
230int r600_dma_ring_test(struct radeon_device *rdev,
231 struct radeon_ring *ring)
232{
233 unsigned i;
234 int r;
235 unsigned index;
236 u32 tmp;
237 u64 gpu_addr;
238
239 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
240 index = R600_WB_DMA_RING_TEST_OFFSET;
241 else
242 index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
243
244 gpu_addr = rdev->wb.gpu_addr + index;
245
246 tmp = 0xCAFEDEAD;
247 rdev->wb.wb[index/4] = cpu_to_le32(tmp);
248
249 r = radeon_ring_lock(rdev, ring, 4);
250 if (r) {
251 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
252 return r;
253 }
254 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
255 radeon_ring_write(ring, lower_32_bits(gpu_addr));
256 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);
257 radeon_ring_write(ring, 0xDEADBEEF);
258 radeon_ring_unlock_commit(rdev, ring, false);
259
260 for (i = 0; i < rdev->usec_timeout; i++) {
261 tmp = le32_to_cpu(rdev->wb.wb[index/4]);
262 if (tmp == 0xDEADBEEF)
263 break;
264 DRM_UDELAY(1);
265 }
266
267 if (i < rdev->usec_timeout) {
268 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
269 } else {
270 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
271 ring->idx, tmp);
272 r = -EINVAL;
273 }
274 return r;
275}
276
277/**
278 * r600_dma_fence_ring_emit - emit a fence on the DMA ring
279 *
280 * @rdev: radeon_device pointer
281 * @fence: radeon fence object
282 *
283 * Add a DMA fence packet to the ring to write
284 * the fence seq number and DMA trap packet to generate
285 * an interrupt if needed (r6xx-r7xx).
286 */
287void r600_dma_fence_ring_emit(struct radeon_device *rdev,
288 struct radeon_fence *fence)
289{
290 struct radeon_ring *ring = &rdev->ring[fence->ring];
291 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
292
293 /* write the fence */
294 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
295 radeon_ring_write(ring, addr & 0xfffffffc);
296 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
297 radeon_ring_write(ring, lower_32_bits(fence->seq));
298 /* generate an interrupt */
299 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
300}
301
302/**
303 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
304 *
305 * @rdev: radeon_device pointer
306 * @ring: radeon_ring structure holding ring information
307 * @semaphore: radeon semaphore object
308 * @emit_wait: wait or signal semaphore
309 *
310 * Add a DMA semaphore packet to the ring wait on or signal
311 * other rings (r6xx-SI).
312 */
313bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
314 struct radeon_ring *ring,
315 struct radeon_semaphore *semaphore,
316 bool emit_wait)
317{
318 u64 addr = semaphore->gpu_addr;
319 u32 s = emit_wait ? 0 : 1;
320
321 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
322 radeon_ring_write(ring, addr & 0xfffffffc);
323 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
324
325 return true;
326}
327
328/**
329 * r600_dma_ib_test - test an IB on the DMA engine
330 *
331 * @rdev: radeon_device pointer
332 * @ring: radeon_ring structure holding ring information
333 *
334 * Test a simple IB in the DMA ring (r6xx-SI).
335 * Returns 0 on success, error on failure.
336 */
337int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
338{
339 struct radeon_ib ib;
340 unsigned i;
341 unsigned index;
342 int r;
343 u32 tmp = 0;
344 u64 gpu_addr;
345
346 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
347 index = R600_WB_DMA_RING_TEST_OFFSET;
348 else
349 index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
350
351 gpu_addr = rdev->wb.gpu_addr + index;
352
353 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
354 if (r) {
355 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
356 return r;
357 }
358
359 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
360 ib.ptr[1] = lower_32_bits(gpu_addr);
361 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff;
362 ib.ptr[3] = 0xDEADBEEF;
363 ib.length_dw = 4;
364
365 r = radeon_ib_schedule(rdev, &ib, NULL, false);
366 if (r) {
367 radeon_ib_free(rdev, &ib);
368 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
369 return r;
370 }
371 r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
372 RADEON_USEC_IB_TEST_TIMEOUT));
373 if (r < 0) {
374 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
375 return r;
376 } else if (r == 0) {
377 DRM_ERROR("radeon: fence wait timed out.\n");
378 return -ETIMEDOUT;
379 }
380 r = 0;
381 for (i = 0; i < rdev->usec_timeout; i++) {
382 tmp = le32_to_cpu(rdev->wb.wb[index/4]);
383 if (tmp == 0xDEADBEEF)
384 break;
385 DRM_UDELAY(1);
386 }
387 if (i < rdev->usec_timeout) {
388 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
389 } else {
390 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
391 r = -EINVAL;
392 }
393 radeon_ib_free(rdev, &ib);
394 return r;
395}
396
397/**
398 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
399 *
400 * @rdev: radeon_device pointer
401 * @ib: IB object to schedule
402 *
403 * Schedule an IB in the DMA ring (r6xx-r7xx).
404 */
405void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
406{
407 struct radeon_ring *ring = &rdev->ring[ib->ring];
408
409 if (rdev->wb.enabled) {
410 u32 next_rptr = ring->wptr + 4;
411 while ((next_rptr & 7) != 5)
412 next_rptr++;
413 next_rptr += 3;
414 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
415 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
416 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
417 radeon_ring_write(ring, next_rptr);
418 }
419
420 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
421 * Pad as necessary with NOPs.
422 */
423 while ((ring->wptr & 7) != 5)
424 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
425 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
426 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
427 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
428
429}
430
431/**
432 * r600_copy_dma - copy pages using the DMA engine
433 *
434 * @rdev: radeon_device pointer
435 * @src_offset: src GPU address
436 * @dst_offset: dst GPU address
437 * @num_gpu_pages: number of GPU pages to xfer
438 * @resv: reservation object to sync to
439 *
440 * Copy GPU paging using the DMA engine (r6xx).
441 * Used by the radeon ttm implementation to move pages if
442 * registered as the asic copy callback.
443 */
444struct radeon_fence *r600_copy_dma(struct radeon_device *rdev,
445 uint64_t src_offset, uint64_t dst_offset,
446 unsigned num_gpu_pages,
447 struct reservation_object *resv)
448{
449 struct radeon_fence *fence;
450 struct radeon_sync sync;
451 int ring_index = rdev->asic->copy.dma_ring_index;
452 struct radeon_ring *ring = &rdev->ring[ring_index];
453 u32 size_in_dw, cur_size_in_dw;
454 int i, num_loops;
455 int r = 0;
456
457 radeon_sync_create(&sync);
458
459 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
460 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE);
461 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
462 if (r) {
463 DRM_ERROR("radeon: moving bo (%d).\n", r);
464 radeon_sync_free(rdev, &sync, NULL);
465 return ERR_PTR(r);
466 }
467
468 radeon_sync_resv(rdev, &sync, resv, false);
469 radeon_sync_rings(rdev, &sync, ring->idx);
470
471 for (i = 0; i < num_loops; i++) {
472 cur_size_in_dw = size_in_dw;
473 if (cur_size_in_dw > 0xFFFE)
474 cur_size_in_dw = 0xFFFE;
475 size_in_dw -= cur_size_in_dw;
476 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
477 radeon_ring_write(ring, dst_offset & 0xfffffffc);
478 radeon_ring_write(ring, src_offset & 0xfffffffc);
479 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
480 (upper_32_bits(src_offset) & 0xff)));
481 src_offset += cur_size_in_dw * 4;
482 dst_offset += cur_size_in_dw * 4;
483 }
484
485 r = radeon_fence_emit(rdev, &fence, ring->idx);
486 if (r) {
487 radeon_ring_unlock_undo(rdev, ring);
488 radeon_sync_free(rdev, &sync, NULL);
489 return ERR_PTR(r);
490 }
491
492 radeon_ring_unlock_commit(rdev, ring, false);
493 radeon_sync_free(rdev, &sync, fence);
494
495 return fence;
496}
497