1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __R600_REG_H__
29#define __R600_REG_H__
30
31#define R600_PCIE_PORT_INDEX 0x0038
32#define R600_PCIE_PORT_DATA 0x003c
33
34#define R600_RCU_INDEX 0x0100
35#define R600_RCU_DATA 0x0104
36
37#define R600_UVD_CTX_INDEX 0xf4a0
38#define R600_UVD_CTX_DATA 0xf4a4
39
40#define R600_MC_VM_FB_LOCATION 0x2180
41#define R600_MC_FB_BASE_MASK 0x0000FFFF
42#define R600_MC_FB_BASE_SHIFT 0
43#define R600_MC_FB_TOP_MASK 0xFFFF0000
44#define R600_MC_FB_TOP_SHIFT 16
45#define R600_MC_VM_AGP_TOP 0x2184
46#define R600_MC_AGP_TOP_MASK 0x0003FFFF
47#define R600_MC_AGP_TOP_SHIFT 0
48#define R600_MC_VM_AGP_BOT 0x2188
49#define R600_MC_AGP_BOT_MASK 0x0003FFFF
50#define R600_MC_AGP_BOT_SHIFT 0
51#define R600_MC_VM_AGP_BASE 0x218c
52#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
53#define R600_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF
54#define R600_LOGICAL_PAGE_NUMBER_SHIFT 0
55#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
56#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
57
58#define R700_MC_VM_FB_LOCATION 0x2024
59#define R700_MC_FB_BASE_MASK 0x0000FFFF
60#define R700_MC_FB_BASE_SHIFT 0
61#define R700_MC_FB_TOP_MASK 0xFFFF0000
62#define R700_MC_FB_TOP_SHIFT 16
63#define R700_MC_VM_AGP_TOP 0x2028
64#define R700_MC_AGP_TOP_MASK 0x0003FFFF
65#define R700_MC_AGP_TOP_SHIFT 0
66#define R700_MC_VM_AGP_BOT 0x202c
67#define R700_MC_AGP_BOT_MASK 0x0003FFFF
68#define R700_MC_AGP_BOT_SHIFT 0
69#define R700_MC_VM_AGP_BASE 0x2030
70#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
71#define R700_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF
72#define R700_LOGICAL_PAGE_NUMBER_SHIFT 0
73#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
74#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c
75
76#define R600_RAMCFG 0x2408
77# define R600_CHANSIZE (1 << 7)
78# define R600_CHANSIZE_OVERRIDE (1 << 10)
79
80
81#define R600_GENERAL_PWRMGT 0x618
82# define R600_OPEN_DRAIN_PADS (1 << 11)
83
84#define R600_LOWER_GPIO_ENABLE 0x710
85#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718
86#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c
87#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720
88#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724
89
90#define R600_D1GRPH_SWAP_CONTROL 0x610C
91# define R600_D1GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)
92# define R600_D1GRPH_SWAP_ENDIAN_NONE 0
93# define R600_D1GRPH_SWAP_ENDIAN_16BIT 1
94# define R600_D1GRPH_SWAP_ENDIAN_32BIT 2
95# define R600_D1GRPH_SWAP_ENDIAN_64BIT 3
96# define R600_D1GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)
97# define R600_D1GRPH_RED_SEL_R 0
98# define R600_D1GRPH_RED_SEL_G 1
99# define R600_D1GRPH_RED_SEL_B 2
100# define R600_D1GRPH_RED_SEL_A 3
101# define R600_D1GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)
102# define R600_D1GRPH_GREEN_SEL_G 0
103# define R600_D1GRPH_GREEN_SEL_B 1
104# define R600_D1GRPH_GREEN_SEL_A 2
105# define R600_D1GRPH_GREEN_SEL_R 3
106# define R600_D1GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)
107# define R600_D1GRPH_BLUE_SEL_B 0
108# define R600_D1GRPH_BLUE_SEL_A 1
109# define R600_D1GRPH_BLUE_SEL_R 2
110# define R600_D1GRPH_BLUE_SEL_G 3
111# define R600_D1GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10)
112# define R600_D1GRPH_ALPHA_SEL_A 0
113# define R600_D1GRPH_ALPHA_SEL_R 1
114# define R600_D1GRPH_ALPHA_SEL_G 2
115# define R600_D1GRPH_ALPHA_SEL_B 3
116
117#define R600_HDP_NONSURFACE_BASE 0x2c04
118
119#define R600_BUS_CNTL 0x5420
120# define R600_BIOS_ROM_DIS (1 << 1)
121#define R600_CONFIG_CNTL 0x5424
122#define R600_CONFIG_MEMSIZE 0x5428
123#define R600_CONFIG_F0_BASE 0x542C
124#define R600_CONFIG_APER_SIZE 0x5430
125
126#define R600_BIF_FB_EN 0x5490
127#define R600_FB_READ_EN (1 << 0)
128#define R600_FB_WRITE_EN (1 << 1)
129
130#define R600_CITF_CNTL 0x200c
131#define R600_BLACKOUT_MASK 0x00000003
132
133#define R700_MC_CITF_CNTL 0x25c0
134
135#define R600_ROM_CNTL 0x1600
136# define R600_SCK_OVERWRITE (1 << 1)
137# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
138# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)
139
140#define R600_CG_SPLL_FUNC_CNTL 0x600
141# define R600_SPLL_BYPASS_EN (1 << 3)
142#define R600_CG_SPLL_STATUS 0x60c
143# define R600_SPLL_CHG_STATUS (1 << 1)
144
145#define R600_BIOS_0_SCRATCH 0x1724
146#define R600_BIOS_1_SCRATCH 0x1728
147#define R600_BIOS_2_SCRATCH 0x172c
148#define R600_BIOS_3_SCRATCH 0x1730
149#define R600_BIOS_4_SCRATCH 0x1734
150#define R600_BIOS_5_SCRATCH 0x1738
151#define R600_BIOS_6_SCRATCH 0x173c
152#define R600_BIOS_7_SCRATCH 0x1740
153
154/* Audio, these regs were reverse enginered,
155 * so the chance is high that the naming is wrong
156 * R6xx+ ??? */
157
158/* Audio clocks */
159#define R600_AUDIO_PLL1_MUL 0x0514
160#define R600_AUDIO_PLL1_DIV 0x0518
161#define R600_AUDIO_PLL2_MUL 0x0524
162#define R600_AUDIO_PLL2_DIV 0x0528
163#define R600_AUDIO_CLK_SRCSEL 0x0534
164
165/* Audio general */
166#define R600_AUDIO_ENABLE 0x7300
167#define R600_AUDIO_TIMING 0x7344
168
169/* Audio params */
170#define R600_AUDIO_VENDOR_ID 0x7380
171#define R600_AUDIO_REVISION_ID 0x7384
172#define R600_AUDIO_ROOT_NODE_COUNT 0x7388
173#define R600_AUDIO_NID1_NODE_COUNT 0x738c
174#define R600_AUDIO_NID1_TYPE 0x7390
175#define R600_AUDIO_SUPPORTED_SIZE_RATE 0x7394
176#define R600_AUDIO_SUPPORTED_CODEC 0x7398
177#define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c
178#define R600_AUDIO_NID2_CAPS 0x73a0
179#define R600_AUDIO_NID3_CAPS 0x73a4
180#define R600_AUDIO_NID3_PIN_CAPS 0x73a8
181
182/* Audio conn list */
183#define R600_AUDIO_CONN_LIST_LEN 0x73ac
184#define R600_AUDIO_CONN_LIST 0x73b0
185
186/* Audio verbs */
187#define R600_AUDIO_RATE_BPS_CHANNEL 0x73c0
188#define R600_AUDIO_PLAYING 0x73c4
189#define R600_AUDIO_IMPLEMENTATION_ID 0x73c8
190#define R600_AUDIO_CONFIG_DEFAULT 0x73cc
191#define R600_AUDIO_PIN_SENSE 0x73d0
192#define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4
193#define R600_AUDIO_STATUS_BITS 0x73d8
194
195#define DCE2_HDMI_OFFSET0 (0x7400 - 0x7400)
196#define DCE2_HDMI_OFFSET1 (0x7700 - 0x7400)
197/* DCE3.2 second instance starts at 0x7800 */
198#define DCE3_HDMI_OFFSET0 (0x7400 - 0x7400)
199#define DCE3_HDMI_OFFSET1 (0x7800 - 0x7400)
200
201#endif
202