1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
26 | * Jerome Glisse |
27 | */ |
28 | #ifndef __RADEON_H__ |
29 | #define __RADEON_H__ |
30 | |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
34 | * related to surface |
35 | * - WB : write back stuff (do it bit like scratch reg things) |
36 | * - Vblank : look at Jesse's rework and what we should do |
37 | * - r600/r700: gart & cp |
38 | * - cs : clean cs ioctl use bitmap & things like that. |
39 | * - power management stuff |
40 | * - Barrier in gart code |
41 | * - Unmappabled vram ? |
42 | * - TESTING, TESTING, TESTING |
43 | */ |
44 | |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various |
47 | * reasons even thought we work hard to make it works on most |
48 | * configurations. In order to still have a working userspace in such |
49 | * situation the init path must succeed up to the memory controller |
50 | * initialization point. Failure before this point are considered as |
51 | * fatal error. Here is the init callchain : |
52 | * radeon_device_init perform common structure, mutex initialization |
53 | * asic_init setup the GPU memory layout and perform all |
54 | * one time initialization (failure in this |
55 | * function are considered fatal) |
56 | * asic_startup setup the GPU acceleration, in order to |
57 | * follow guideline the first thing this |
58 | * function should do is setting the GPU |
59 | * memory controller (only MC setup failure |
60 | * are considered as fatal) |
61 | */ |
62 | |
63 | #include <linux/atomic.h> |
64 | #include <linux/wait.h> |
65 | #include <linux/list.h> |
66 | #include <linux/kref.h> |
67 | #include <linux/interval_tree.h> |
68 | #include <linux/hashtable.h> |
69 | #include <linux/dma-fence.h> |
70 | |
71 | #include <drm/ttm/ttm_bo_api.h> |
72 | #include <drm/ttm/ttm_bo_driver.h> |
73 | #include <drm/ttm/ttm_placement.h> |
74 | #include <drm/ttm/ttm_module.h> |
75 | #include <drm/ttm/ttm_execbuf_util.h> |
76 | |
77 | #include <drm/drm_gem.h> |
78 | |
79 | #include "radeon_family.h" |
80 | #include "radeon_mode.h" |
81 | #include "radeon_reg.h" |
82 | |
83 | /* |
84 | * Modules parameters. |
85 | */ |
86 | extern int radeon_no_wb; |
87 | extern int radeon_modeset; |
88 | extern int radeon_dynclks; |
89 | extern int radeon_r4xx_atom; |
90 | extern int radeon_agpmode; |
91 | extern int radeon_vram_limit; |
92 | extern int radeon_gart_size; |
93 | extern int radeon_benchmarking; |
94 | extern int radeon_testing; |
95 | extern int radeon_connector_table; |
96 | extern int radeon_tv; |
97 | extern int radeon_audio; |
98 | extern int radeon_disp_priority; |
99 | extern int radeon_hw_i2c; |
100 | extern int radeon_pcie_gen2; |
101 | extern int radeon_msi; |
102 | extern int radeon_lockup_timeout; |
103 | extern int radeon_fastfb; |
104 | extern int radeon_dpm; |
105 | extern int radeon_aspm; |
106 | extern int radeon_runtime_pm; |
107 | extern int radeon_hard_reset; |
108 | extern int radeon_vm_size; |
109 | extern int radeon_vm_block_size; |
110 | extern int radeon_deep_color; |
111 | extern int radeon_use_pflipirq; |
112 | extern int radeon_bapm; |
113 | extern int radeon_backlight; |
114 | extern int radeon_auxch; |
115 | extern int radeon_mst; |
116 | extern int radeon_uvd; |
117 | extern int radeon_vce; |
118 | extern int radeon_si_support; |
119 | extern int radeon_cik_support; |
120 | |
121 | /* |
122 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
123 | * symbol; |
124 | */ |
125 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
126 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
127 | #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */ |
128 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
129 | #define RADEON_IB_POOL_SIZE 16 |
130 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 |
131 | #define RADEONFB_CONN_LIMIT 4 |
132 | #define RADEON_BIOS_NUM_SCRATCH 8 |
133 | |
134 | /* internal ring indices */ |
135 | /* r1xx+ has gfx CP ring */ |
136 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
137 | |
138 | /* cayman has 2 compute CP rings */ |
139 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
140 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 |
141 | |
142 | /* R600+ has an async dma ring */ |
143 | #define R600_RING_TYPE_DMA_INDEX 3 |
144 | /* cayman add a second async dma ring */ |
145 | #define CAYMAN_RING_TYPE_DMA1_INDEX 4 |
146 | |
147 | /* R600+ */ |
148 | #define R600_RING_TYPE_UVD_INDEX 5 |
149 | |
150 | /* TN+ */ |
151 | #define TN_RING_TYPE_VCE1_INDEX 6 |
152 | #define TN_RING_TYPE_VCE2_INDEX 7 |
153 | |
154 | /* max number of rings */ |
155 | #define RADEON_NUM_RINGS 8 |
156 | |
157 | /* number of hw syncs before falling back on blocking */ |
158 | #define RADEON_NUM_SYNCS 4 |
159 | |
160 | /* hardcode those limit for now */ |
161 | #define RADEON_VA_IB_OFFSET (1 << 20) |
162 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
163 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) |
164 | |
165 | /* hard reset data */ |
166 | #define RADEON_ASIC_RESET_DATA 0x39d5e86b |
167 | |
168 | /* reset flags */ |
169 | #define RADEON_RESET_GFX (1 << 0) |
170 | #define RADEON_RESET_COMPUTE (1 << 1) |
171 | #define RADEON_RESET_DMA (1 << 2) |
172 | #define RADEON_RESET_CP (1 << 3) |
173 | #define RADEON_RESET_GRBM (1 << 4) |
174 | #define RADEON_RESET_DMA1 (1 << 5) |
175 | #define RADEON_RESET_RLC (1 << 6) |
176 | #define RADEON_RESET_SEM (1 << 7) |
177 | #define RADEON_RESET_IH (1 << 8) |
178 | #define RADEON_RESET_VMC (1 << 9) |
179 | #define RADEON_RESET_MC (1 << 10) |
180 | #define RADEON_RESET_DISPLAY (1 << 11) |
181 | |
182 | /* CG block flags */ |
183 | #define RADEON_CG_BLOCK_GFX (1 << 0) |
184 | #define RADEON_CG_BLOCK_MC (1 << 1) |
185 | #define RADEON_CG_BLOCK_SDMA (1 << 2) |
186 | #define RADEON_CG_BLOCK_UVD (1 << 3) |
187 | #define RADEON_CG_BLOCK_VCE (1 << 4) |
188 | #define RADEON_CG_BLOCK_HDP (1 << 5) |
189 | #define RADEON_CG_BLOCK_BIF (1 << 6) |
190 | |
191 | /* CG flags */ |
192 | #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) |
193 | #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) |
194 | #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) |
195 | #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) |
196 | #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) |
197 | #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) |
198 | #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) |
199 | #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) |
200 | #define RADEON_CG_SUPPORT_MC_LS (1 << 8) |
201 | #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) |
202 | #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) |
203 | #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) |
204 | #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) |
205 | #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) |
206 | #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) |
207 | #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) |
208 | #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) |
209 | |
210 | /* PG flags */ |
211 | #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) |
212 | #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) |
213 | #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) |
214 | #define RADEON_PG_SUPPORT_UVD (1 << 3) |
215 | #define RADEON_PG_SUPPORT_VCE (1 << 4) |
216 | #define RADEON_PG_SUPPORT_CP (1 << 5) |
217 | #define RADEON_PG_SUPPORT_GDS (1 << 6) |
218 | #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) |
219 | #define RADEON_PG_SUPPORT_SDMA (1 << 8) |
220 | #define RADEON_PG_SUPPORT_ACP (1 << 9) |
221 | #define RADEON_PG_SUPPORT_SAMU (1 << 10) |
222 | |
223 | /* max cursor sizes (in pixels) */ |
224 | #define CURSOR_WIDTH 64 |
225 | #define CURSOR_HEIGHT 64 |
226 | |
227 | #define CIK_CURSOR_WIDTH 128 |
228 | #define CIK_CURSOR_HEIGHT 128 |
229 | |
230 | /* |
231 | * Errata workarounds. |
232 | */ |
233 | enum radeon_pll_errata { |
234 | CHIP_ERRATA_R300_CG = 0x00000001, |
235 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
236 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
237 | }; |
238 | |
239 | |
240 | struct radeon_device; |
241 | |
242 | |
243 | /* |
244 | * BIOS. |
245 | */ |
246 | bool radeon_get_bios(struct radeon_device *rdev); |
247 | |
248 | /* |
249 | * Dummy page |
250 | */ |
251 | struct radeon_dummy_page { |
252 | uint64_t entry; |
253 | struct page *page; |
254 | dma_addr_t addr; |
255 | }; |
256 | int radeon_dummy_page_init(struct radeon_device *rdev); |
257 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
258 | |
259 | |
260 | /* |
261 | * Clocks |
262 | */ |
263 | struct radeon_clock { |
264 | struct radeon_pll p1pll; |
265 | struct radeon_pll p2pll; |
266 | struct radeon_pll dcpll; |
267 | struct radeon_pll spll; |
268 | struct radeon_pll mpll; |
269 | /* 10 Khz units */ |
270 | uint32_t default_mclk; |
271 | uint32_t default_sclk; |
272 | uint32_t default_dispclk; |
273 | uint32_t current_dispclk; |
274 | uint32_t dp_extclk; |
275 | uint32_t max_pixel_clock; |
276 | uint32_t vco_freq; |
277 | }; |
278 | |
279 | /* |
280 | * Power management |
281 | */ |
282 | int radeon_pm_init(struct radeon_device *rdev); |
283 | int radeon_pm_late_init(struct radeon_device *rdev); |
284 | void radeon_pm_fini(struct radeon_device *rdev); |
285 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
286 | void radeon_pm_suspend(struct radeon_device *rdev); |
287 | void radeon_pm_resume(struct radeon_device *rdev); |
288 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
289 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
290 | int radeon_atom_get_clock_dividers(struct radeon_device *rdev, |
291 | u8 clock_type, |
292 | u32 clock, |
293 | bool strobe_mode, |
294 | struct atom_clock_dividers *dividers); |
295 | int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, |
296 | u32 clock, |
297 | bool strobe_mode, |
298 | struct atom_mpll_param *mpll_param); |
299 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
300 | int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, |
301 | u16 voltage_level, u8 voltage_type, |
302 | u32 *gpio_value, u32 *gpio_mask); |
303 | void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, |
304 | u32 eng_clock, u32 mem_clock); |
305 | int radeon_atom_get_voltage_step(struct radeon_device *rdev, |
306 | u8 voltage_type, u16 *voltage_step); |
307 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
308 | u16 voltage_id, u16 *voltage); |
309 | int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, |
310 | u16 *voltage, |
311 | u16 leakage_idx); |
312 | int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, |
313 | u16 *leakage_id); |
314 | int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, |
315 | u16 *vddc, u16 *vddci, |
316 | u16 virtual_voltage_id, |
317 | u16 vbios_voltage_id); |
318 | int radeon_atom_get_voltage_evv(struct radeon_device *rdev, |
319 | u16 virtual_voltage_id, |
320 | u16 *voltage); |
321 | int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, |
322 | u8 voltage_type, |
323 | u16 nominal_voltage, |
324 | u16 *true_voltage); |
325 | int radeon_atom_get_min_voltage(struct radeon_device *rdev, |
326 | u8 voltage_type, u16 *min_voltage); |
327 | int radeon_atom_get_max_voltage(struct radeon_device *rdev, |
328 | u8 voltage_type, u16 *max_voltage); |
329 | int radeon_atom_get_voltage_table(struct radeon_device *rdev, |
330 | u8 voltage_type, u8 voltage_mode, |
331 | struct atom_voltage_table *voltage_table); |
332 | bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, |
333 | u8 voltage_type, u8 voltage_mode); |
334 | int radeon_atom_get_svi2_info(struct radeon_device *rdev, |
335 | u8 voltage_type, |
336 | u8 *svd_gpio_id, u8 *svc_gpio_id); |
337 | void radeon_atom_update_memory_dll(struct radeon_device *rdev, |
338 | u32 mem_clock); |
339 | void radeon_atom_set_ac_timing(struct radeon_device *rdev, |
340 | u32 mem_clock); |
341 | int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, |
342 | u8 module_index, |
343 | struct atom_mc_reg_table *reg_table); |
344 | int radeon_atom_get_memory_info(struct radeon_device *rdev, |
345 | u8 module_index, struct atom_memory_info *mem_info); |
346 | int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, |
347 | bool gddr5, u8 module_index, |
348 | struct atom_memory_clock_range_table *mclk_range_table); |
349 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
350 | u16 voltage_id, u16 *voltage); |
351 | void rs690_pm_info(struct radeon_device *rdev); |
352 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
353 | unsigned *bankh, unsigned *mtaspect, |
354 | unsigned *tile_split); |
355 | |
356 | /* |
357 | * Fences. |
358 | */ |
359 | struct radeon_fence_driver { |
360 | struct radeon_device *rdev; |
361 | uint32_t scratch_reg; |
362 | uint64_t gpu_addr; |
363 | volatile uint32_t *cpu_addr; |
364 | /* sync_seq is protected by ring emission lock */ |
365 | uint64_t sync_seq[RADEON_NUM_RINGS]; |
366 | atomic64_t last_seq; |
367 | bool initialized, delayed_irq; |
368 | struct delayed_work lockup_work; |
369 | }; |
370 | |
371 | struct radeon_fence { |
372 | struct dma_fence base; |
373 | |
374 | struct radeon_device *rdev; |
375 | uint64_t seq; |
376 | /* RB, DMA, etc. */ |
377 | unsigned ring; |
378 | bool is_vm_update; |
379 | |
380 | wait_queue_entry_t fence_wake; |
381 | }; |
382 | |
383 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
384 | int radeon_fence_driver_init(struct radeon_device *rdev); |
385 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
386 | void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); |
387 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
388 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
389 | bool radeon_fence_signaled(struct radeon_fence *fence); |
390 | long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout); |
391 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
392 | int radeon_fence_wait_next(struct radeon_device *rdev, int ring); |
393 | int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); |
394 | int radeon_fence_wait_any(struct radeon_device *rdev, |
395 | struct radeon_fence **fences, |
396 | bool intr); |
397 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
398 | void radeon_fence_unref(struct radeon_fence **fence); |
399 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
400 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
401 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); |
402 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, |
403 | struct radeon_fence *b) |
404 | { |
405 | if (!a) { |
406 | return b; |
407 | } |
408 | |
409 | if (!b) { |
410 | return a; |
411 | } |
412 | |
413 | BUG_ON(a->ring != b->ring); |
414 | |
415 | if (a->seq > b->seq) { |
416 | return a; |
417 | } else { |
418 | return b; |
419 | } |
420 | } |
421 | |
422 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
423 | struct radeon_fence *b) |
424 | { |
425 | if (!a) { |
426 | return false; |
427 | } |
428 | |
429 | if (!b) { |
430 | return true; |
431 | } |
432 | |
433 | BUG_ON(a->ring != b->ring); |
434 | |
435 | return a->seq < b->seq; |
436 | } |
437 | |
438 | /* |
439 | * Tiling registers |
440 | */ |
441 | struct radeon_surface_reg { |
442 | struct radeon_bo *bo; |
443 | }; |
444 | |
445 | #define RADEON_GEM_MAX_SURFACES 8 |
446 | |
447 | /* |
448 | * TTM. |
449 | */ |
450 | struct radeon_mman { |
451 | struct ttm_bo_device bdev; |
452 | bool initialized; |
453 | |
454 | #if defined(CONFIG_DEBUG_FS) |
455 | struct dentry *vram; |
456 | struct dentry *gtt; |
457 | #endif |
458 | }; |
459 | |
460 | struct radeon_bo_list { |
461 | struct radeon_bo *robj; |
462 | struct ttm_validate_buffer tv; |
463 | uint64_t gpu_offset; |
464 | unsigned preferred_domains; |
465 | unsigned allowed_domains; |
466 | uint32_t tiling_flags; |
467 | }; |
468 | |
469 | /* bo virtual address in a specific vm */ |
470 | struct radeon_bo_va { |
471 | /* protected by bo being reserved */ |
472 | struct list_head bo_list; |
473 | uint32_t flags; |
474 | struct radeon_fence *last_pt_update; |
475 | unsigned ref_count; |
476 | |
477 | /* protected by vm mutex */ |
478 | struct interval_tree_node it; |
479 | struct list_head vm_status; |
480 | |
481 | /* constant after initialization */ |
482 | struct radeon_vm *vm; |
483 | struct radeon_bo *bo; |
484 | }; |
485 | |
486 | struct radeon_bo { |
487 | /* Protected by gem.mutex */ |
488 | struct list_head list; |
489 | /* Protected by tbo.reserved */ |
490 | u32 initial_domain; |
491 | struct ttm_place placements[4]; |
492 | struct ttm_placement placement; |
493 | struct ttm_buffer_object tbo; |
494 | struct ttm_bo_kmap_obj kmap; |
495 | u32 flags; |
496 | unsigned pin_count; |
497 | void *kptr; |
498 | u32 tiling_flags; |
499 | u32 pitch; |
500 | int surface_reg; |
501 | unsigned prime_shared_count; |
502 | /* list of all virtual address to which this bo |
503 | * is associated to |
504 | */ |
505 | struct list_head va; |
506 | /* Constant after initialization */ |
507 | struct radeon_device *rdev; |
508 | struct drm_gem_object gem_base; |
509 | |
510 | struct ttm_bo_kmap_obj dma_buf_vmap; |
511 | pid_t pid; |
512 | |
513 | struct radeon_mn *mn; |
514 | struct list_head mn_list; |
515 | }; |
516 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
517 | |
518 | int radeon_gem_debugfs_init(struct radeon_device *rdev); |
519 | |
520 | /* sub-allocation manager, it has to be protected by another lock. |
521 | * By conception this is an helper for other part of the driver |
522 | * like the indirect buffer or semaphore, which both have their |
523 | * locking. |
524 | * |
525 | * Principe is simple, we keep a list of sub allocation in offset |
526 | * order (first entry has offset == 0, last entry has the highest |
527 | * offset). |
528 | * |
529 | * When allocating new object we first check if there is room at |
530 | * the end total_size - (last_object_offset + last_object_size) >= |
531 | * alloc_size. If so we allocate new object there. |
532 | * |
533 | * When there is not enough room at the end, we start waiting for |
534 | * each sub object until we reach object_offset+object_size >= |
535 | * alloc_size, this object then become the sub object we return. |
536 | * |
537 | * Alignment can't be bigger than page size. |
538 | * |
539 | * Hole are not considered for allocation to keep things simple. |
540 | * Assumption is that there won't be hole (all object on same |
541 | * alignment). |
542 | */ |
543 | struct radeon_sa_manager { |
544 | wait_queue_head_t wq; |
545 | struct radeon_bo *bo; |
546 | struct list_head *hole; |
547 | struct list_head flist[RADEON_NUM_RINGS]; |
548 | struct list_head olist; |
549 | unsigned size; |
550 | uint64_t gpu_addr; |
551 | void *cpu_ptr; |
552 | uint32_t domain; |
553 | uint32_t align; |
554 | }; |
555 | |
556 | struct radeon_sa_bo; |
557 | |
558 | /* sub-allocation buffer */ |
559 | struct radeon_sa_bo { |
560 | struct list_head olist; |
561 | struct list_head flist; |
562 | struct radeon_sa_manager *manager; |
563 | unsigned soffset; |
564 | unsigned eoffset; |
565 | struct radeon_fence *fence; |
566 | }; |
567 | |
568 | /* |
569 | * GEM objects. |
570 | */ |
571 | struct radeon_gem { |
572 | struct mutex mutex; |
573 | struct list_head objects; |
574 | }; |
575 | |
576 | int radeon_gem_init(struct radeon_device *rdev); |
577 | void radeon_gem_fini(struct radeon_device *rdev); |
578 | int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, |
579 | int alignment, int initial_domain, |
580 | u32 flags, bool kernel, |
581 | struct drm_gem_object **obj); |
582 | |
583 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
584 | struct drm_device *dev, |
585 | struct drm_mode_create_dumb *args); |
586 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
587 | struct drm_device *dev, |
588 | uint32_t handle, uint64_t *offset_p); |
589 | |
590 | /* |
591 | * Semaphores. |
592 | */ |
593 | struct radeon_semaphore { |
594 | struct radeon_sa_bo *sa_bo; |
595 | signed waiters; |
596 | uint64_t gpu_addr; |
597 | }; |
598 | |
599 | int radeon_semaphore_create(struct radeon_device *rdev, |
600 | struct radeon_semaphore **semaphore); |
601 | bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, |
602 | struct radeon_semaphore *semaphore); |
603 | bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, |
604 | struct radeon_semaphore *semaphore); |
605 | void radeon_semaphore_free(struct radeon_device *rdev, |
606 | struct radeon_semaphore **semaphore, |
607 | struct radeon_fence *fence); |
608 | |
609 | /* |
610 | * Synchronization |
611 | */ |
612 | struct radeon_sync { |
613 | struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; |
614 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; |
615 | struct radeon_fence *last_vm_update; |
616 | }; |
617 | |
618 | void radeon_sync_create(struct radeon_sync *sync); |
619 | void radeon_sync_fence(struct radeon_sync *sync, |
620 | struct radeon_fence *fence); |
621 | int radeon_sync_resv(struct radeon_device *rdev, |
622 | struct radeon_sync *sync, |
623 | struct reservation_object *resv, |
624 | bool shared); |
625 | int radeon_sync_rings(struct radeon_device *rdev, |
626 | struct radeon_sync *sync, |
627 | int waiting_ring); |
628 | void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, |
629 | struct radeon_fence *fence); |
630 | |
631 | /* |
632 | * GART structures, functions & helpers |
633 | */ |
634 | struct radeon_mc; |
635 | |
636 | #define RADEON_GPU_PAGE_SIZE 4096 |
637 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
638 | #define RADEON_GPU_PAGE_SHIFT 12 |
639 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
640 | |
641 | #define RADEON_GART_PAGE_DUMMY 0 |
642 | #define RADEON_GART_PAGE_VALID (1 << 0) |
643 | #define RADEON_GART_PAGE_READ (1 << 1) |
644 | #define RADEON_GART_PAGE_WRITE (1 << 2) |
645 | #define RADEON_GART_PAGE_SNOOP (1 << 3) |
646 | |
647 | struct radeon_gart { |
648 | dma_addr_t table_addr; |
649 | struct radeon_bo *robj; |
650 | void *ptr; |
651 | unsigned num_gpu_pages; |
652 | unsigned num_cpu_pages; |
653 | unsigned table_size; |
654 | struct page **pages; |
655 | uint64_t *pages_entry; |
656 | bool ready; |
657 | }; |
658 | |
659 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
660 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
661 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
662 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
663 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
664 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); |
665 | int radeon_gart_init(struct radeon_device *rdev); |
666 | void radeon_gart_fini(struct radeon_device *rdev); |
667 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
668 | int pages); |
669 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
670 | int pages, struct page **pagelist, |
671 | dma_addr_t *dma_addr, uint32_t flags); |
672 | |
673 | |
674 | /* |
675 | * GPU MC structures, functions & helpers |
676 | */ |
677 | struct radeon_mc { |
678 | resource_size_t aper_size; |
679 | resource_size_t aper_base; |
680 | resource_size_t agp_base; |
681 | /* for some chips with <= 32MB we need to lie |
682 | * about vram size near mc fb location */ |
683 | u64 mc_vram_size; |
684 | u64 visible_vram_size; |
685 | u64 gtt_size; |
686 | u64 gtt_start; |
687 | u64 gtt_end; |
688 | u64 vram_start; |
689 | u64 vram_end; |
690 | unsigned vram_width; |
691 | u64 real_vram_size; |
692 | int vram_mtrr; |
693 | bool vram_is_ddr; |
694 | bool igp_sideport_enabled; |
695 | u64 gtt_base_align; |
696 | u64 mc_mask; |
697 | }; |
698 | |
699 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
700 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
701 | |
702 | /* |
703 | * GPU scratch registers structures, functions & helpers |
704 | */ |
705 | struct radeon_scratch { |
706 | unsigned num_reg; |
707 | uint32_t reg_base; |
708 | bool free[32]; |
709 | uint32_t reg[32]; |
710 | }; |
711 | |
712 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
713 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
714 | |
715 | /* |
716 | * GPU doorbell structures, functions & helpers |
717 | */ |
718 | #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ |
719 | |
720 | struct radeon_doorbell { |
721 | /* doorbell mmio */ |
722 | resource_size_t base; |
723 | resource_size_t size; |
724 | u32 __iomem *ptr; |
725 | u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ |
726 | DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); |
727 | }; |
728 | |
729 | int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); |
730 | void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); |
731 | |
732 | /* |
733 | * IRQS. |
734 | */ |
735 | |
736 | struct radeon_flip_work { |
737 | struct work_struct flip_work; |
738 | struct work_struct unpin_work; |
739 | struct radeon_device *rdev; |
740 | int crtc_id; |
741 | u32 target_vblank; |
742 | uint64_t base; |
743 | struct drm_pending_vblank_event *event; |
744 | struct radeon_bo *old_rbo; |
745 | struct dma_fence *fence; |
746 | bool async; |
747 | }; |
748 | |
749 | struct r500_irq_stat_regs { |
750 | u32 disp_int; |
751 | u32 hdmi0_status; |
752 | }; |
753 | |
754 | struct r600_irq_stat_regs { |
755 | u32 disp_int; |
756 | u32 disp_int_cont; |
757 | u32 disp_int_cont2; |
758 | u32 d1grph_int; |
759 | u32 d2grph_int; |
760 | u32 hdmi0_status; |
761 | u32 hdmi1_status; |
762 | }; |
763 | |
764 | struct evergreen_irq_stat_regs { |
765 | u32 disp_int[6]; |
766 | u32 grph_int[6]; |
767 | u32 afmt_status[6]; |
768 | }; |
769 | |
770 | struct cik_irq_stat_regs { |
771 | u32 disp_int; |
772 | u32 disp_int_cont; |
773 | u32 disp_int_cont2; |
774 | u32 disp_int_cont3; |
775 | u32 disp_int_cont4; |
776 | u32 disp_int_cont5; |
777 | u32 disp_int_cont6; |
778 | u32 d1grph_int; |
779 | u32 d2grph_int; |
780 | u32 d3grph_int; |
781 | u32 d4grph_int; |
782 | u32 d5grph_int; |
783 | u32 d6grph_int; |
784 | }; |
785 | |
786 | union radeon_irq_stat_regs { |
787 | struct r500_irq_stat_regs r500; |
788 | struct r600_irq_stat_regs r600; |
789 | struct evergreen_irq_stat_regs evergreen; |
790 | struct cik_irq_stat_regs cik; |
791 | }; |
792 | |
793 | struct radeon_irq { |
794 | bool installed; |
795 | spinlock_t lock; |
796 | atomic_t ring_int[RADEON_NUM_RINGS]; |
797 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
798 | atomic_t pflip[RADEON_MAX_CRTCS]; |
799 | wait_queue_head_t vblank_queue; |
800 | bool hpd[RADEON_MAX_HPD_PINS]; |
801 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
802 | union radeon_irq_stat_regs stat_regs; |
803 | bool dpm_thermal; |
804 | }; |
805 | |
806 | int radeon_irq_kms_init(struct radeon_device *rdev); |
807 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
808 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
809 | bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); |
810 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); |
811 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
812 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); |
813 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
814 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); |
815 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
816 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
817 | |
818 | /* |
819 | * CP & rings. |
820 | */ |
821 | |
822 | struct radeon_ib { |
823 | struct radeon_sa_bo *sa_bo; |
824 | uint32_t length_dw; |
825 | uint64_t gpu_addr; |
826 | uint32_t *ptr; |
827 | int ring; |
828 | struct radeon_fence *fence; |
829 | struct radeon_vm *vm; |
830 | bool is_const_ib; |
831 | struct radeon_sync sync; |
832 | }; |
833 | |
834 | struct radeon_ring { |
835 | struct radeon_bo *ring_obj; |
836 | volatile uint32_t *ring; |
837 | unsigned rptr_offs; |
838 | unsigned rptr_save_reg; |
839 | u64 next_rptr_gpu_addr; |
840 | volatile u32 *next_rptr_cpu_addr; |
841 | unsigned wptr; |
842 | unsigned wptr_old; |
843 | unsigned ring_size; |
844 | unsigned ring_free_dw; |
845 | int count_dw; |
846 | atomic_t last_rptr; |
847 | atomic64_t last_activity; |
848 | uint64_t gpu_addr; |
849 | uint32_t align_mask; |
850 | uint32_t ptr_mask; |
851 | bool ready; |
852 | u32 nop; |
853 | u32 idx; |
854 | u64 last_semaphore_signal_addr; |
855 | u64 last_semaphore_wait_addr; |
856 | /* for CIK queues */ |
857 | u32 me; |
858 | u32 pipe; |
859 | u32 queue; |
860 | struct radeon_bo *mqd_obj; |
861 | u32 doorbell_index; |
862 | unsigned wptr_offs; |
863 | }; |
864 | |
865 | struct radeon_mec { |
866 | struct radeon_bo *hpd_eop_obj; |
867 | u64 hpd_eop_gpu_addr; |
868 | u32 num_pipe; |
869 | u32 num_mec; |
870 | u32 num_queue; |
871 | }; |
872 | |
873 | /* |
874 | * VM |
875 | */ |
876 | |
877 | /* maximum number of VMIDs */ |
878 | #define RADEON_NUM_VM 16 |
879 | |
880 | /* number of entries in page table */ |
881 | #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) |
882 | |
883 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ |
884 | #define RADEON_VM_PTB_ALIGN_SIZE 32768 |
885 | #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) |
886 | #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) |
887 | |
888 | #define R600_PTE_VALID (1 << 0) |
889 | #define R600_PTE_SYSTEM (1 << 1) |
890 | #define R600_PTE_SNOOPED (1 << 2) |
891 | #define R600_PTE_READABLE (1 << 5) |
892 | #define R600_PTE_WRITEABLE (1 << 6) |
893 | |
894 | /* PTE (Page Table Entry) fragment field for different page sizes */ |
895 | #define R600_PTE_FRAG_4KB (0 << 7) |
896 | #define R600_PTE_FRAG_64KB (4 << 7) |
897 | #define R600_PTE_FRAG_256KB (6 << 7) |
898 | |
899 | /* flags needed to be set so we can copy directly from the GART table */ |
900 | #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ |
901 | R600_PTE_SYSTEM | R600_PTE_VALID ) |
902 | |
903 | struct radeon_vm_pt { |
904 | struct radeon_bo *bo; |
905 | uint64_t addr; |
906 | }; |
907 | |
908 | struct radeon_vm_id { |
909 | unsigned id; |
910 | uint64_t pd_gpu_addr; |
911 | /* last flushed PD/PT update */ |
912 | struct radeon_fence *flushed_updates; |
913 | /* last use of vmid */ |
914 | struct radeon_fence *last_id_use; |
915 | }; |
916 | |
917 | struct radeon_vm { |
918 | struct mutex mutex; |
919 | |
920 | struct rb_root_cached va; |
921 | |
922 | /* protecting invalidated and freed */ |
923 | spinlock_t status_lock; |
924 | |
925 | /* BOs moved, but not yet updated in the PT */ |
926 | struct list_head invalidated; |
927 | |
928 | /* BOs freed, but not yet updated in the PT */ |
929 | struct list_head freed; |
930 | |
931 | /* BOs cleared in the PT */ |
932 | struct list_head cleared; |
933 | |
934 | /* contains the page directory */ |
935 | struct radeon_bo *page_directory; |
936 | unsigned max_pde_used; |
937 | |
938 | /* array of page tables, one for each page directory entry */ |
939 | struct radeon_vm_pt *page_tables; |
940 | |
941 | struct radeon_bo_va *ib_bo_va; |
942 | |
943 | /* for id and flush management per ring */ |
944 | struct radeon_vm_id ids[RADEON_NUM_RINGS]; |
945 | }; |
946 | |
947 | struct radeon_vm_manager { |
948 | struct radeon_fence *active[RADEON_NUM_VM]; |
949 | uint32_t max_pfn; |
950 | /* number of VMIDs */ |
951 | unsigned nvm; |
952 | /* vram base address for page table entry */ |
953 | u64 vram_base_offset; |
954 | /* is vm enabled? */ |
955 | bool enabled; |
956 | /* for hw to save the PD addr on suspend/resume */ |
957 | uint32_t saved_table_addr[RADEON_NUM_VM]; |
958 | }; |
959 | |
960 | /* |
961 | * file private structure |
962 | */ |
963 | struct radeon_fpriv { |
964 | struct radeon_vm vm; |
965 | }; |
966 | |
967 | /* |
968 | * R6xx+ IH ring |
969 | */ |
970 | struct r600_ih { |
971 | struct radeon_bo *ring_obj; |
972 | volatile uint32_t *ring; |
973 | unsigned rptr; |
974 | unsigned ring_size; |
975 | uint64_t gpu_addr; |
976 | uint32_t ptr_mask; |
977 | atomic_t lock; |
978 | bool enabled; |
979 | }; |
980 | |
981 | /* |
982 | * RLC stuff |
983 | */ |
984 | #include "clearstate_defs.h" |
985 | |
986 | struct radeon_rlc { |
987 | /* for power gating */ |
988 | struct radeon_bo *save_restore_obj; |
989 | uint64_t save_restore_gpu_addr; |
990 | volatile uint32_t *sr_ptr; |
991 | const u32 *reg_list; |
992 | u32 reg_list_size; |
993 | /* for clear state */ |
994 | struct radeon_bo *clear_state_obj; |
995 | uint64_t clear_state_gpu_addr; |
996 | volatile uint32_t *cs_ptr; |
997 | const struct cs_section_def *cs_data; |
998 | u32 clear_state_size; |
999 | /* for cp tables */ |
1000 | struct radeon_bo *cp_table_obj; |
1001 | uint64_t cp_table_gpu_addr; |
1002 | volatile uint32_t *cp_table_ptr; |
1003 | u32 cp_table_size; |
1004 | }; |
1005 | |
1006 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
1007 | struct radeon_ib *ib, struct radeon_vm *vm, |
1008 | unsigned size); |
1009 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
1010 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
1011 | struct radeon_ib *const_ib, bool hdp_flush); |
1012 | int radeon_ib_pool_init(struct radeon_device *rdev); |
1013 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
1014 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
1015 | /* Ring access between begin & end cannot sleep */ |
1016 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
1017 | struct radeon_ring *ring); |
1018 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
1019 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
1020 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
1021 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, |
1022 | bool hdp_flush); |
1023 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, |
1024 | bool hdp_flush); |
1025 | void radeon_ring_undo(struct radeon_ring *ring); |
1026 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
1027 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
1028 | void radeon_ring_lockup_update(struct radeon_device *rdev, |
1029 | struct radeon_ring *ring); |
1030 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
1031 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
1032 | uint32_t **data); |
1033 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, |
1034 | unsigned size, uint32_t *data); |
1035 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
1036 | unsigned rptr_offs, u32 nop); |
1037 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
1038 | |
1039 | |
1040 | /* r600 async dma */ |
1041 | void r600_dma_stop(struct radeon_device *rdev); |
1042 | int r600_dma_resume(struct radeon_device *rdev); |
1043 | void r600_dma_fini(struct radeon_device *rdev); |
1044 | |
1045 | void cayman_dma_stop(struct radeon_device *rdev); |
1046 | int cayman_dma_resume(struct radeon_device *rdev); |
1047 | void cayman_dma_fini(struct radeon_device *rdev); |
1048 | |
1049 | /* |
1050 | * CS. |
1051 | */ |
1052 | struct radeon_cs_chunk { |
1053 | uint32_t length_dw; |
1054 | uint32_t *kdata; |
1055 | void __user *user_ptr; |
1056 | }; |
1057 | |
1058 | struct radeon_cs_parser { |
1059 | struct device *dev; |
1060 | struct radeon_device *rdev; |
1061 | struct drm_file *filp; |
1062 | /* chunks */ |
1063 | unsigned nchunks; |
1064 | struct radeon_cs_chunk *chunks; |
1065 | uint64_t *chunks_array; |
1066 | /* IB */ |
1067 | unsigned idx; |
1068 | /* relocations */ |
1069 | unsigned nrelocs; |
1070 | struct radeon_bo_list *relocs; |
1071 | struct radeon_bo_list *vm_bos; |
1072 | struct list_head validated; |
1073 | unsigned dma_reloc_idx; |
1074 | /* indices of various chunks */ |
1075 | struct radeon_cs_chunk *chunk_ib; |
1076 | struct radeon_cs_chunk *chunk_relocs; |
1077 | struct radeon_cs_chunk *chunk_flags; |
1078 | struct radeon_cs_chunk *chunk_const_ib; |
1079 | struct radeon_ib ib; |
1080 | struct radeon_ib const_ib; |
1081 | void *track; |
1082 | unsigned family; |
1083 | int parser_error; |
1084 | u32 cs_flags; |
1085 | u32 ring; |
1086 | s32 priority; |
1087 | struct ww_acquire_ctx ticket; |
1088 | }; |
1089 | |
1090 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
1091 | { |
1092 | struct radeon_cs_chunk *ibc = p->chunk_ib; |
1093 | |
1094 | if (ibc->kdata) |
1095 | return ibc->kdata[idx]; |
1096 | return p->ib.ptr[idx]; |
1097 | } |
1098 | |
1099 | |
1100 | struct radeon_cs_packet { |
1101 | unsigned idx; |
1102 | unsigned type; |
1103 | unsigned reg; |
1104 | unsigned opcode; |
1105 | int count; |
1106 | unsigned one_reg_wr; |
1107 | }; |
1108 | |
1109 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
1110 | struct radeon_cs_packet *pkt, |
1111 | unsigned idx, unsigned reg); |
1112 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
1113 | struct radeon_cs_packet *pkt); |
1114 | |
1115 | |
1116 | /* |
1117 | * AGP |
1118 | */ |
1119 | int radeon_agp_init(struct radeon_device *rdev); |
1120 | void radeon_agp_resume(struct radeon_device *rdev); |
1121 | void radeon_agp_suspend(struct radeon_device *rdev); |
1122 | void radeon_agp_fini(struct radeon_device *rdev); |
1123 | |
1124 | |
1125 | /* |
1126 | * Writeback |
1127 | */ |
1128 | struct radeon_wb { |
1129 | struct radeon_bo *wb_obj; |
1130 | volatile uint32_t *wb; |
1131 | uint64_t gpu_addr; |
1132 | bool enabled; |
1133 | bool use_event; |
1134 | }; |
1135 | |
1136 | #define RADEON_WB_SCRATCH_OFFSET 0 |
1137 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
1138 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
1139 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
1140 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 |
1141 | #define R600_WB_DMA_RPTR_OFFSET 1792 |
1142 | #define R600_WB_IH_WPTR_OFFSET 2048 |
1143 | #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 |
1144 | #define R600_WB_EVENT_OFFSET 3072 |
1145 | #define CIK_WB_CP1_WPTR_OFFSET 3328 |
1146 | #define CIK_WB_CP2_WPTR_OFFSET 3584 |
1147 | #define R600_WB_DMA_RING_TEST_OFFSET 3588 |
1148 | #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 |
1149 | |
1150 | /** |
1151 | * struct radeon_pm - power management datas |
1152 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
1153 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
1154 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
1155 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
1156 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
1157 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
1158 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
1159 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
1160 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
1161 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
1162 | * @needed_bandwidth: current bandwidth needs |
1163 | * |
1164 | * It keeps track of various data needed to take powermanagement decision. |
1165 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
1166 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
1167 | * (type of memory, bus size, efficiency, ...) |
1168 | */ |
1169 | |
1170 | enum radeon_pm_method { |
1171 | PM_METHOD_PROFILE, |
1172 | PM_METHOD_DYNPM, |
1173 | PM_METHOD_DPM, |
1174 | }; |
1175 | |
1176 | enum radeon_dynpm_state { |
1177 | DYNPM_STATE_DISABLED, |
1178 | DYNPM_STATE_MINIMUM, |
1179 | DYNPM_STATE_PAUSED, |
1180 | DYNPM_STATE_ACTIVE, |
1181 | DYNPM_STATE_SUSPENDED, |
1182 | }; |
1183 | enum radeon_dynpm_action { |
1184 | DYNPM_ACTION_NONE, |
1185 | DYNPM_ACTION_MINIMUM, |
1186 | DYNPM_ACTION_DOWNCLOCK, |
1187 | DYNPM_ACTION_UPCLOCK, |
1188 | DYNPM_ACTION_DEFAULT |
1189 | }; |
1190 | |
1191 | enum radeon_voltage_type { |
1192 | VOLTAGE_NONE = 0, |
1193 | VOLTAGE_GPIO, |
1194 | VOLTAGE_VDDC, |
1195 | VOLTAGE_SW |
1196 | }; |
1197 | |
1198 | enum radeon_pm_state_type { |
1199 | /* not used for dpm */ |
1200 | POWER_STATE_TYPE_DEFAULT, |
1201 | POWER_STATE_TYPE_POWERSAVE, |
1202 | /* user selectable states */ |
1203 | POWER_STATE_TYPE_BATTERY, |
1204 | POWER_STATE_TYPE_BALANCED, |
1205 | POWER_STATE_TYPE_PERFORMANCE, |
1206 | /* internal states */ |
1207 | POWER_STATE_TYPE_INTERNAL_UVD, |
1208 | POWER_STATE_TYPE_INTERNAL_UVD_SD, |
1209 | POWER_STATE_TYPE_INTERNAL_UVD_HD, |
1210 | POWER_STATE_TYPE_INTERNAL_UVD_HD2, |
1211 | POWER_STATE_TYPE_INTERNAL_UVD_MVC, |
1212 | POWER_STATE_TYPE_INTERNAL_BOOT, |
1213 | POWER_STATE_TYPE_INTERNAL_THERMAL, |
1214 | POWER_STATE_TYPE_INTERNAL_ACPI, |
1215 | POWER_STATE_TYPE_INTERNAL_ULV, |
1216 | POWER_STATE_TYPE_INTERNAL_3DPERF, |
1217 | }; |
1218 | |
1219 | enum radeon_pm_profile_type { |
1220 | PM_PROFILE_DEFAULT, |
1221 | PM_PROFILE_AUTO, |
1222 | PM_PROFILE_LOW, |
1223 | PM_PROFILE_MID, |
1224 | PM_PROFILE_HIGH, |
1225 | }; |
1226 | |
1227 | #define PM_PROFILE_DEFAULT_IDX 0 |
1228 | #define PM_PROFILE_LOW_SH_IDX 1 |
1229 | #define PM_PROFILE_MID_SH_IDX 2 |
1230 | #define PM_PROFILE_HIGH_SH_IDX 3 |
1231 | #define PM_PROFILE_LOW_MH_IDX 4 |
1232 | #define PM_PROFILE_MID_MH_IDX 5 |
1233 | #define PM_PROFILE_HIGH_MH_IDX 6 |
1234 | #define PM_PROFILE_MAX 7 |
1235 | |
1236 | struct radeon_pm_profile { |
1237 | int dpms_off_ps_idx; |
1238 | int dpms_on_ps_idx; |
1239 | int dpms_off_cm_idx; |
1240 | int dpms_on_cm_idx; |
1241 | }; |
1242 | |
1243 | enum radeon_int_thermal_type { |
1244 | THERMAL_TYPE_NONE, |
1245 | THERMAL_TYPE_EXTERNAL, |
1246 | THERMAL_TYPE_EXTERNAL_GPIO, |
1247 | THERMAL_TYPE_RV6XX, |
1248 | THERMAL_TYPE_RV770, |
1249 | THERMAL_TYPE_ADT7473_WITH_INTERNAL, |
1250 | THERMAL_TYPE_EVERGREEN, |
1251 | THERMAL_TYPE_SUMO, |
1252 | THERMAL_TYPE_NI, |
1253 | THERMAL_TYPE_SI, |
1254 | THERMAL_TYPE_EMC2103_WITH_INTERNAL, |
1255 | THERMAL_TYPE_CI, |
1256 | THERMAL_TYPE_KV, |
1257 | }; |
1258 | |
1259 | struct radeon_voltage { |
1260 | enum radeon_voltage_type type; |
1261 | /* gpio voltage */ |
1262 | struct radeon_gpio_rec gpio; |
1263 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
1264 | bool active_high; /* voltage drop is active when bit is high */ |
1265 | /* VDDC voltage */ |
1266 | u8 vddc_id; /* index into vddc voltage table */ |
1267 | u8 vddci_id; /* index into vddci voltage table */ |
1268 | bool vddci_enabled; |
1269 | /* r6xx+ sw */ |
1270 | u16 voltage; |
1271 | /* evergreen+ vddci */ |
1272 | u16 vddci; |
1273 | }; |
1274 | |
1275 | /* clock mode flags */ |
1276 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) |
1277 | |
1278 | struct radeon_pm_clock_info { |
1279 | /* memory clock */ |
1280 | u32 mclk; |
1281 | /* engine clock */ |
1282 | u32 sclk; |
1283 | /* voltage info */ |
1284 | struct radeon_voltage voltage; |
1285 | /* standardized clock flags */ |
1286 | u32 flags; |
1287 | }; |
1288 | |
1289 | /* state flags */ |
1290 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
1291 | |
1292 | struct radeon_power_state { |
1293 | enum radeon_pm_state_type type; |
1294 | struct radeon_pm_clock_info *clock_info; |
1295 | /* number of valid clock modes in this power state */ |
1296 | int num_clock_modes; |
1297 | struct radeon_pm_clock_info *default_clock_mode; |
1298 | /* standardized state flags */ |
1299 | u32 flags; |
1300 | u32 misc; /* vbios specific flags */ |
1301 | u32 misc2; /* vbios specific flags */ |
1302 | int pcie_lanes; /* pcie lanes */ |
1303 | }; |
1304 | |
1305 | /* |
1306 | * Some modes are overclocked by very low value, accept them |
1307 | */ |
1308 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
1309 | |
1310 | enum radeon_dpm_auto_throttle_src { |
1311 | RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, |
1312 | RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL |
1313 | }; |
1314 | |
1315 | enum radeon_dpm_event_src { |
1316 | RADEON_DPM_EVENT_SRC_ANALOG = 0, |
1317 | RADEON_DPM_EVENT_SRC_EXTERNAL = 1, |
1318 | RADEON_DPM_EVENT_SRC_DIGITAL = 2, |
1319 | RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, |
1320 | RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 |
1321 | }; |
1322 | |
1323 | #define RADEON_MAX_VCE_LEVELS 6 |
1324 | |
1325 | enum radeon_vce_level { |
1326 | RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ |
1327 | RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ |
1328 | RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ |
1329 | RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ |
1330 | RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ |
1331 | RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ |
1332 | }; |
1333 | |
1334 | struct radeon_ps { |
1335 | u32 caps; /* vbios flags */ |
1336 | u32 class; /* vbios flags */ |
1337 | u32 class2; /* vbios flags */ |
1338 | /* UVD clocks */ |
1339 | u32 vclk; |
1340 | u32 dclk; |
1341 | /* VCE clocks */ |
1342 | u32 evclk; |
1343 | u32 ecclk; |
1344 | bool vce_active; |
1345 | enum radeon_vce_level vce_level; |
1346 | /* asic priv */ |
1347 | void *ps_priv; |
1348 | }; |
1349 | |
1350 | struct radeon_dpm_thermal { |
1351 | /* thermal interrupt work */ |
1352 | struct work_struct work; |
1353 | /* low temperature threshold */ |
1354 | int min_temp; |
1355 | /* high temperature threshold */ |
1356 | int max_temp; |
1357 | /* was interrupt low to high or high to low */ |
1358 | bool high_to_low; |
1359 | }; |
1360 | |
1361 | enum radeon_clk_action |
1362 | { |
1363 | RADEON_SCLK_UP = 1, |
1364 | RADEON_SCLK_DOWN |
1365 | }; |
1366 | |
1367 | struct radeon_blacklist_clocks |
1368 | { |
1369 | u32 sclk; |
1370 | u32 mclk; |
1371 | enum radeon_clk_action action; |
1372 | }; |
1373 | |
1374 | struct radeon_clock_and_voltage_limits { |
1375 | u32 sclk; |
1376 | u32 mclk; |
1377 | u16 vddc; |
1378 | u16 vddci; |
1379 | }; |
1380 | |
1381 | struct radeon_clock_array { |
1382 | u32 count; |
1383 | u32 *values; |
1384 | }; |
1385 | |
1386 | struct radeon_clock_voltage_dependency_entry { |
1387 | u32 clk; |
1388 | u16 v; |
1389 | }; |
1390 | |
1391 | struct radeon_clock_voltage_dependency_table { |
1392 | u32 count; |
1393 | struct radeon_clock_voltage_dependency_entry *entries; |
1394 | }; |
1395 | |
1396 | union radeon_cac_leakage_entry { |
1397 | struct { |
1398 | u16 vddc; |
1399 | u32 leakage; |
1400 | }; |
1401 | struct { |
1402 | u16 vddc1; |
1403 | u16 vddc2; |
1404 | u16 vddc3; |
1405 | }; |
1406 | }; |
1407 | |
1408 | struct radeon_cac_leakage_table { |
1409 | u32 count; |
1410 | union radeon_cac_leakage_entry *entries; |
1411 | }; |
1412 | |
1413 | struct radeon_phase_shedding_limits_entry { |
1414 | u16 voltage; |
1415 | u32 sclk; |
1416 | u32 mclk; |
1417 | }; |
1418 | |
1419 | struct radeon_phase_shedding_limits_table { |
1420 | u32 count; |
1421 | struct radeon_phase_shedding_limits_entry *entries; |
1422 | }; |
1423 | |
1424 | struct radeon_uvd_clock_voltage_dependency_entry { |
1425 | u32 vclk; |
1426 | u32 dclk; |
1427 | u16 v; |
1428 | }; |
1429 | |
1430 | struct radeon_uvd_clock_voltage_dependency_table { |
1431 | u8 count; |
1432 | struct radeon_uvd_clock_voltage_dependency_entry *entries; |
1433 | }; |
1434 | |
1435 | struct radeon_vce_clock_voltage_dependency_entry { |
1436 | u32 ecclk; |
1437 | u32 evclk; |
1438 | u16 v; |
1439 | }; |
1440 | |
1441 | struct radeon_vce_clock_voltage_dependency_table { |
1442 | u8 count; |
1443 | struct radeon_vce_clock_voltage_dependency_entry *entries; |
1444 | }; |
1445 | |
1446 | struct radeon_ppm_table { |
1447 | u8 ppm_design; |
1448 | u16 cpu_core_number; |
1449 | u32 platform_tdp; |
1450 | u32 small_ac_platform_tdp; |
1451 | u32 platform_tdc; |
1452 | u32 small_ac_platform_tdc; |
1453 | u32 apu_tdp; |
1454 | u32 dgpu_tdp; |
1455 | u32 dgpu_ulv_power; |
1456 | u32 tj_max; |
1457 | }; |
1458 | |
1459 | struct radeon_cac_tdp_table { |
1460 | u16 tdp; |
1461 | u16 configurable_tdp; |
1462 | u16 tdc; |
1463 | u16 battery_power_limit; |
1464 | u16 small_power_limit; |
1465 | u16 low_cac_leakage; |
1466 | u16 high_cac_leakage; |
1467 | u16 maximum_power_delivery_limit; |
1468 | }; |
1469 | |
1470 | struct radeon_dpm_dynamic_state { |
1471 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; |
1472 | struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; |
1473 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; |
1474 | struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; |
1475 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; |
1476 | struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; |
1477 | struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; |
1478 | struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; |
1479 | struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; |
1480 | struct radeon_clock_array valid_sclk_values; |
1481 | struct radeon_clock_array valid_mclk_values; |
1482 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; |
1483 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; |
1484 | u32 mclk_sclk_ratio; |
1485 | u32 sclk_mclk_delta; |
1486 | u16 vddc_vddci_delta; |
1487 | u16 min_vddc_for_pcie_gen2; |
1488 | struct radeon_cac_leakage_table cac_leakage_table; |
1489 | struct radeon_phase_shedding_limits_table phase_shedding_limits_table; |
1490 | struct radeon_ppm_table *ppm_table; |
1491 | struct radeon_cac_tdp_table *cac_tdp_table; |
1492 | }; |
1493 | |
1494 | struct radeon_dpm_fan { |
1495 | u16 t_min; |
1496 | u16 t_med; |
1497 | u16 t_high; |
1498 | u16 pwm_min; |
1499 | u16 pwm_med; |
1500 | u16 pwm_high; |
1501 | u8 t_hyst; |
1502 | u32 cycle_delay; |
1503 | u16 t_max; |
1504 | u8 control_mode; |
1505 | u16 default_max_fan_pwm; |
1506 | u16 default_fan_output_sensitivity; |
1507 | u16 fan_output_sensitivity; |
1508 | bool ucode_fan_control; |
1509 | }; |
1510 | |
1511 | enum radeon_pcie_gen { |
1512 | RADEON_PCIE_GEN1 = 0, |
1513 | RADEON_PCIE_GEN2 = 1, |
1514 | RADEON_PCIE_GEN3 = 2, |
1515 | RADEON_PCIE_GEN_INVALID = 0xffff |
1516 | }; |
1517 | |
1518 | enum radeon_dpm_forced_level { |
1519 | RADEON_DPM_FORCED_LEVEL_AUTO = 0, |
1520 | RADEON_DPM_FORCED_LEVEL_LOW = 1, |
1521 | RADEON_DPM_FORCED_LEVEL_HIGH = 2, |
1522 | }; |
1523 | |
1524 | struct radeon_vce_state { |
1525 | /* vce clocks */ |
1526 | u32 evclk; |
1527 | u32 ecclk; |
1528 | /* gpu clocks */ |
1529 | u32 sclk; |
1530 | u32 mclk; |
1531 | u8 clk_idx; |
1532 | u8 pstate; |
1533 | }; |
1534 | |
1535 | struct radeon_dpm { |
1536 | struct radeon_ps *ps; |
1537 | /* number of valid power states */ |
1538 | int num_ps; |
1539 | /* current power state that is active */ |
1540 | struct radeon_ps *current_ps; |
1541 | /* requested power state */ |
1542 | struct radeon_ps *requested_ps; |
1543 | /* boot up power state */ |
1544 | struct radeon_ps *boot_ps; |
1545 | /* default uvd power state */ |
1546 | struct radeon_ps *uvd_ps; |
1547 | /* vce requirements */ |
1548 | struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; |
1549 | enum radeon_vce_level vce_level; |
1550 | enum radeon_pm_state_type state; |
1551 | enum radeon_pm_state_type user_state; |
1552 | u32 platform_caps; |
1553 | u32 voltage_response_time; |
1554 | u32 backbias_response_time; |
1555 | void *priv; |
1556 | u32 new_active_crtcs; |
1557 | int new_active_crtc_count; |
1558 | u32 current_active_crtcs; |
1559 | int current_active_crtc_count; |
1560 | bool single_display; |
1561 | struct radeon_dpm_dynamic_state dyn_state; |
1562 | struct radeon_dpm_fan fan; |
1563 | u32 tdp_limit; |
1564 | u32 near_tdp_limit; |
1565 | u32 near_tdp_limit_adjusted; |
1566 | u32 sq_ramping_threshold; |
1567 | u32 cac_leakage; |
1568 | u16 tdp_od_limit; |
1569 | u32 tdp_adjustment; |
1570 | u16 load_line_slope; |
1571 | bool power_control; |
1572 | bool ac_power; |
1573 | /* special states active */ |
1574 | bool thermal_active; |
1575 | bool uvd_active; |
1576 | bool vce_active; |
1577 | /* thermal handling */ |
1578 | struct radeon_dpm_thermal thermal; |
1579 | /* forced levels */ |
1580 | enum radeon_dpm_forced_level forced_level; |
1581 | /* track UVD streams */ |
1582 | unsigned sd; |
1583 | unsigned hd; |
1584 | }; |
1585 | |
1586 | void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); |
1587 | void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); |
1588 | |
1589 | struct radeon_pm { |
1590 | struct mutex mutex; |
1591 | /* write locked while reprogramming mclk */ |
1592 | struct rw_semaphore mclk_lock; |
1593 | u32 active_crtcs; |
1594 | int active_crtc_count; |
1595 | int req_vblank; |
1596 | bool vblank_sync; |
1597 | fixed20_12 max_bandwidth; |
1598 | fixed20_12 igp_sideport_mclk; |
1599 | fixed20_12 igp_system_mclk; |
1600 | fixed20_12 igp_ht_link_clk; |
1601 | fixed20_12 igp_ht_link_width; |
1602 | fixed20_12 k8_bandwidth; |
1603 | fixed20_12 sideport_bandwidth; |
1604 | fixed20_12 ht_bandwidth; |
1605 | fixed20_12 core_bandwidth; |
1606 | fixed20_12 sclk; |
1607 | fixed20_12 mclk; |
1608 | fixed20_12 needed_bandwidth; |
1609 | struct radeon_power_state *power_state; |
1610 | /* number of valid power states */ |
1611 | int num_power_states; |
1612 | int current_power_state_index; |
1613 | int current_clock_mode_index; |
1614 | int requested_power_state_index; |
1615 | int requested_clock_mode_index; |
1616 | int default_power_state_index; |
1617 | u32 current_sclk; |
1618 | u32 current_mclk; |
1619 | u16 current_vddc; |
1620 | u16 current_vddci; |
1621 | u32 default_sclk; |
1622 | u32 default_mclk; |
1623 | u16 default_vddc; |
1624 | u16 default_vddci; |
1625 | struct radeon_i2c_chan *i2c_bus; |
1626 | /* selected pm method */ |
1627 | enum radeon_pm_method pm_method; |
1628 | /* dynpm power management */ |
1629 | struct delayed_work dynpm_idle_work; |
1630 | enum radeon_dynpm_state dynpm_state; |
1631 | enum radeon_dynpm_action dynpm_planned_action; |
1632 | unsigned long dynpm_action_timeout; |
1633 | bool dynpm_can_upclock; |
1634 | bool dynpm_can_downclock; |
1635 | /* profile-based power management */ |
1636 | enum radeon_pm_profile_type profile; |
1637 | int profile_index; |
1638 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; |
1639 | /* internal thermal controller on rv6xx+ */ |
1640 | enum radeon_int_thermal_type int_thermal_type; |
1641 | struct device *int_hwmon_dev; |
1642 | /* fan control parameters */ |
1643 | bool no_fan; |
1644 | u8 fan_pulses_per_revolution; |
1645 | u8 fan_min_rpm; |
1646 | u8 fan_max_rpm; |
1647 | /* dpm */ |
1648 | bool dpm_enabled; |
1649 | bool sysfs_initialized; |
1650 | struct radeon_dpm dpm; |
1651 | }; |
1652 | |
1653 | #define RADEON_PCIE_SPEED_25 1 |
1654 | #define RADEON_PCIE_SPEED_50 2 |
1655 | #define RADEON_PCIE_SPEED_80 4 |
1656 | |
1657 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
1658 | enum radeon_pm_state_type ps_type, |
1659 | int instance); |
1660 | /* |
1661 | * UVD |
1662 | */ |
1663 | #define RADEON_DEFAULT_UVD_HANDLES 10 |
1664 | #define RADEON_MAX_UVD_HANDLES 30 |
1665 | #define RADEON_UVD_STACK_SIZE (200*1024) |
1666 | #define RADEON_UVD_HEAP_SIZE (256*1024) |
1667 | #define RADEON_UVD_SESSION_SIZE (50*1024) |
1668 | |
1669 | struct radeon_uvd { |
1670 | bool ; |
1671 | struct radeon_bo *vcpu_bo; |
1672 | void *cpu_addr; |
1673 | uint64_t gpu_addr; |
1674 | unsigned max_handles; |
1675 | atomic_t handles[RADEON_MAX_UVD_HANDLES]; |
1676 | struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; |
1677 | unsigned img_size[RADEON_MAX_UVD_HANDLES]; |
1678 | struct delayed_work idle_work; |
1679 | }; |
1680 | |
1681 | int radeon_uvd_init(struct radeon_device *rdev); |
1682 | void radeon_uvd_fini(struct radeon_device *rdev); |
1683 | int radeon_uvd_suspend(struct radeon_device *rdev); |
1684 | int radeon_uvd_resume(struct radeon_device *rdev); |
1685 | int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, |
1686 | uint32_t handle, struct radeon_fence **fence); |
1687 | int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, |
1688 | uint32_t handle, struct radeon_fence **fence); |
1689 | void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, |
1690 | uint32_t allowed_domains); |
1691 | void radeon_uvd_free_handles(struct radeon_device *rdev, |
1692 | struct drm_file *filp); |
1693 | int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); |
1694 | void radeon_uvd_note_usage(struct radeon_device *rdev); |
1695 | int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, |
1696 | unsigned vclk, unsigned dclk, |
1697 | unsigned vco_min, unsigned vco_max, |
1698 | unsigned fb_factor, unsigned fb_mask, |
1699 | unsigned pd_min, unsigned pd_max, |
1700 | unsigned pd_even, |
1701 | unsigned *optimal_fb_div, |
1702 | unsigned *optimal_vclk_div, |
1703 | unsigned *optimal_dclk_div); |
1704 | int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, |
1705 | unsigned cg_upll_func_cntl); |
1706 | |
1707 | /* |
1708 | * VCE |
1709 | */ |
1710 | #define RADEON_MAX_VCE_HANDLES 16 |
1711 | |
1712 | struct radeon_vce { |
1713 | struct radeon_bo *vcpu_bo; |
1714 | uint64_t gpu_addr; |
1715 | unsigned fw_version; |
1716 | unsigned fb_version; |
1717 | atomic_t handles[RADEON_MAX_VCE_HANDLES]; |
1718 | struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; |
1719 | unsigned img_size[RADEON_MAX_VCE_HANDLES]; |
1720 | struct delayed_work idle_work; |
1721 | uint32_t keyselect; |
1722 | }; |
1723 | |
1724 | int radeon_vce_init(struct radeon_device *rdev); |
1725 | void radeon_vce_fini(struct radeon_device *rdev); |
1726 | int radeon_vce_suspend(struct radeon_device *rdev); |
1727 | int radeon_vce_resume(struct radeon_device *rdev); |
1728 | int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, |
1729 | uint32_t handle, struct radeon_fence **fence); |
1730 | int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, |
1731 | uint32_t handle, struct radeon_fence **fence); |
1732 | void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); |
1733 | void radeon_vce_note_usage(struct radeon_device *rdev); |
1734 | int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); |
1735 | int radeon_vce_cs_parse(struct radeon_cs_parser *p); |
1736 | bool radeon_vce_semaphore_emit(struct radeon_device *rdev, |
1737 | struct radeon_ring *ring, |
1738 | struct radeon_semaphore *semaphore, |
1739 | bool emit_wait); |
1740 | void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
1741 | void radeon_vce_fence_emit(struct radeon_device *rdev, |
1742 | struct radeon_fence *fence); |
1743 | int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); |
1744 | int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
1745 | |
1746 | struct r600_audio_pin { |
1747 | int channels; |
1748 | int rate; |
1749 | int bits_per_sample; |
1750 | u8 status_bits; |
1751 | u8 category_code; |
1752 | u32 offset; |
1753 | bool connected; |
1754 | u32 id; |
1755 | }; |
1756 | |
1757 | struct r600_audio { |
1758 | bool enabled; |
1759 | struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; |
1760 | int num_pins; |
1761 | struct radeon_audio_funcs *hdmi_funcs; |
1762 | struct radeon_audio_funcs *dp_funcs; |
1763 | struct radeon_audio_basic_funcs *funcs; |
1764 | }; |
1765 | |
1766 | /* |
1767 | * Benchmarking |
1768 | */ |
1769 | void radeon_benchmark(struct radeon_device *rdev, int test_number); |
1770 | |
1771 | |
1772 | /* |
1773 | * Testing |
1774 | */ |
1775 | void radeon_test_moves(struct radeon_device *rdev); |
1776 | void radeon_test_ring_sync(struct radeon_device *rdev, |
1777 | struct radeon_ring *cpA, |
1778 | struct radeon_ring *cpB); |
1779 | void radeon_test_syncing(struct radeon_device *rdev); |
1780 | |
1781 | /* |
1782 | * MMU Notifier |
1783 | */ |
1784 | #if defined(CONFIG_MMU_NOTIFIER) |
1785 | int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); |
1786 | void radeon_mn_unregister(struct radeon_bo *bo); |
1787 | #else |
1788 | static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) |
1789 | { |
1790 | return -ENODEV; |
1791 | } |
1792 | static inline void radeon_mn_unregister(struct radeon_bo *bo) {} |
1793 | #endif |
1794 | |
1795 | /* |
1796 | * Debugfs |
1797 | */ |
1798 | struct radeon_debugfs { |
1799 | struct drm_info_list *files; |
1800 | unsigned num_files; |
1801 | }; |
1802 | |
1803 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
1804 | struct drm_info_list *files, |
1805 | unsigned nfiles); |
1806 | int radeon_debugfs_fence_init(struct radeon_device *rdev); |
1807 | |
1808 | /* |
1809 | * ASIC ring specific functions. |
1810 | */ |
1811 | struct radeon_asic_ring { |
1812 | /* ring read/write ptr handling */ |
1813 | u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
1814 | u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
1815 | void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); |
1816 | |
1817 | /* validating and patching of IBs */ |
1818 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
1819 | int (*cs_parse)(struct radeon_cs_parser *p); |
1820 | |
1821 | /* command emmit functions */ |
1822 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
1823 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); |
1824 | void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); |
1825 | bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
1826 | struct radeon_semaphore *semaphore, bool emit_wait); |
1827 | void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, |
1828 | unsigned vm_id, uint64_t pd_addr); |
1829 | |
1830 | /* testing functions */ |
1831 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
1832 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
1833 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); |
1834 | |
1835 | /* deprecated */ |
1836 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); |
1837 | }; |
1838 | |
1839 | /* |
1840 | * ASIC specific functions. |
1841 | */ |
1842 | struct radeon_asic { |
1843 | int (*init)(struct radeon_device *rdev); |
1844 | void (*fini)(struct radeon_device *rdev); |
1845 | int (*resume)(struct radeon_device *rdev); |
1846 | int (*suspend)(struct radeon_device *rdev); |
1847 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
1848 | int (*asic_reset)(struct radeon_device *rdev, bool hard); |
1849 | /* Flush the HDP cache via MMIO */ |
1850 | void (*mmio_hdp_flush)(struct radeon_device *rdev); |
1851 | /* check if 3D engine is idle */ |
1852 | bool (*gui_idle)(struct radeon_device *rdev); |
1853 | /* wait for mc_idle */ |
1854 | int (*mc_wait_for_idle)(struct radeon_device *rdev); |
1855 | /* get the reference clock */ |
1856 | u32 (*get_xclk)(struct radeon_device *rdev); |
1857 | /* get the gpu clock counter */ |
1858 | uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); |
1859 | /* get register for info ioctl */ |
1860 | int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); |
1861 | /* gart */ |
1862 | struct { |
1863 | void (*tlb_flush)(struct radeon_device *rdev); |
1864 | uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); |
1865 | void (*set_page)(struct radeon_device *rdev, unsigned i, |
1866 | uint64_t entry); |
1867 | } gart; |
1868 | struct { |
1869 | int (*init)(struct radeon_device *rdev); |
1870 | void (*fini)(struct radeon_device *rdev); |
1871 | void (*copy_pages)(struct radeon_device *rdev, |
1872 | struct radeon_ib *ib, |
1873 | uint64_t pe, uint64_t src, |
1874 | unsigned count); |
1875 | void (*write_pages)(struct radeon_device *rdev, |
1876 | struct radeon_ib *ib, |
1877 | uint64_t pe, |
1878 | uint64_t addr, unsigned count, |
1879 | uint32_t incr, uint32_t flags); |
1880 | void (*set_pages)(struct radeon_device *rdev, |
1881 | struct radeon_ib *ib, |
1882 | uint64_t pe, |
1883 | uint64_t addr, unsigned count, |
1884 | uint32_t incr, uint32_t flags); |
1885 | void (*pad_ib)(struct radeon_ib *ib); |
1886 | } vm; |
1887 | /* ring specific callbacks */ |
1888 | const struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; |
1889 | /* irqs */ |
1890 | struct { |
1891 | int (*set)(struct radeon_device *rdev); |
1892 | int (*process)(struct radeon_device *rdev); |
1893 | } irq; |
1894 | /* displays */ |
1895 | struct { |
1896 | /* display watermarks */ |
1897 | void (*bandwidth_update)(struct radeon_device *rdev); |
1898 | /* get frame count */ |
1899 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
1900 | /* wait for vblank */ |
1901 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); |
1902 | /* set backlight level */ |
1903 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); |
1904 | /* get backlight level */ |
1905 | u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); |
1906 | /* audio callbacks */ |
1907 | void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); |
1908 | void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); |
1909 | } display; |
1910 | /* copy functions for bo handling */ |
1911 | struct { |
1912 | struct radeon_fence *(*blit)(struct radeon_device *rdev, |
1913 | uint64_t src_offset, |
1914 | uint64_t dst_offset, |
1915 | unsigned num_gpu_pages, |
1916 | struct reservation_object *resv); |
1917 | u32 blit_ring_index; |
1918 | struct radeon_fence *(*dma)(struct radeon_device *rdev, |
1919 | uint64_t src_offset, |
1920 | uint64_t dst_offset, |
1921 | unsigned num_gpu_pages, |
1922 | struct reservation_object *resv); |
1923 | u32 dma_ring_index; |
1924 | /* method used for bo copy */ |
1925 | struct radeon_fence *(*copy)(struct radeon_device *rdev, |
1926 | uint64_t src_offset, |
1927 | uint64_t dst_offset, |
1928 | unsigned num_gpu_pages, |
1929 | struct reservation_object *resv); |
1930 | /* ring used for bo copies */ |
1931 | u32 copy_ring_index; |
1932 | } copy; |
1933 | /* surfaces */ |
1934 | struct { |
1935 | int (*set_reg)(struct radeon_device *rdev, int reg, |
1936 | uint32_t tiling_flags, uint32_t pitch, |
1937 | uint32_t offset, uint32_t obj_size); |
1938 | void (*clear_reg)(struct radeon_device *rdev, int reg); |
1939 | } surface; |
1940 | /* hotplug detect */ |
1941 | struct { |
1942 | void (*init)(struct radeon_device *rdev); |
1943 | void (*fini)(struct radeon_device *rdev); |
1944 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
1945 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
1946 | } hpd; |
1947 | /* static power management */ |
1948 | struct { |
1949 | void (*misc)(struct radeon_device *rdev); |
1950 | void (*prepare)(struct radeon_device *rdev); |
1951 | void (*finish)(struct radeon_device *rdev); |
1952 | void (*init_profile)(struct radeon_device *rdev); |
1953 | void (*get_dynpm_state)(struct radeon_device *rdev); |
1954 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1955 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
1956 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
1957 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
1958 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
1959 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
1960 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
1961 | int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); |
1962 | int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); |
1963 | int (*get_temperature)(struct radeon_device *rdev); |
1964 | } pm; |
1965 | /* dynamic power management */ |
1966 | struct { |
1967 | int (*init)(struct radeon_device *rdev); |
1968 | void (*setup_asic)(struct radeon_device *rdev); |
1969 | int (*enable)(struct radeon_device *rdev); |
1970 | int (*late_enable)(struct radeon_device *rdev); |
1971 | void (*disable)(struct radeon_device *rdev); |
1972 | int (*pre_set_power_state)(struct radeon_device *rdev); |
1973 | int (*set_power_state)(struct radeon_device *rdev); |
1974 | void (*post_set_power_state)(struct radeon_device *rdev); |
1975 | void (*display_configuration_changed)(struct radeon_device *rdev); |
1976 | void (*fini)(struct radeon_device *rdev); |
1977 | u32 (*get_sclk)(struct radeon_device *rdev, bool low); |
1978 | u32 (*get_mclk)(struct radeon_device *rdev, bool low); |
1979 | void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); |
1980 | void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); |
1981 | int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); |
1982 | bool (*vblank_too_short)(struct radeon_device *rdev); |
1983 | void (*powergate_uvd)(struct radeon_device *rdev, bool gate); |
1984 | void (*enable_bapm)(struct radeon_device *rdev, bool enable); |
1985 | void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); |
1986 | u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); |
1987 | int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); |
1988 | int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); |
1989 | u32 (*get_current_sclk)(struct radeon_device *rdev); |
1990 | u32 (*get_current_mclk)(struct radeon_device *rdev); |
1991 | } dpm; |
1992 | /* pageflipping */ |
1993 | struct { |
1994 | void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async); |
1995 | bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); |
1996 | } pflip; |
1997 | }; |
1998 | |
1999 | /* |
2000 | * Asic structures |
2001 | */ |
2002 | struct r100_asic { |
2003 | const unsigned *reg_safe_bm; |
2004 | unsigned reg_safe_bm_size; |
2005 | u32 hdp_cntl; |
2006 | }; |
2007 | |
2008 | struct r300_asic { |
2009 | const unsigned *reg_safe_bm; |
2010 | unsigned reg_safe_bm_size; |
2011 | u32 resync_scratch; |
2012 | u32 hdp_cntl; |
2013 | }; |
2014 | |
2015 | struct r600_asic { |
2016 | unsigned max_pipes; |
2017 | unsigned max_tile_pipes; |
2018 | unsigned max_simds; |
2019 | unsigned max_backends; |
2020 | unsigned max_gprs; |
2021 | unsigned max_threads; |
2022 | unsigned max_stack_entries; |
2023 | unsigned max_hw_contexts; |
2024 | unsigned max_gs_threads; |
2025 | unsigned sx_max_export_size; |
2026 | unsigned sx_max_export_pos_size; |
2027 | unsigned sx_max_export_smx_size; |
2028 | unsigned sq_num_cf_insts; |
2029 | unsigned tiling_nbanks; |
2030 | unsigned tiling_npipes; |
2031 | unsigned tiling_group_size; |
2032 | unsigned tile_config; |
2033 | unsigned backend_map; |
2034 | unsigned active_simds; |
2035 | }; |
2036 | |
2037 | struct rv770_asic { |
2038 | unsigned max_pipes; |
2039 | unsigned max_tile_pipes; |
2040 | unsigned max_simds; |
2041 | unsigned max_backends; |
2042 | unsigned max_gprs; |
2043 | unsigned max_threads; |
2044 | unsigned max_stack_entries; |
2045 | unsigned max_hw_contexts; |
2046 | unsigned max_gs_threads; |
2047 | unsigned sx_max_export_size; |
2048 | unsigned sx_max_export_pos_size; |
2049 | unsigned sx_max_export_smx_size; |
2050 | unsigned sq_num_cf_insts; |
2051 | unsigned sx_num_of_sets; |
2052 | unsigned sc_prim_fifo_size; |
2053 | unsigned sc_hiz_tile_fifo_size; |
2054 | unsigned sc_earlyz_tile_fifo_fize; |
2055 | unsigned tiling_nbanks; |
2056 | unsigned tiling_npipes; |
2057 | unsigned tiling_group_size; |
2058 | unsigned tile_config; |
2059 | unsigned backend_map; |
2060 | unsigned active_simds; |
2061 | }; |
2062 | |
2063 | struct evergreen_asic { |
2064 | unsigned num_ses; |
2065 | unsigned max_pipes; |
2066 | unsigned max_tile_pipes; |
2067 | unsigned max_simds; |
2068 | unsigned max_backends; |
2069 | unsigned max_gprs; |
2070 | unsigned max_threads; |
2071 | unsigned max_stack_entries; |
2072 | unsigned max_hw_contexts; |
2073 | unsigned max_gs_threads; |
2074 | unsigned sx_max_export_size; |
2075 | unsigned sx_max_export_pos_size; |
2076 | unsigned sx_max_export_smx_size; |
2077 | unsigned sq_num_cf_insts; |
2078 | unsigned sx_num_of_sets; |
2079 | unsigned sc_prim_fifo_size; |
2080 | unsigned sc_hiz_tile_fifo_size; |
2081 | unsigned sc_earlyz_tile_fifo_size; |
2082 | unsigned tiling_nbanks; |
2083 | unsigned tiling_npipes; |
2084 | unsigned tiling_group_size; |
2085 | unsigned tile_config; |
2086 | unsigned backend_map; |
2087 | unsigned active_simds; |
2088 | }; |
2089 | |
2090 | struct cayman_asic { |
2091 | unsigned max_shader_engines; |
2092 | unsigned max_pipes_per_simd; |
2093 | unsigned max_tile_pipes; |
2094 | unsigned max_simds_per_se; |
2095 | unsigned max_backends_per_se; |
2096 | unsigned max_texture_channel_caches; |
2097 | unsigned max_gprs; |
2098 | unsigned max_threads; |
2099 | unsigned max_gs_threads; |
2100 | unsigned max_stack_entries; |
2101 | unsigned sx_num_of_sets; |
2102 | unsigned sx_max_export_size; |
2103 | unsigned sx_max_export_pos_size; |
2104 | unsigned sx_max_export_smx_size; |
2105 | unsigned max_hw_contexts; |
2106 | unsigned sq_num_cf_insts; |
2107 | unsigned sc_prim_fifo_size; |
2108 | unsigned sc_hiz_tile_fifo_size; |
2109 | unsigned sc_earlyz_tile_fifo_size; |
2110 | |
2111 | unsigned num_shader_engines; |
2112 | unsigned num_shader_pipes_per_simd; |
2113 | unsigned num_tile_pipes; |
2114 | unsigned num_simds_per_se; |
2115 | unsigned num_backends_per_se; |
2116 | unsigned backend_disable_mask_per_asic; |
2117 | unsigned backend_map; |
2118 | unsigned num_texture_channel_caches; |
2119 | unsigned mem_max_burst_length_bytes; |
2120 | unsigned mem_row_size_in_kb; |
2121 | unsigned shader_engine_tile_size; |
2122 | unsigned num_gpus; |
2123 | unsigned multi_gpu_tile_size; |
2124 | |
2125 | unsigned tile_config; |
2126 | unsigned active_simds; |
2127 | }; |
2128 | |
2129 | struct si_asic { |
2130 | unsigned max_shader_engines; |
2131 | unsigned max_tile_pipes; |
2132 | unsigned max_cu_per_sh; |
2133 | unsigned max_sh_per_se; |
2134 | unsigned max_backends_per_se; |
2135 | unsigned max_texture_channel_caches; |
2136 | unsigned max_gprs; |
2137 | unsigned max_gs_threads; |
2138 | unsigned max_hw_contexts; |
2139 | unsigned sc_prim_fifo_size_frontend; |
2140 | unsigned sc_prim_fifo_size_backend; |
2141 | unsigned sc_hiz_tile_fifo_size; |
2142 | unsigned sc_earlyz_tile_fifo_size; |
2143 | |
2144 | unsigned num_tile_pipes; |
2145 | unsigned backend_enable_mask; |
2146 | unsigned backend_disable_mask_per_asic; |
2147 | unsigned backend_map; |
2148 | unsigned num_texture_channel_caches; |
2149 | unsigned mem_max_burst_length_bytes; |
2150 | unsigned mem_row_size_in_kb; |
2151 | unsigned shader_engine_tile_size; |
2152 | unsigned num_gpus; |
2153 | unsigned multi_gpu_tile_size; |
2154 | |
2155 | unsigned tile_config; |
2156 | uint32_t tile_mode_array[32]; |
2157 | uint32_t active_cus; |
2158 | }; |
2159 | |
2160 | struct cik_asic { |
2161 | unsigned max_shader_engines; |
2162 | unsigned max_tile_pipes; |
2163 | unsigned max_cu_per_sh; |
2164 | unsigned max_sh_per_se; |
2165 | unsigned max_backends_per_se; |
2166 | unsigned max_texture_channel_caches; |
2167 | unsigned max_gprs; |
2168 | unsigned max_gs_threads; |
2169 | unsigned max_hw_contexts; |
2170 | unsigned sc_prim_fifo_size_frontend; |
2171 | unsigned sc_prim_fifo_size_backend; |
2172 | unsigned sc_hiz_tile_fifo_size; |
2173 | unsigned sc_earlyz_tile_fifo_size; |
2174 | |
2175 | unsigned num_tile_pipes; |
2176 | unsigned backend_enable_mask; |
2177 | unsigned backend_disable_mask_per_asic; |
2178 | unsigned backend_map; |
2179 | unsigned num_texture_channel_caches; |
2180 | unsigned mem_max_burst_length_bytes; |
2181 | unsigned mem_row_size_in_kb; |
2182 | unsigned shader_engine_tile_size; |
2183 | unsigned num_gpus; |
2184 | unsigned multi_gpu_tile_size; |
2185 | |
2186 | unsigned tile_config; |
2187 | uint32_t tile_mode_array[32]; |
2188 | uint32_t macrotile_mode_array[16]; |
2189 | uint32_t active_cus; |
2190 | }; |
2191 | |
2192 | union radeon_asic_config { |
2193 | struct r300_asic r300; |
2194 | struct r100_asic r100; |
2195 | struct r600_asic r600; |
2196 | struct rv770_asic rv770; |
2197 | struct evergreen_asic evergreen; |
2198 | struct cayman_asic cayman; |
2199 | struct si_asic si; |
2200 | struct cik_asic cik; |
2201 | }; |
2202 | |
2203 | /* |
2204 | * asic initizalization from radeon_asic.c |
2205 | */ |
2206 | void radeon_agp_disable(struct radeon_device *rdev); |
2207 | int radeon_asic_init(struct radeon_device *rdev); |
2208 | |
2209 | |
2210 | /* |
2211 | * IOCTL. |
2212 | */ |
2213 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, |
2214 | struct drm_file *filp); |
2215 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, |
2216 | struct drm_file *filp); |
2217 | int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, |
2218 | struct drm_file *filp); |
2219 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, |
2220 | struct drm_file *file_priv); |
2221 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, |
2222 | struct drm_file *file_priv); |
2223 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
2224 | struct drm_file *file_priv); |
2225 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, |
2226 | struct drm_file *file_priv); |
2227 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2228 | struct drm_file *filp); |
2229 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, |
2230 | struct drm_file *filp); |
2231 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, |
2232 | struct drm_file *filp); |
2233 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, |
2234 | struct drm_file *filp); |
2235 | int radeon_gem_va_ioctl(struct drm_device *dev, void *data, |
2236 | struct drm_file *filp); |
2237 | int radeon_gem_op_ioctl(struct drm_device *dev, void *data, |
2238 | struct drm_file *filp); |
2239 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
2240 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
2241 | struct drm_file *filp); |
2242 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, |
2243 | struct drm_file *filp); |
2244 | |
2245 | /* VRAM scratch page for HDP bug, default vram page */ |
2246 | struct r600_vram_scratch { |
2247 | struct radeon_bo *robj; |
2248 | volatile uint32_t *ptr; |
2249 | u64 gpu_addr; |
2250 | }; |
2251 | |
2252 | /* |
2253 | * ACPI |
2254 | */ |
2255 | struct radeon_atif_notification_cfg { |
2256 | bool enabled; |
2257 | int command_code; |
2258 | }; |
2259 | |
2260 | struct radeon_atif_notifications { |
2261 | bool display_switch; |
2262 | bool expansion_mode_change; |
2263 | bool thermal_state; |
2264 | bool forced_power_state; |
2265 | bool system_power_state; |
2266 | bool display_conf_change; |
2267 | bool px_gfx_switch; |
2268 | bool brightness_change; |
2269 | bool dgpu_display_event; |
2270 | }; |
2271 | |
2272 | struct radeon_atif_functions { |
2273 | bool system_params; |
2274 | bool sbios_requests; |
2275 | bool select_active_disp; |
2276 | bool lid_state; |
2277 | bool get_tv_standard; |
2278 | bool set_tv_standard; |
2279 | bool get_panel_expansion_mode; |
2280 | bool set_panel_expansion_mode; |
2281 | bool temperature_change; |
2282 | bool graphics_device_types; |
2283 | }; |
2284 | |
2285 | struct radeon_atif { |
2286 | struct radeon_atif_notifications notifications; |
2287 | struct radeon_atif_functions functions; |
2288 | struct radeon_atif_notification_cfg notification_cfg; |
2289 | struct radeon_encoder *encoder_for_bl; |
2290 | }; |
2291 | |
2292 | struct radeon_atcs_functions { |
2293 | bool get_ext_state; |
2294 | bool pcie_perf_req; |
2295 | bool pcie_dev_rdy; |
2296 | bool pcie_bus_width; |
2297 | }; |
2298 | |
2299 | struct radeon_atcs { |
2300 | struct radeon_atcs_functions functions; |
2301 | }; |
2302 | |
2303 | /* |
2304 | * Core structure, functions and helpers. |
2305 | */ |
2306 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
2307 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
2308 | |
2309 | struct radeon_device { |
2310 | struct device *dev; |
2311 | struct drm_device *ddev; |
2312 | struct pci_dev *pdev; |
2313 | struct rw_semaphore exclusive_lock; |
2314 | /* ASIC */ |
2315 | union radeon_asic_config config; |
2316 | enum radeon_family family; |
2317 | unsigned long flags; |
2318 | int usec_timeout; |
2319 | enum radeon_pll_errata pll_errata; |
2320 | int num_gb_pipes; |
2321 | int num_z_pipes; |
2322 | int disp_priority; |
2323 | /* BIOS */ |
2324 | uint8_t *bios; |
2325 | bool is_atom_bios; |
2326 | uint16_t ; |
2327 | struct radeon_bo *stolen_vga_memory; |
2328 | /* Register mmio */ |
2329 | resource_size_t rmmio_base; |
2330 | resource_size_t rmmio_size; |
2331 | /* protects concurrent MM_INDEX/DATA based register access */ |
2332 | spinlock_t mmio_idx_lock; |
2333 | /* protects concurrent SMC based register access */ |
2334 | spinlock_t smc_idx_lock; |
2335 | /* protects concurrent PLL register access */ |
2336 | spinlock_t pll_idx_lock; |
2337 | /* protects concurrent MC register access */ |
2338 | spinlock_t mc_idx_lock; |
2339 | /* protects concurrent PCIE register access */ |
2340 | spinlock_t pcie_idx_lock; |
2341 | /* protects concurrent PCIE_PORT register access */ |
2342 | spinlock_t pciep_idx_lock; |
2343 | /* protects concurrent PIF register access */ |
2344 | spinlock_t pif_idx_lock; |
2345 | /* protects concurrent CG register access */ |
2346 | spinlock_t cg_idx_lock; |
2347 | /* protects concurrent UVD register access */ |
2348 | spinlock_t uvd_idx_lock; |
2349 | /* protects concurrent RCU register access */ |
2350 | spinlock_t rcu_idx_lock; |
2351 | /* protects concurrent DIDT register access */ |
2352 | spinlock_t didt_idx_lock; |
2353 | /* protects concurrent ENDPOINT (audio) register access */ |
2354 | spinlock_t end_idx_lock; |
2355 | void __iomem *rmmio; |
2356 | radeon_rreg_t mc_rreg; |
2357 | radeon_wreg_t mc_wreg; |
2358 | radeon_rreg_t pll_rreg; |
2359 | radeon_wreg_t pll_wreg; |
2360 | uint32_t pcie_reg_mask; |
2361 | radeon_rreg_t pciep_rreg; |
2362 | radeon_wreg_t pciep_wreg; |
2363 | /* io port */ |
2364 | void __iomem *rio_mem; |
2365 | resource_size_t rio_mem_size; |
2366 | struct radeon_clock clock; |
2367 | struct radeon_mc mc; |
2368 | struct radeon_gart gart; |
2369 | struct radeon_mode_info mode_info; |
2370 | struct radeon_scratch scratch; |
2371 | struct radeon_doorbell doorbell; |
2372 | struct radeon_mman mman; |
2373 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
2374 | wait_queue_head_t fence_queue; |
2375 | u64 fence_context; |
2376 | struct mutex ring_lock; |
2377 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
2378 | bool ib_pool_ready; |
2379 | struct radeon_sa_manager ring_tmp_bo; |
2380 | struct radeon_irq irq; |
2381 | struct radeon_asic *asic; |
2382 | struct radeon_gem gem; |
2383 | struct radeon_pm pm; |
2384 | struct radeon_uvd uvd; |
2385 | struct radeon_vce vce; |
2386 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
2387 | struct radeon_wb wb; |
2388 | struct radeon_dummy_page dummy_page; |
2389 | bool shutdown; |
2390 | bool need_dma32; |
2391 | bool need_swiotlb; |
2392 | bool accel_working; |
2393 | bool fastfb_working; /* IGP feature*/ |
2394 | bool needs_reset, in_reset; |
2395 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
2396 | const struct firmware *me_fw; /* all family ME firmware */ |
2397 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
2398 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
2399 | const struct firmware *mc_fw; /* NI MC firmware */ |
2400 | const struct firmware *ce_fw; /* SI CE firmware */ |
2401 | const struct firmware *mec_fw; /* CIK MEC firmware */ |
2402 | const struct firmware *mec2_fw; /* KV MEC2 firmware */ |
2403 | const struct firmware *sdma_fw; /* CIK SDMA firmware */ |
2404 | const struct firmware *smc_fw; /* SMC firmware */ |
2405 | const struct firmware *uvd_fw; /* UVD firmware */ |
2406 | const struct firmware *vce_fw; /* VCE firmware */ |
2407 | bool new_fw; |
2408 | struct r600_vram_scratch vram_scratch; |
2409 | int msi_enabled; /* msi enabled */ |
2410 | struct r600_ih ih; /* r6/700 interrupt ring */ |
2411 | struct radeon_rlc rlc; |
2412 | struct radeon_mec mec; |
2413 | struct delayed_work hotplug_work; |
2414 | struct work_struct dp_work; |
2415 | struct work_struct audio_work; |
2416 | int num_crtc; /* number of crtcs */ |
2417 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
2418 | bool has_uvd; |
2419 | bool has_vce; |
2420 | struct r600_audio audio; /* audio stuff */ |
2421 | struct notifier_block acpi_nb; |
2422 | /* only one userspace can use Hyperz features or CMASK at a time */ |
2423 | struct drm_file *hyperz_filp; |
2424 | struct drm_file *cmask_filp; |
2425 | /* i2c buses */ |
2426 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; |
2427 | /* debugfs */ |
2428 | struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; |
2429 | unsigned debugfs_count; |
2430 | /* virtual memory */ |
2431 | struct radeon_vm_manager vm_manager; |
2432 | struct mutex gpu_clock_mutex; |
2433 | /* memory stats */ |
2434 | atomic64_t vram_usage; |
2435 | atomic64_t gtt_usage; |
2436 | atomic64_t num_bytes_moved; |
2437 | atomic_t gpu_reset_counter; |
2438 | /* ACPI interface */ |
2439 | struct radeon_atif atif; |
2440 | struct radeon_atcs atcs; |
2441 | /* srbm instance registers */ |
2442 | struct mutex srbm_mutex; |
2443 | /* clock, powergating flags */ |
2444 | u32 cg_flags; |
2445 | u32 pg_flags; |
2446 | |
2447 | struct dev_pm_domain vga_pm_domain; |
2448 | bool have_disp_power_ref; |
2449 | u32 px_quirk_flags; |
2450 | |
2451 | /* tracking pinned memory */ |
2452 | u64 vram_pin_size; |
2453 | u64 gart_pin_size; |
2454 | |
2455 | struct mutex mn_lock; |
2456 | DECLARE_HASHTABLE(mn_hash, 7); |
2457 | }; |
2458 | |
2459 | bool radeon_is_px(struct drm_device *dev); |
2460 | int radeon_device_init(struct radeon_device *rdev, |
2461 | struct drm_device *ddev, |
2462 | struct pci_dev *pdev, |
2463 | uint32_t flags); |
2464 | void radeon_device_fini(struct radeon_device *rdev); |
2465 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
2466 | |
2467 | #define RADEON_MIN_MMIO_SIZE 0x10000 |
2468 | |
2469 | uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); |
2470 | void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
2471 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, |
2472 | bool always_indirect) |
2473 | { |
2474 | /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ |
2475 | if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) |
2476 | return readl(((void __iomem *)rdev->rmmio) + reg); |
2477 | else |
2478 | return r100_mm_rreg_slow(rdev, reg); |
2479 | } |
2480 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, |
2481 | bool always_indirect) |
2482 | { |
2483 | if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) |
2484 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
2485 | else |
2486 | r100_mm_wreg_slow(rdev, reg, v); |
2487 | } |
2488 | |
2489 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
2490 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2491 | |
2492 | u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); |
2493 | void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); |
2494 | |
2495 | /* |
2496 | * Cast helper |
2497 | */ |
2498 | extern const struct dma_fence_ops radeon_fence_ops; |
2499 | |
2500 | static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f) |
2501 | { |
2502 | struct radeon_fence *__f = container_of(f, struct radeon_fence, base); |
2503 | |
2504 | if (__f->base.ops == &radeon_fence_ops) |
2505 | return __f; |
2506 | |
2507 | return NULL; |
2508 | } |
2509 | |
2510 | /* |
2511 | * Registers read & write functions. |
2512 | */ |
2513 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
2514 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) |
2515 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) |
2516 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) |
2517 | #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) |
2518 | #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) |
2519 | #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \ |
2520 | r100_mm_rreg(rdev, (reg), false)) |
2521 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) |
2522 | #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) |
2523 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
2524 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
2525 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
2526 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
2527 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
2528 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
2529 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
2530 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
2531 | #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) |
2532 | #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
2533 | #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) |
2534 | #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) |
2535 | #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) |
2536 | #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) |
2537 | #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) |
2538 | #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) |
2539 | #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) |
2540 | #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) |
2541 | #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) |
2542 | #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) |
2543 | #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) |
2544 | #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) |
2545 | #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) |
2546 | #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) |
2547 | #define WREG32_P(reg, val, mask) \ |
2548 | do { \ |
2549 | uint32_t tmp_ = RREG32(reg); \ |
2550 | tmp_ &= (mask); \ |
2551 | tmp_ |= ((val) & ~(mask)); \ |
2552 | WREG32(reg, tmp_); \ |
2553 | } while (0) |
2554 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) |
2555 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) |
2556 | #define WREG32_PLL_P(reg, val, mask) \ |
2557 | do { \ |
2558 | uint32_t tmp_ = RREG32_PLL(reg); \ |
2559 | tmp_ &= (mask); \ |
2560 | tmp_ |= ((val) & ~(mask)); \ |
2561 | WREG32_PLL(reg, tmp_); \ |
2562 | } while (0) |
2563 | #define WREG32_SMC_P(reg, val, mask) \ |
2564 | do { \ |
2565 | uint32_t tmp_ = RREG32_SMC(reg); \ |
2566 | tmp_ &= (mask); \ |
2567 | tmp_ |= ((val) & ~(mask)); \ |
2568 | WREG32_SMC(reg, tmp_); \ |
2569 | } while (0) |
2570 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) |
2571 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
2572 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) |
2573 | |
2574 | #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) |
2575 | #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) |
2576 | |
2577 | /* |
2578 | * Indirect registers accessors. |
2579 | * They used to be inlined, but this increases code size by ~65 kbytes. |
2580 | * Since each performs a pair of MMIO ops |
2581 | * within a spin_lock_irqsave/spin_unlock_irqrestore region, |
2582 | * the cost of call+ret is almost negligible. MMIO and locking |
2583 | * costs several dozens of cycles each at best, call+ret is ~5 cycles. |
2584 | */ |
2585 | uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
2586 | void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
2587 | u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); |
2588 | void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2589 | u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); |
2590 | void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2591 | u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); |
2592 | void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2593 | u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); |
2594 | void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2595 | u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); |
2596 | void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2597 | u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); |
2598 | void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2599 | u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); |
2600 | void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
2601 | |
2602 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
2603 | |
2604 | |
2605 | /* |
2606 | * ASICs helpers. |
2607 | */ |
2608 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
2609 | (rdev->pdev->device == 0x5969)) |
2610 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
2611 | (rdev->family == CHIP_RV200) || \ |
2612 | (rdev->family == CHIP_RS100) || \ |
2613 | (rdev->family == CHIP_RS200) || \ |
2614 | (rdev->family == CHIP_RV250) || \ |
2615 | (rdev->family == CHIP_RV280) || \ |
2616 | (rdev->family == CHIP_RS300)) |
2617 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
2618 | (rdev->family == CHIP_RV350) || \ |
2619 | (rdev->family == CHIP_R350) || \ |
2620 | (rdev->family == CHIP_RV380) || \ |
2621 | (rdev->family == CHIP_R420) || \ |
2622 | (rdev->family == CHIP_R423) || \ |
2623 | (rdev->family == CHIP_RV410) || \ |
2624 | (rdev->family == CHIP_RS400) || \ |
2625 | (rdev->family == CHIP_RS480)) |
2626 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
2627 | (rdev->ddev->pdev->device == 0x9443) || \ |
2628 | (rdev->ddev->pdev->device == 0x944B) || \ |
2629 | (rdev->ddev->pdev->device == 0x9506) || \ |
2630 | (rdev->ddev->pdev->device == 0x9509) || \ |
2631 | (rdev->ddev->pdev->device == 0x950F) || \ |
2632 | (rdev->ddev->pdev->device == 0x689C) || \ |
2633 | (rdev->ddev->pdev->device == 0x689D)) |
2634 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
2635 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
2636 | (rdev->family == CHIP_RS690) || \ |
2637 | (rdev->family == CHIP_RS740) || \ |
2638 | (rdev->family >= CHIP_R600)) |
2639 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
2640 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
2641 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
2642 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
2643 | (rdev->flags & RADEON_IS_IGP)) |
2644 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
2645 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
2646 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ |
2647 | (rdev->flags & RADEON_IS_IGP)) |
2648 | #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) |
2649 | #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) |
2650 | #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) |
2651 | #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) |
2652 | #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) |
2653 | #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ |
2654 | (rdev->family == CHIP_MULLINS)) |
2655 | |
2656 | #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ |
2657 | (rdev->ddev->pdev->device == 0x6850) || \ |
2658 | (rdev->ddev->pdev->device == 0x6858) || \ |
2659 | (rdev->ddev->pdev->device == 0x6859) || \ |
2660 | (rdev->ddev->pdev->device == 0x6840) || \ |
2661 | (rdev->ddev->pdev->device == 0x6841) || \ |
2662 | (rdev->ddev->pdev->device == 0x6842) || \ |
2663 | (rdev->ddev->pdev->device == 0x6843)) |
2664 | |
2665 | /* |
2666 | * BIOS helpers. |
2667 | */ |
2668 | #define RBIOS8(i) (rdev->bios[i]) |
2669 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
2670 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
2671 | |
2672 | int radeon_combios_init(struct radeon_device *rdev); |
2673 | void radeon_combios_fini(struct radeon_device *rdev); |
2674 | int radeon_atombios_init(struct radeon_device *rdev); |
2675 | void radeon_atombios_fini(struct radeon_device *rdev); |
2676 | |
2677 | |
2678 | /* |
2679 | * RING helpers. |
2680 | */ |
2681 | |
2682 | /** |
2683 | * radeon_ring_write - write a value to the ring |
2684 | * |
2685 | * @ring: radeon_ring structure holding ring information |
2686 | * @v: dword (dw) value to write |
2687 | * |
2688 | * Write a value to the requested ring buffer (all asics). |
2689 | */ |
2690 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
2691 | { |
2692 | if (ring->count_dw <= 0) |
2693 | DRM_ERROR("radeon: writing more dwords to the ring than expected!\n" ); |
2694 | |
2695 | ring->ring[ring->wptr++] = v; |
2696 | ring->wptr &= ring->ptr_mask; |
2697 | ring->count_dw--; |
2698 | ring->ring_free_dw--; |
2699 | } |
2700 | |
2701 | /* |
2702 | * ASICs macro. |
2703 | */ |
2704 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
2705 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
2706 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
2707 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
2708 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) |
2709 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
2710 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false) |
2711 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
2712 | #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) |
2713 | #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) |
2714 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
2715 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) |
2716 | #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) |
2717 | #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
2718 | #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
2719 | #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) |
2720 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) |
2721 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) |
2722 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) |
2723 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) |
2724 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) |
2725 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) |
2726 | #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) |
2727 | #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) |
2728 | #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) |
2729 | #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) |
2730 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
2731 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) |
2732 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
2733 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
2734 | #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) |
2735 | #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) |
2736 | #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) |
2737 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) |
2738 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) |
2739 | #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) |
2740 | #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) |
2741 | #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) |
2742 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index |
2743 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index |
2744 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index |
2745 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
2746 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) |
2747 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) |
2748 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) |
2749 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) |
2750 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) |
2751 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) |
2752 | #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) |
2753 | #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) |
2754 | #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) |
2755 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
2756 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) |
2757 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
2758 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
2759 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) |
2760 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) |
2761 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) |
2762 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
2763 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
2764 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) |
2765 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) |
2766 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) |
2767 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) |
2768 | #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async)) |
2769 | #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) |
2770 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) |
2771 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) |
2772 | #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) |
2773 | #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) |
2774 | #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) |
2775 | #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) |
2776 | #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) |
2777 | #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) |
2778 | #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) |
2779 | #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) |
2780 | #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) |
2781 | #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) |
2782 | #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) |
2783 | #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) |
2784 | #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) |
2785 | #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) |
2786 | #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) |
2787 | #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) |
2788 | #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) |
2789 | #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) |
2790 | #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) |
2791 | #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) |
2792 | #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) |
2793 | #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) |
2794 | #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) |
2795 | |
2796 | /* Common functions */ |
2797 | /* AGP */ |
2798 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
2799 | extern void radeon_pci_config_reset(struct radeon_device *rdev); |
2800 | extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); |
2801 | extern void radeon_agp_disable(struct radeon_device *rdev); |
2802 | extern int radeon_modeset_init(struct radeon_device *rdev); |
2803 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
2804 | extern bool radeon_card_posted(struct radeon_device *rdev); |
2805 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
2806 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
2807 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
2808 | extern void radeon_scratch_init(struct radeon_device *rdev); |
2809 | extern void radeon_wb_fini(struct radeon_device *rdev); |
2810 | extern int radeon_wb_init(struct radeon_device *rdev); |
2811 | extern void radeon_wb_disable(struct radeon_device *rdev); |
2812 | extern void radeon_surface_init(struct radeon_device *rdev); |
2813 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
2814 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
2815 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
2816 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
2817 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
2818 | extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, |
2819 | uint32_t flags); |
2820 | extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); |
2821 | extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); |
2822 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
2823 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
2824 | extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); |
2825 | extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, |
2826 | bool fbcon, bool freeze); |
2827 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
2828 | extern void radeon_program_register_sequence(struct radeon_device *rdev, |
2829 | const u32 *registers, |
2830 | const u32 array_size); |
2831 | |
2832 | /* |
2833 | * vm |
2834 | */ |
2835 | int radeon_vm_manager_init(struct radeon_device *rdev); |
2836 | void radeon_vm_manager_fini(struct radeon_device *rdev); |
2837 | int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
2838 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
2839 | struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, |
2840 | struct radeon_vm *vm, |
2841 | struct list_head *head); |
2842 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
2843 | struct radeon_vm *vm, int ring); |
2844 | void radeon_vm_flush(struct radeon_device *rdev, |
2845 | struct radeon_vm *vm, |
2846 | int ring, struct radeon_fence *fence); |
2847 | void radeon_vm_fence(struct radeon_device *rdev, |
2848 | struct radeon_vm *vm, |
2849 | struct radeon_fence *fence); |
2850 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); |
2851 | int radeon_vm_update_page_directory(struct radeon_device *rdev, |
2852 | struct radeon_vm *vm); |
2853 | int radeon_vm_clear_freed(struct radeon_device *rdev, |
2854 | struct radeon_vm *vm); |
2855 | int radeon_vm_clear_invalids(struct radeon_device *rdev, |
2856 | struct radeon_vm *vm); |
2857 | int radeon_vm_bo_update(struct radeon_device *rdev, |
2858 | struct radeon_bo_va *bo_va, |
2859 | struct ttm_mem_reg *mem); |
2860 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, |
2861 | struct radeon_bo *bo); |
2862 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
2863 | struct radeon_bo *bo); |
2864 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
2865 | struct radeon_vm *vm, |
2866 | struct radeon_bo *bo); |
2867 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, |
2868 | struct radeon_bo_va *bo_va, |
2869 | uint64_t offset, |
2870 | uint32_t flags); |
2871 | void radeon_vm_bo_rmv(struct radeon_device *rdev, |
2872 | struct radeon_bo_va *bo_va); |
2873 | |
2874 | /* audio */ |
2875 | void r600_audio_update_hdmi(struct work_struct *work); |
2876 | struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); |
2877 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); |
2878 | void r600_audio_enable(struct radeon_device *rdev, |
2879 | struct r600_audio_pin *pin, |
2880 | u8 enable_mask); |
2881 | void dce6_audio_enable(struct radeon_device *rdev, |
2882 | struct r600_audio_pin *pin, |
2883 | u8 enable_mask); |
2884 | |
2885 | /* |
2886 | * R600 vram scratch functions |
2887 | */ |
2888 | int r600_vram_scratch_init(struct radeon_device *rdev); |
2889 | void r600_vram_scratch_fini(struct radeon_device *rdev); |
2890 | |
2891 | /* |
2892 | * r600 cs checking helper |
2893 | */ |
2894 | unsigned r600_mip_minify(unsigned size, unsigned level); |
2895 | bool r600_fmt_is_valid_color(u32 format); |
2896 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); |
2897 | int r600_fmt_get_blocksize(u32 format); |
2898 | int r600_fmt_get_nblocksx(u32 format, u32 w); |
2899 | int r600_fmt_get_nblocksy(u32 format, u32 h); |
2900 | |
2901 | /* |
2902 | * r600 functions used by radeon_encoder.c |
2903 | */ |
2904 | struct radeon_hdmi_acr { |
2905 | u32 clock; |
2906 | |
2907 | int n_32khz; |
2908 | int cts_32khz; |
2909 | |
2910 | int n_44_1khz; |
2911 | int cts_44_1khz; |
2912 | |
2913 | int n_48khz; |
2914 | int cts_48khz; |
2915 | |
2916 | }; |
2917 | |
2918 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
2919 | |
2920 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
2921 | u32 tiling_pipe_num, |
2922 | u32 max_rb_num, |
2923 | u32 total_max_rb_num, |
2924 | u32 enabled_rb_mask); |
2925 | |
2926 | /* |
2927 | * evergreen functions used by radeon_encoder.c |
2928 | */ |
2929 | |
2930 | extern int ni_init_microcode(struct radeon_device *rdev); |
2931 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
2932 | |
2933 | /* radeon_acpi.c */ |
2934 | #if defined(CONFIG_ACPI) |
2935 | extern int radeon_acpi_init(struct radeon_device *rdev); |
2936 | extern void radeon_acpi_fini(struct radeon_device *rdev); |
2937 | extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); |
2938 | extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, |
2939 | u8 perf_req, bool advertise); |
2940 | extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); |
2941 | #else |
2942 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } |
2943 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } |
2944 | #endif |
2945 | |
2946 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, |
2947 | struct radeon_cs_packet *pkt, |
2948 | unsigned idx); |
2949 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); |
2950 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, |
2951 | struct radeon_cs_packet *pkt); |
2952 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, |
2953 | struct radeon_bo_list **cs_reloc, |
2954 | int nomm); |
2955 | int r600_cs_common_vline_parse(struct radeon_cs_parser *p, |
2956 | uint32_t *vline_start_end, |
2957 | uint32_t *vline_status); |
2958 | |
2959 | /* interrupt control register helpers */ |
2960 | void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev, |
2961 | u32 reg, u32 mask, |
2962 | bool enable, const char *name, |
2963 | unsigned n); |
2964 | |
2965 | #include "radeon_object.h" |
2966 | |
2967 | #endif |
2968 | |