1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_util.h>
28#include <drm/drm_crtc_helper.h>
29#include <drm/radeon_drm.h>
30#include "radeon.h"
31#include "radeon_asic.h"
32#include "atom.h"
33#include <linux/backlight.h>
34#ifdef CONFIG_PMAC_BACKLIGHT
35#include <asm/backlight.h>
36#endif
37
38static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
39{
40 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
41 const struct drm_encoder_helper_funcs *encoder_funcs;
42
43 encoder_funcs = encoder->helper_private;
44 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
45 radeon_encoder->active_device = 0;
46}
47
48static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
49{
50 struct drm_device *dev = encoder->dev;
51 struct radeon_device *rdev = dev->dev_private;
52 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
53 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
54 int panel_pwr_delay = 2000;
55 bool is_mac = false;
56 uint8_t backlight_level;
57 DRM_DEBUG_KMS("\n");
58
59 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
60 backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
61
62 if (radeon_encoder->enc_priv) {
63 if (rdev->is_atom_bios) {
64 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
65 panel_pwr_delay = lvds->panel_pwr_delay;
66 if (lvds->bl_dev)
67 backlight_level = lvds->backlight_level;
68 } else {
69 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
70 panel_pwr_delay = lvds->panel_pwr_delay;
71 if (lvds->bl_dev)
72 backlight_level = lvds->backlight_level;
73 }
74 }
75
76 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
77 * Taken from radeonfb.
78 */
79 if ((rdev->mode_info.connector_table == CT_IBOOK) ||
80 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
81 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
82 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
83 is_mac = true;
84
85 switch (mode) {
86 case DRM_MODE_DPMS_ON:
87 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
88 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
89 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
90 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
91 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
92 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
93 mdelay(1);
94
95 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
96 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
97 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
98
99 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
100 RADEON_LVDS_BL_MOD_LEVEL_MASK);
101 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
102 RADEON_LVDS_DIGON | RADEON_LVDS_BLON |
103 (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
104 if (is_mac)
105 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
106 mdelay(panel_pwr_delay);
107 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
108 break;
109 case DRM_MODE_DPMS_STANDBY:
110 case DRM_MODE_DPMS_SUSPEND:
111 case DRM_MODE_DPMS_OFF:
112 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
113 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
114 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
115 if (is_mac) {
116 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
117 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
118 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
119 } else {
120 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
121 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
122 }
123 mdelay(panel_pwr_delay);
124 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
125 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
126 mdelay(panel_pwr_delay);
127 break;
128 }
129
130 if (rdev->is_atom_bios)
131 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
132 else
133 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
134
135}
136
137static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
138{
139 struct radeon_device *rdev = encoder->dev->dev_private;
140 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
141 DRM_DEBUG("\n");
142
143 if (radeon_encoder->enc_priv) {
144 if (rdev->is_atom_bios) {
145 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
146 lvds->dpms_mode = mode;
147 } else {
148 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
149 lvds->dpms_mode = mode;
150 }
151 }
152
153 radeon_legacy_lvds_update(encoder, mode);
154}
155
156static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
157{
158 struct radeon_device *rdev = encoder->dev->dev_private;
159
160 if (rdev->is_atom_bios)
161 radeon_atom_output_lock(encoder, true);
162 else
163 radeon_combios_output_lock(encoder, true);
164 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
165}
166
167static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
168{
169 struct radeon_device *rdev = encoder->dev->dev_private;
170
171 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
172 if (rdev->is_atom_bios)
173 radeon_atom_output_lock(encoder, false);
174 else
175 radeon_combios_output_lock(encoder, false);
176}
177
178static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
179 struct drm_display_mode *mode,
180 struct drm_display_mode *adjusted_mode)
181{
182 struct drm_device *dev = encoder->dev;
183 struct radeon_device *rdev = dev->dev_private;
184 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
185 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
186 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
187
188 DRM_DEBUG_KMS("\n");
189
190 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
191 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
192
193 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
194 if (rdev->is_atom_bios) {
195 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
196 * need to call that on resume to set up the reg properly.
197 */
198 radeon_encoder->pixel_clock = adjusted_mode->clock;
199 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
200 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
201 } else {
202 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
203 if (lvds) {
204 DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
205 lvds_gen_cntl = lvds->lvds_gen_cntl;
206 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
207 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
208 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
209 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
210 } else
211 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
212 }
213 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
214 lvds_gen_cntl &= ~(RADEON_LVDS_ON |
215 RADEON_LVDS_BLON |
216 RADEON_LVDS_EN |
217 RADEON_LVDS_RST_FM);
218
219 if (ASIC_IS_R300(rdev))
220 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
221
222 if (radeon_crtc->crtc_id == 0) {
223 if (ASIC_IS_R300(rdev)) {
224 if (radeon_encoder->rmx_type != RMX_OFF)
225 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
226 } else
227 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
228 } else {
229 if (ASIC_IS_R300(rdev))
230 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
231 else
232 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
233 }
234
235 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
236 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
237 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
238
239 if (rdev->family == CHIP_RV410)
240 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
241
242 if (rdev->is_atom_bios)
243 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
244 else
245 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
246}
247
248static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
249 const struct drm_display_mode *mode,
250 struct drm_display_mode *adjusted_mode)
251{
252 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
253
254 /* set the active encoder to connector routing */
255 radeon_encoder_set_active_device(encoder);
256 drm_mode_set_crtcinfo(adjusted_mode, 0);
257
258 /* get the native mode for LVDS */
259 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
260 radeon_panel_mode_fixup(encoder, adjusted_mode);
261
262 return true;
263}
264
265static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
266 .dpms = radeon_legacy_lvds_dpms,
267 .mode_fixup = radeon_legacy_mode_fixup,
268 .prepare = radeon_legacy_lvds_prepare,
269 .mode_set = radeon_legacy_lvds_mode_set,
270 .commit = radeon_legacy_lvds_commit,
271 .disable = radeon_legacy_encoder_disable,
272};
273
274u8
275radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder)
276{
277 struct drm_device *dev = radeon_encoder->base.dev;
278 struct radeon_device *rdev = dev->dev_private;
279 u8 backlight_level;
280
281 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
282 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
283
284 return backlight_level;
285}
286
287void
288radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
289{
290 struct drm_device *dev = radeon_encoder->base.dev;
291 struct radeon_device *rdev = dev->dev_private;
292 int dpms_mode = DRM_MODE_DPMS_ON;
293
294 if (radeon_encoder->enc_priv) {
295 if (rdev->is_atom_bios) {
296 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
297 if (lvds->backlight_level > 0)
298 dpms_mode = lvds->dpms_mode;
299 else
300 dpms_mode = DRM_MODE_DPMS_OFF;
301 lvds->backlight_level = level;
302 } else {
303 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
304 if (lvds->backlight_level > 0)
305 dpms_mode = lvds->dpms_mode;
306 else
307 dpms_mode = DRM_MODE_DPMS_OFF;
308 lvds->backlight_level = level;
309 }
310 }
311
312 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
313}
314
315#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
316
317static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
318{
319 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
320 uint8_t level;
321
322 /* Convert brightness to hardware level */
323 if (bd->props.brightness < 0)
324 level = 0;
325 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
326 level = RADEON_MAX_BL_LEVEL;
327 else
328 level = bd->props.brightness;
329
330 if (pdata->negative)
331 level = RADEON_MAX_BL_LEVEL - level;
332
333 return level;
334}
335
336static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
337{
338 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
339 struct radeon_encoder *radeon_encoder = pdata->encoder;
340
341 radeon_legacy_set_backlight_level(radeon_encoder,
342 radeon_legacy_lvds_level(bd));
343
344 return 0;
345}
346
347static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
348{
349 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
350 struct radeon_encoder *radeon_encoder = pdata->encoder;
351 struct drm_device *dev = radeon_encoder->base.dev;
352 struct radeon_device *rdev = dev->dev_private;
353 uint8_t backlight_level;
354
355 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
356 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
357
358 return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level;
359}
360
361static const struct backlight_ops radeon_backlight_ops = {
362 .get_brightness = radeon_legacy_backlight_get_brightness,
363 .update_status = radeon_legacy_backlight_update_status,
364};
365
366void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
367 struct drm_connector *drm_connector)
368{
369 struct drm_device *dev = radeon_encoder->base.dev;
370 struct radeon_device *rdev = dev->dev_private;
371 struct backlight_device *bd;
372 struct backlight_properties props;
373 struct radeon_backlight_privdata *pdata;
374 uint8_t backlight_level;
375 char bl_name[16];
376
377 if (!radeon_encoder->enc_priv)
378 return;
379
380#ifdef CONFIG_PMAC_BACKLIGHT
381 if (!pmac_has_backlight_type("ati") &&
382 !pmac_has_backlight_type("mnca"))
383 return;
384#endif
385
386 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
387 if (!pdata) {
388 DRM_ERROR("Memory allocation failed\n");
389 goto error;
390 }
391
392 memset(&props, 0, sizeof(props));
393 props.max_brightness = RADEON_MAX_BL_LEVEL;
394 props.type = BACKLIGHT_RAW;
395 snprintf(bl_name, sizeof(bl_name),
396 "radeon_bl%d", dev->primary->index);
397 bd = backlight_device_register(bl_name, drm_connector->kdev,
398 pdata, &radeon_backlight_ops, &props);
399 if (IS_ERR(bd)) {
400 DRM_ERROR("Backlight registration failed\n");
401 goto error;
402 }
403
404 pdata->encoder = radeon_encoder;
405
406 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
407 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
408
409 /* First, try to detect backlight level sense based on the assumption
410 * that firmware set it up at full brightness
411 */
412 if (backlight_level == 0)
413 pdata->negative = true;
414 else if (backlight_level == 0xff)
415 pdata->negative = false;
416 else {
417 /* XXX hack... maybe some day we can figure out in what direction
418 * backlight should work on a given panel?
419 */
420 pdata->negative = (rdev->family != CHIP_RV200 &&
421 rdev->family != CHIP_RV250 &&
422 rdev->family != CHIP_RV280 &&
423 rdev->family != CHIP_RV350);
424
425#ifdef CONFIG_PMAC_BACKLIGHT
426 pdata->negative = (pdata->negative ||
427 of_machine_is_compatible("PowerBook4,3") ||
428 of_machine_is_compatible("PowerBook6,3") ||
429 of_machine_is_compatible("PowerBook6,5"));
430#endif
431 }
432
433 if (rdev->is_atom_bios) {
434 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
435 lvds->bl_dev = bd;
436 } else {
437 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
438 lvds->bl_dev = bd;
439 }
440
441 bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
442 bd->props.power = FB_BLANK_UNBLANK;
443 backlight_update_status(bd);
444
445 DRM_INFO("radeon legacy LVDS backlight initialized\n");
446 rdev->mode_info.bl_encoder = radeon_encoder;
447
448 return;
449
450error:
451 kfree(pdata);
452 return;
453}
454
455static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
456{
457 struct drm_device *dev = radeon_encoder->base.dev;
458 struct radeon_device *rdev = dev->dev_private;
459 struct backlight_device *bd = NULL;
460
461 if (!radeon_encoder->enc_priv)
462 return;
463
464 if (rdev->is_atom_bios) {
465 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
466 bd = lvds->bl_dev;
467 lvds->bl_dev = NULL;
468 } else {
469 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
470 bd = lvds->bl_dev;
471 lvds->bl_dev = NULL;
472 }
473
474 if (bd) {
475 struct radeon_backlight_privdata *pdata;
476
477 pdata = bl_get_data(bd);
478 backlight_device_unregister(bd);
479 kfree(pdata);
480
481 DRM_INFO("radeon legacy LVDS backlight unloaded\n");
482 }
483}
484
485#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
486
487void radeon_legacy_backlight_init(struct radeon_encoder *encoder)
488{
489}
490
491static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
492{
493}
494
495#endif
496
497
498static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
499{
500 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
501
502 if (radeon_encoder->enc_priv) {
503 radeon_legacy_backlight_exit(radeon_encoder);
504 kfree(radeon_encoder->enc_priv);
505 }
506 drm_encoder_cleanup(encoder);
507 kfree(radeon_encoder);
508}
509
510static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
511 .destroy = radeon_lvds_enc_destroy,
512};
513
514static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
515{
516 struct drm_device *dev = encoder->dev;
517 struct radeon_device *rdev = dev->dev_private;
518 uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
519 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
520 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
521
522 DRM_DEBUG_KMS("\n");
523
524 switch (mode) {
525 case DRM_MODE_DPMS_ON:
526 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
527 dac_cntl &= ~RADEON_DAC_PDWN;
528 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
529 RADEON_DAC_PDWN_G |
530 RADEON_DAC_PDWN_B);
531 break;
532 case DRM_MODE_DPMS_STANDBY:
533 case DRM_MODE_DPMS_SUSPEND:
534 case DRM_MODE_DPMS_OFF:
535 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
536 dac_cntl |= RADEON_DAC_PDWN;
537 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
538 RADEON_DAC_PDWN_G |
539 RADEON_DAC_PDWN_B);
540 break;
541 }
542
543 /* handled in radeon_crtc_dpms() */
544 if (!(rdev->flags & RADEON_SINGLE_CRTC))
545 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
546 WREG32(RADEON_DAC_CNTL, dac_cntl);
547 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
548
549 if (rdev->is_atom_bios)
550 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
551 else
552 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
553
554}
555
556static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
557{
558 struct radeon_device *rdev = encoder->dev->dev_private;
559
560 if (rdev->is_atom_bios)
561 radeon_atom_output_lock(encoder, true);
562 else
563 radeon_combios_output_lock(encoder, true);
564 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
565}
566
567static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
568{
569 struct radeon_device *rdev = encoder->dev->dev_private;
570
571 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
572
573 if (rdev->is_atom_bios)
574 radeon_atom_output_lock(encoder, false);
575 else
576 radeon_combios_output_lock(encoder, false);
577}
578
579static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
580 struct drm_display_mode *mode,
581 struct drm_display_mode *adjusted_mode)
582{
583 struct drm_device *dev = encoder->dev;
584 struct radeon_device *rdev = dev->dev_private;
585 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
586 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
587 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
588
589 DRM_DEBUG_KMS("\n");
590
591 if (radeon_crtc->crtc_id == 0) {
592 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
593 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
594 ~(RADEON_DISP_DAC_SOURCE_MASK);
595 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
596 } else {
597 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
598 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
599 }
600 } else {
601 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
602 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
603 ~(RADEON_DISP_DAC_SOURCE_MASK);
604 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
605 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
606 } else {
607 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
608 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
609 }
610 }
611
612 dac_cntl = (RADEON_DAC_MASK_ALL |
613 RADEON_DAC_VGA_ADR_EN |
614 /* TODO 6-bits */
615 RADEON_DAC_8BIT_EN);
616
617 WREG32_P(RADEON_DAC_CNTL,
618 dac_cntl,
619 RADEON_DAC_RANGE_CNTL |
620 RADEON_DAC_BLANKING);
621
622 if (radeon_encoder->enc_priv) {
623 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
624 dac_macro_cntl = p_dac->ps2_pdac_adj;
625 } else
626 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
627 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
628 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
629
630 if (rdev->is_atom_bios)
631 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
632 else
633 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
634}
635
636static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
637 struct drm_connector *connector)
638{
639 struct drm_device *dev = encoder->dev;
640 struct radeon_device *rdev = dev->dev_private;
641 uint32_t vclk_ecp_cntl, crtc_ext_cntl;
642 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
643 enum drm_connector_status found = connector_status_disconnected;
644 bool color = true;
645
646 /* just don't bother on RN50 those chip are often connected to remoting
647 * console hw and often we get failure to load detect those. So to make
648 * everyone happy report the encoder as always connected.
649 */
650 if (ASIC_IS_RN50(rdev)) {
651 return connector_status_connected;
652 }
653
654 /* save the regs we need */
655 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
656 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
657 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
658 dac_cntl = RREG32(RADEON_DAC_CNTL);
659 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
660
661 tmp = vclk_ecp_cntl &
662 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
663 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
664
665 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
666 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
667
668 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
669 RADEON_DAC_FORCE_DATA_EN;
670
671 if (color)
672 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
673 else
674 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
675
676 if (ASIC_IS_R300(rdev))
677 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
678 else if (ASIC_IS_RV100(rdev))
679 tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT);
680 else
681 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
682
683 WREG32(RADEON_DAC_EXT_CNTL, tmp);
684
685 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
686 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
687 WREG32(RADEON_DAC_CNTL, tmp);
688
689 tmp = dac_macro_cntl;
690 tmp &= ~(RADEON_DAC_PDWN_R |
691 RADEON_DAC_PDWN_G |
692 RADEON_DAC_PDWN_B);
693
694 WREG32(RADEON_DAC_MACRO_CNTL, tmp);
695
696 mdelay(2);
697
698 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
699 found = connector_status_connected;
700
701 /* restore the regs we used */
702 WREG32(RADEON_DAC_CNTL, dac_cntl);
703 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
704 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
705 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
706 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
707
708 return found;
709}
710
711static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
712 .dpms = radeon_legacy_primary_dac_dpms,
713 .mode_fixup = radeon_legacy_mode_fixup,
714 .prepare = radeon_legacy_primary_dac_prepare,
715 .mode_set = radeon_legacy_primary_dac_mode_set,
716 .commit = radeon_legacy_primary_dac_commit,
717 .detect = radeon_legacy_primary_dac_detect,
718 .disable = radeon_legacy_encoder_disable,
719};
720
721
722static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
723 .destroy = radeon_enc_destroy,
724};
725
726static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
727{
728 struct drm_device *dev = encoder->dev;
729 struct radeon_device *rdev = dev->dev_private;
730 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
731 DRM_DEBUG_KMS("\n");
732
733 switch (mode) {
734 case DRM_MODE_DPMS_ON:
735 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
736 break;
737 case DRM_MODE_DPMS_STANDBY:
738 case DRM_MODE_DPMS_SUSPEND:
739 case DRM_MODE_DPMS_OFF:
740 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
741 break;
742 }
743
744 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
745
746 if (rdev->is_atom_bios)
747 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
748 else
749 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
750
751}
752
753static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
754{
755 struct radeon_device *rdev = encoder->dev->dev_private;
756
757 if (rdev->is_atom_bios)
758 radeon_atom_output_lock(encoder, true);
759 else
760 radeon_combios_output_lock(encoder, true);
761 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
762}
763
764static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
765{
766 struct radeon_device *rdev = encoder->dev->dev_private;
767
768 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
769
770 if (rdev->is_atom_bios)
771 radeon_atom_output_lock(encoder, true);
772 else
773 radeon_combios_output_lock(encoder, true);
774}
775
776static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
777 struct drm_display_mode *mode,
778 struct drm_display_mode *adjusted_mode)
779{
780 struct drm_device *dev = encoder->dev;
781 struct radeon_device *rdev = dev->dev_private;
782 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
783 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
784 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
785 int i;
786
787 DRM_DEBUG_KMS("\n");
788
789 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
790 tmp &= 0xfffff;
791 if (rdev->family == CHIP_RV280) {
792 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
793 tmp ^= (1 << 22);
794 tmds_pll_cntl ^= (1 << 22);
795 }
796
797 if (radeon_encoder->enc_priv) {
798 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
799
800 for (i = 0; i < 4; i++) {
801 if (tmds->tmds_pll[i].freq == 0)
802 break;
803 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
804 tmp = tmds->tmds_pll[i].value ;
805 break;
806 }
807 }
808 }
809
810 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
811 if (tmp & 0xfff00000)
812 tmds_pll_cntl = tmp;
813 else {
814 tmds_pll_cntl &= 0xfff00000;
815 tmds_pll_cntl |= tmp;
816 }
817 } else
818 tmds_pll_cntl = tmp;
819
820 tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
821 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
822
823 if (rdev->family == CHIP_R200 ||
824 rdev->family == CHIP_R100 ||
825 ASIC_IS_R300(rdev))
826 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
827 else /* RV chips got this bit reversed */
828 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
829
830 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
831 (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
832 RADEON_FP_CRTC_DONT_SHADOW_HEND));
833
834 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
835
836 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
837 RADEON_FP_DFP_SYNC_SEL |
838 RADEON_FP_CRT_SYNC_SEL |
839 RADEON_FP_CRTC_LOCK_8DOT |
840 RADEON_FP_USE_SHADOW_EN |
841 RADEON_FP_CRTC_USE_SHADOW_VEND |
842 RADEON_FP_CRT_SYNC_ALT);
843
844 if (1) /* FIXME rgbBits == 8 */
845 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
846 else
847 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
848
849 if (radeon_crtc->crtc_id == 0) {
850 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
851 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
852 if (radeon_encoder->rmx_type != RMX_OFF)
853 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
854 else
855 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
856 } else
857 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
858 } else {
859 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
860 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
861 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
862 } else
863 fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
864 }
865
866 WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
867 WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
868 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
869
870 if (rdev->is_atom_bios)
871 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
872 else
873 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
874}
875
876static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
877 .dpms = radeon_legacy_tmds_int_dpms,
878 .mode_fixup = radeon_legacy_mode_fixup,
879 .prepare = radeon_legacy_tmds_int_prepare,
880 .mode_set = radeon_legacy_tmds_int_mode_set,
881 .commit = radeon_legacy_tmds_int_commit,
882 .disable = radeon_legacy_encoder_disable,
883};
884
885
886static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
887 .destroy = radeon_enc_destroy,
888};
889
890static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
891{
892 struct drm_device *dev = encoder->dev;
893 struct radeon_device *rdev = dev->dev_private;
894 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
895 DRM_DEBUG_KMS("\n");
896
897 switch (mode) {
898 case DRM_MODE_DPMS_ON:
899 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
900 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
901 break;
902 case DRM_MODE_DPMS_STANDBY:
903 case DRM_MODE_DPMS_SUSPEND:
904 case DRM_MODE_DPMS_OFF:
905 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
906 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
907 break;
908 }
909
910 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
911
912 if (rdev->is_atom_bios)
913 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
914 else
915 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
916
917}
918
919static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
920{
921 struct radeon_device *rdev = encoder->dev->dev_private;
922
923 if (rdev->is_atom_bios)
924 radeon_atom_output_lock(encoder, true);
925 else
926 radeon_combios_output_lock(encoder, true);
927 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
928}
929
930static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
931{
932 struct radeon_device *rdev = encoder->dev->dev_private;
933 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
934
935 if (rdev->is_atom_bios)
936 radeon_atom_output_lock(encoder, false);
937 else
938 radeon_combios_output_lock(encoder, false);
939}
940
941static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
942 struct drm_display_mode *mode,
943 struct drm_display_mode *adjusted_mode)
944{
945 struct drm_device *dev = encoder->dev;
946 struct radeon_device *rdev = dev->dev_private;
947 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
948 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
949 uint32_t fp2_gen_cntl;
950
951 DRM_DEBUG_KMS("\n");
952
953 if (rdev->is_atom_bios) {
954 radeon_encoder->pixel_clock = adjusted_mode->clock;
955 atombios_dvo_setup(encoder, ATOM_ENABLE);
956 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
957 } else {
958 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
959
960 if (1) /* FIXME rgbBits == 8 */
961 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
962 else
963 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
964
965 fp2_gen_cntl &= ~(RADEON_FP2_ON |
966 RADEON_FP2_DVO_EN |
967 RADEON_FP2_DVO_RATE_SEL_SDR);
968
969 /* XXX: these are oem specific */
970 if (ASIC_IS_R300(rdev)) {
971 if ((dev->pdev->device == 0x4850) &&
972 (dev->pdev->subsystem_vendor == 0x1028) &&
973 (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
974 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
975 else
976 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
977
978 /*if (mode->clock > 165000)
979 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
980 }
981 if (!radeon_combios_external_tmds_setup(encoder))
982 radeon_external_tmds_setup(encoder);
983 }
984
985 if (radeon_crtc->crtc_id == 0) {
986 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
987 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
988 if (radeon_encoder->rmx_type != RMX_OFF)
989 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
990 else
991 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
992 } else
993 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
994 } else {
995 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
996 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
997 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
998 } else
999 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
1000 }
1001
1002 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1003
1004 if (rdev->is_atom_bios)
1005 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1006 else
1007 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1008}
1009
1010static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
1011{
1012 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1013 /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */
1014 kfree(radeon_encoder->enc_priv);
1015 drm_encoder_cleanup(encoder);
1016 kfree(radeon_encoder);
1017}
1018
1019static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
1020 .dpms = radeon_legacy_tmds_ext_dpms,
1021 .mode_fixup = radeon_legacy_mode_fixup,
1022 .prepare = radeon_legacy_tmds_ext_prepare,
1023 .mode_set = radeon_legacy_tmds_ext_mode_set,
1024 .commit = radeon_legacy_tmds_ext_commit,
1025 .disable = radeon_legacy_encoder_disable,
1026};
1027
1028
1029static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
1030 .destroy = radeon_ext_tmds_enc_destroy,
1031};
1032
1033static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
1034{
1035 struct drm_device *dev = encoder->dev;
1036 struct radeon_device *rdev = dev->dev_private;
1037 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1038 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1039 uint32_t tv_master_cntl = 0;
1040 bool is_tv;
1041 DRM_DEBUG_KMS("\n");
1042
1043 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1044
1045 if (rdev->family == CHIP_R200)
1046 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1047 else {
1048 if (is_tv)
1049 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1050 else
1051 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1052 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1053 }
1054
1055 switch (mode) {
1056 case DRM_MODE_DPMS_ON:
1057 if (rdev->family == CHIP_R200) {
1058 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1059 } else {
1060 if (is_tv)
1061 tv_master_cntl |= RADEON_TV_ON;
1062 else
1063 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1064
1065 if (rdev->family == CHIP_R420 ||
1066 rdev->family == CHIP_R423 ||
1067 rdev->family == CHIP_RV410)
1068 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
1069 R420_TV_DAC_GDACPD |
1070 R420_TV_DAC_BDACPD |
1071 RADEON_TV_DAC_BGSLEEP);
1072 else
1073 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
1074 RADEON_TV_DAC_GDACPD |
1075 RADEON_TV_DAC_BDACPD |
1076 RADEON_TV_DAC_BGSLEEP);
1077 }
1078 break;
1079 case DRM_MODE_DPMS_STANDBY:
1080 case DRM_MODE_DPMS_SUSPEND:
1081 case DRM_MODE_DPMS_OFF:
1082 if (rdev->family == CHIP_R200)
1083 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1084 else {
1085 if (is_tv)
1086 tv_master_cntl &= ~RADEON_TV_ON;
1087 else
1088 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1089
1090 if (rdev->family == CHIP_R420 ||
1091 rdev->family == CHIP_R423 ||
1092 rdev->family == CHIP_RV410)
1093 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
1094 R420_TV_DAC_GDACPD |
1095 R420_TV_DAC_BDACPD |
1096 RADEON_TV_DAC_BGSLEEP);
1097 else
1098 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
1099 RADEON_TV_DAC_GDACPD |
1100 RADEON_TV_DAC_BDACPD |
1101 RADEON_TV_DAC_BGSLEEP);
1102 }
1103 break;
1104 }
1105
1106 if (rdev->family == CHIP_R200) {
1107 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1108 } else {
1109 if (is_tv)
1110 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1111 /* handled in radeon_crtc_dpms() */
1112 else if (!(rdev->flags & RADEON_SINGLE_CRTC))
1113 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1114 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1115 }
1116
1117 if (rdev->is_atom_bios)
1118 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1119 else
1120 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1121
1122}
1123
1124static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1125{
1126 struct radeon_device *rdev = encoder->dev->dev_private;
1127
1128 if (rdev->is_atom_bios)
1129 radeon_atom_output_lock(encoder, true);
1130 else
1131 radeon_combios_output_lock(encoder, true);
1132 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1133}
1134
1135static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1136{
1137 struct radeon_device *rdev = encoder->dev->dev_private;
1138
1139 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1140
1141 if (rdev->is_atom_bios)
1142 radeon_atom_output_lock(encoder, true);
1143 else
1144 radeon_combios_output_lock(encoder, true);
1145}
1146
1147static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1148 struct drm_display_mode *mode,
1149 struct drm_display_mode *adjusted_mode)
1150{
1151 struct drm_device *dev = encoder->dev;
1152 struct radeon_device *rdev = dev->dev_private;
1153 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1154 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1155 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1156 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1157 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
1158 bool is_tv = false;
1159
1160 DRM_DEBUG_KMS("\n");
1161
1162 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1163
1164 if (rdev->family != CHIP_R200) {
1165 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1166 if (rdev->family == CHIP_R420 ||
1167 rdev->family == CHIP_R423 ||
1168 rdev->family == CHIP_RV410) {
1169 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1170 RADEON_TV_DAC_BGADJ_MASK |
1171 R420_TV_DAC_DACADJ_MASK |
1172 R420_TV_DAC_RDACPD |
1173 R420_TV_DAC_GDACPD |
1174 R420_TV_DAC_BDACPD |
1175 R420_TV_DAC_TVENABLE);
1176 } else {
1177 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1178 RADEON_TV_DAC_BGADJ_MASK |
1179 RADEON_TV_DAC_DACADJ_MASK |
1180 RADEON_TV_DAC_RDACPD |
1181 RADEON_TV_DAC_GDACPD |
1182 RADEON_TV_DAC_BDACPD);
1183 }
1184
1185 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
1186
1187 if (is_tv) {
1188 if (tv_dac->tv_std == TV_STD_NTSC ||
1189 tv_dac->tv_std == TV_STD_NTSC_J ||
1190 tv_dac->tv_std == TV_STD_PAL_M ||
1191 tv_dac->tv_std == TV_STD_PAL_60)
1192 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
1193 else
1194 tv_dac_cntl |= tv_dac->pal_tvdac_adj;
1195
1196 if (tv_dac->tv_std == TV_STD_NTSC ||
1197 tv_dac->tv_std == TV_STD_NTSC_J)
1198 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
1199 else
1200 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
1201 } else
1202 tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
1203 tv_dac->ps2_tvdac_adj);
1204
1205 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1206 }
1207
1208 if (ASIC_IS_R300(rdev)) {
1209 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
1210 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1211 } else if (rdev->family != CHIP_R200)
1212 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1213 else if (rdev->family == CHIP_R200)
1214 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1215
1216 if (rdev->family >= CHIP_R200)
1217 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1218
1219 if (is_tv) {
1220 uint32_t dac_cntl;
1221
1222 dac_cntl = RREG32(RADEON_DAC_CNTL);
1223 dac_cntl &= ~RADEON_DAC_TVO_EN;
1224 WREG32(RADEON_DAC_CNTL, dac_cntl);
1225
1226 if (ASIC_IS_R300(rdev))
1227 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
1228
1229 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
1230 if (radeon_crtc->crtc_id == 0) {
1231 if (ASIC_IS_R300(rdev)) {
1232 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1233 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
1234 RADEON_DISP_TV_SOURCE_CRTC);
1235 }
1236 if (rdev->family >= CHIP_R200) {
1237 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
1238 } else {
1239 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1240 }
1241 } else {
1242 if (ASIC_IS_R300(rdev)) {
1243 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1244 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
1245 }
1246 if (rdev->family >= CHIP_R200) {
1247 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
1248 } else {
1249 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1250 }
1251 }
1252 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1253 } else {
1254
1255 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1256
1257 if (radeon_crtc->crtc_id == 0) {
1258 if (ASIC_IS_R300(rdev)) {
1259 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1260 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1261 } else if (rdev->family == CHIP_R200) {
1262 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1263 RADEON_FP2_DVO_RATE_SEL_SDR);
1264 } else
1265 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1266 } else {
1267 if (ASIC_IS_R300(rdev)) {
1268 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1269 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1270 } else if (rdev->family == CHIP_R200) {
1271 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1272 RADEON_FP2_DVO_RATE_SEL_SDR);
1273 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1274 } else
1275 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1276 }
1277 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1278 }
1279
1280 if (ASIC_IS_R300(rdev)) {
1281 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1282 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1283 } else if (rdev->family != CHIP_R200)
1284 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1285 else if (rdev->family == CHIP_R200)
1286 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1287
1288 if (rdev->family >= CHIP_R200)
1289 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1290
1291 if (is_tv)
1292 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1293
1294 if (rdev->is_atom_bios)
1295 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1296 else
1297 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1298
1299}
1300
1301static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1302 struct drm_connector *connector)
1303{
1304 struct drm_device *dev = encoder->dev;
1305 struct radeon_device *rdev = dev->dev_private;
1306 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1307 uint32_t disp_output_cntl, gpiopad_a, tmp;
1308 bool found = false;
1309
1310 /* save regs needed */
1311 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1312 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1313 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1314 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1315 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1316 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1317
1318 WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1319
1320 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1321
1322 WREG32(RADEON_CRTC2_GEN_CNTL,
1323 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1324
1325 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1326 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1327 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1328
1329 WREG32(RADEON_DAC_EXT_CNTL,
1330 RADEON_DAC2_FORCE_BLANK_OFF_EN |
1331 RADEON_DAC2_FORCE_DATA_EN |
1332 RADEON_DAC_FORCE_DATA_SEL_RGB |
1333 (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1334
1335 WREG32(RADEON_TV_DAC_CNTL,
1336 RADEON_TV_DAC_STD_NTSC |
1337 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1338 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1339
1340 RREG32(RADEON_TV_DAC_CNTL);
1341 mdelay(4);
1342
1343 WREG32(RADEON_TV_DAC_CNTL,
1344 RADEON_TV_DAC_NBLANK |
1345 RADEON_TV_DAC_NHOLD |
1346 RADEON_TV_MONITOR_DETECT_EN |
1347 RADEON_TV_DAC_STD_NTSC |
1348 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1349 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1350
1351 RREG32(RADEON_TV_DAC_CNTL);
1352 mdelay(6);
1353
1354 tmp = RREG32(RADEON_TV_DAC_CNTL);
1355 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1356 found = true;
1357 DRM_DEBUG_KMS("S-video TV connection detected\n");
1358 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1359 found = true;
1360 DRM_DEBUG_KMS("Composite TV connection detected\n");
1361 }
1362
1363 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1364 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1365 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1366 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1367 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1368 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1369 return found;
1370}
1371
1372static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1373 struct drm_connector *connector)
1374{
1375 struct drm_device *dev = encoder->dev;
1376 struct radeon_device *rdev = dev->dev_private;
1377 uint32_t tv_dac_cntl, dac_cntl2;
1378 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1379 bool found = false;
1380
1381 if (ASIC_IS_R300(rdev))
1382 return r300_legacy_tv_detect(encoder, connector);
1383
1384 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1385 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1386 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1387 config_cntl = RREG32(RADEON_CONFIG_CNTL);
1388 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1389
1390 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1391 WREG32(RADEON_DAC_CNTL2, tmp);
1392
1393 tmp = tv_master_cntl | RADEON_TV_ON;
1394 tmp &= ~(RADEON_TV_ASYNC_RST |
1395 RADEON_RESTART_PHASE_FIX |
1396 RADEON_CRT_FIFO_CE_EN |
1397 RADEON_TV_FIFO_CE_EN |
1398 RADEON_RE_SYNC_NOW_SEL_MASK);
1399 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1400 WREG32(RADEON_TV_MASTER_CNTL, tmp);
1401
1402 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1403 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1404 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1405
1406 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1407 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1408 else
1409 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1410 WREG32(RADEON_TV_DAC_CNTL, tmp);
1411
1412 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1413 RADEON_RED_MX_FORCE_DAC_DATA |
1414 RADEON_GRN_MX_FORCE_DAC_DATA |
1415 RADEON_BLU_MX_FORCE_DAC_DATA |
1416 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1417 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1418
1419 mdelay(3);
1420 tmp = RREG32(RADEON_TV_DAC_CNTL);
1421 if (tmp & RADEON_TV_DAC_GDACDET) {
1422 found = true;
1423 DRM_DEBUG_KMS("S-video TV connection detected\n");
1424 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1425 found = true;
1426 DRM_DEBUG_KMS("Composite TV connection detected\n");
1427 }
1428
1429 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1430 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1431 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1432 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1433 return found;
1434}
1435
1436static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder,
1437 struct drm_connector *connector)
1438{
1439 struct drm_device *dev = encoder->dev;
1440 struct radeon_device *rdev = dev->dev_private;
1441 uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl;
1442 uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c;
1443 uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f;
1444 uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp;
1445 uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid;
1446 bool found = false;
1447 int i;
1448
1449 /* save the regs we need */
1450 gpio_monid = RREG32(RADEON_GPIO_MONID);
1451 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1452 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1453 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1454 disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A);
1455 disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B);
1456 disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C);
1457 disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D);
1458 disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E);
1459 disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F);
1460 crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP);
1461 crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP);
1462 crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID);
1463 crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID);
1464
1465 tmp = RREG32(RADEON_GPIO_MONID);
1466 tmp &= ~RADEON_GPIO_A_0;
1467 WREG32(RADEON_GPIO_MONID, tmp);
1468
1469 WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON |
1470 RADEON_FP2_PANEL_FORMAT |
1471 R200_FP2_SOURCE_SEL_TRANS_UNIT |
1472 RADEON_FP2_DVO_EN |
1473 R200_FP2_DVO_RATE_SEL_SDR));
1474
1475 WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX |
1476 RADEON_DISP_TRANS_MATRIX_GRAPHICS));
1477
1478 WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN |
1479 RADEON_CRTC2_DISP_REQ_EN_B));
1480
1481 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);
1482 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);
1483 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);
1484 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);
1485 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);
1486 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);
1487
1488 WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);
1489 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);
1490 WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);
1491 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);
1492
1493 for (i = 0; i < 200; i++) {
1494 tmp = RREG32(RADEON_GPIO_MONID);
1495 if (tmp & RADEON_GPIO_Y_0)
1496 found = true;
1497
1498 if (found)
1499 break;
1500
1501 if (!drm_can_sleep())
1502 mdelay(1);
1503 else
1504 msleep(1);
1505 }
1506
1507 /* restore the regs we used */
1508 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a);
1509 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b);
1510 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c);
1511 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d);
1512 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e);
1513 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f);
1514 WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp);
1515 WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp);
1516 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
1517 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
1518 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1519 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1520 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1521 WREG32(RADEON_GPIO_MONID, gpio_monid);
1522
1523 return found;
1524}
1525
1526static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1527 struct drm_connector *connector)
1528{
1529 struct drm_device *dev = encoder->dev;
1530 struct radeon_device *rdev = dev->dev_private;
1531 uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1532 uint32_t gpiopad_a = 0, pixclks_cntl, tmp;
1533 uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0;
1534 enum drm_connector_status found = connector_status_disconnected;
1535 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1536 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1537 bool color = true;
1538 struct drm_crtc *crtc;
1539
1540 /* find out if crtc2 is in use or if this encoder is using it */
1541 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1542 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1543 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1544 if (encoder->crtc != crtc) {
1545 return connector_status_disconnected;
1546 }
1547 }
1548 }
1549
1550 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1551 connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1552 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1553 bool tv_detect;
1554
1555 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1556 return connector_status_disconnected;
1557
1558 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1559 if (tv_detect && tv_dac)
1560 found = connector_status_connected;
1561 return found;
1562 }
1563
1564 /* don't probe if the encoder is being used for something else not CRT related */
1565 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1566 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1567 return connector_status_disconnected;
1568 }
1569
1570 /* R200 uses an external DAC for secondary DAC */
1571 if (rdev->family == CHIP_R200) {
1572 if (radeon_legacy_ext_dac_detect(encoder, connector))
1573 found = connector_status_connected;
1574 return found;
1575 }
1576
1577 /* save the regs we need */
1578 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1579
1580 if (rdev->flags & RADEON_SINGLE_CRTC) {
1581 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
1582 } else {
1583 if (ASIC_IS_R300(rdev)) {
1584 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1585 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1586 } else {
1587 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1588 }
1589 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1590 }
1591 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1592 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1593 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1594
1595 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1596 | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1597 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1598
1599 if (rdev->flags & RADEON_SINGLE_CRTC) {
1600 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
1601 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
1602 } else {
1603 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1604 tmp |= RADEON_CRTC2_CRT2_ON |
1605 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1606 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1607
1608 if (ASIC_IS_R300(rdev)) {
1609 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1610 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1611 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1612 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1613 } else {
1614 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1615 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1616 }
1617 }
1618
1619 tmp = RADEON_TV_DAC_NBLANK |
1620 RADEON_TV_DAC_NHOLD |
1621 RADEON_TV_MONITOR_DETECT_EN |
1622 RADEON_TV_DAC_STD_PS2;
1623
1624 WREG32(RADEON_TV_DAC_CNTL, tmp);
1625
1626 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1627 RADEON_DAC2_FORCE_DATA_EN;
1628
1629 if (color)
1630 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1631 else
1632 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1633
1634 if (ASIC_IS_R300(rdev))
1635 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1636 else
1637 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1638
1639 WREG32(RADEON_DAC_EXT_CNTL, tmp);
1640
1641 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1642 WREG32(RADEON_DAC_CNTL2, tmp);
1643
1644 mdelay(10);
1645
1646 if (ASIC_IS_R300(rdev)) {
1647 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1648 found = connector_status_connected;
1649 } else {
1650 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1651 found = connector_status_connected;
1652 }
1653
1654 /* restore regs we used */
1655 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1656 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1657 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1658
1659 if (rdev->flags & RADEON_SINGLE_CRTC) {
1660 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
1661 } else {
1662 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1663 if (ASIC_IS_R300(rdev)) {
1664 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1665 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1666 } else {
1667 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1668 }
1669 }
1670
1671 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1672
1673 return found;
1674
1675}
1676
1677static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1678 .dpms = radeon_legacy_tv_dac_dpms,
1679 .mode_fixup = radeon_legacy_mode_fixup,
1680 .prepare = radeon_legacy_tv_dac_prepare,
1681 .mode_set = radeon_legacy_tv_dac_mode_set,
1682 .commit = radeon_legacy_tv_dac_commit,
1683 .detect = radeon_legacy_tv_dac_detect,
1684 .disable = radeon_legacy_encoder_disable,
1685};
1686
1687
1688static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1689 .destroy = radeon_enc_destroy,
1690};
1691
1692
1693static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1694{
1695 struct drm_device *dev = encoder->base.dev;
1696 struct radeon_device *rdev = dev->dev_private;
1697 struct radeon_encoder_int_tmds *tmds = NULL;
1698 bool ret;
1699
1700 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1701
1702 if (!tmds)
1703 return NULL;
1704
1705 if (rdev->is_atom_bios)
1706 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1707 else
1708 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1709
1710 if (ret == false)
1711 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1712
1713 return tmds;
1714}
1715
1716static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1717{
1718 struct drm_device *dev = encoder->base.dev;
1719 struct radeon_device *rdev = dev->dev_private;
1720 struct radeon_encoder_ext_tmds *tmds = NULL;
1721 bool ret;
1722
1723 if (rdev->is_atom_bios)
1724 return NULL;
1725
1726 tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1727
1728 if (!tmds)
1729 return NULL;
1730
1731 ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1732
1733 if (ret == false)
1734 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1735
1736 return tmds;
1737}
1738
1739void
1740radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1741{
1742 struct radeon_device *rdev = dev->dev_private;
1743 struct drm_encoder *encoder;
1744 struct radeon_encoder *radeon_encoder;
1745
1746 /* see if we already added it */
1747 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1748 radeon_encoder = to_radeon_encoder(encoder);
1749 if (radeon_encoder->encoder_enum == encoder_enum) {
1750 radeon_encoder->devices |= supported_device;
1751 return;
1752 }
1753
1754 }
1755
1756 /* add a new one */
1757 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1758 if (!radeon_encoder)
1759 return;
1760
1761 encoder = &radeon_encoder->base;
1762 if (rdev->flags & RADEON_SINGLE_CRTC)
1763 encoder->possible_crtcs = 0x1;
1764 else
1765 encoder->possible_crtcs = 0x3;
1766
1767 radeon_encoder->enc_priv = NULL;
1768
1769 radeon_encoder->encoder_enum = encoder_enum;
1770 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1771 radeon_encoder->devices = supported_device;
1772 radeon_encoder->rmx_type = RMX_OFF;
1773
1774 switch (radeon_encoder->encoder_id) {
1775 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1776 encoder->possible_crtcs = 0x1;
1777 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs,
1778 DRM_MODE_ENCODER_LVDS, NULL);
1779 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1780 if (rdev->is_atom_bios)
1781 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1782 else
1783 radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1784 radeon_encoder->rmx_type = RMX_FULL;
1785 break;
1786 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1787 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs,
1788 DRM_MODE_ENCODER_TMDS, NULL);
1789 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1790 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1791 break;
1792 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1793 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs,
1794 DRM_MODE_ENCODER_DAC, NULL);
1795 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1796 if (rdev->is_atom_bios)
1797 radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1798 else
1799 radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1800 break;
1801 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1802 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs,
1803 DRM_MODE_ENCODER_TVDAC, NULL);
1804 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1805 if (rdev->is_atom_bios)
1806 radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1807 else
1808 radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1809 break;
1810 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1811 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs,
1812 DRM_MODE_ENCODER_TMDS, NULL);
1813 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1814 if (!rdev->is_atom_bios)
1815 radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1816 break;
1817 }
1818}
1819