1 | /* |
2 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
3 | * VA Linux Systems Inc., Fremont, California. |
4 | * Copyright 2008 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Original Authors: |
25 | * Kevin E. Martin, Rickard E. Faith, Alan Hourihane |
26 | * |
27 | * Kernel port Author: Dave Airlie |
28 | */ |
29 | |
30 | #ifndef RADEON_MODE_H |
31 | #define RADEON_MODE_H |
32 | |
33 | #include <drm/drm_crtc.h> |
34 | #include <drm/drm_edid.h> |
35 | #include <drm/drm_encoder.h> |
36 | #include <drm/drm_dp_helper.h> |
37 | #include <drm/drm_dp_mst_helper.h> |
38 | #include <drm/drm_fixed.h> |
39 | #include <drm/drm_crtc_helper.h> |
40 | #include <linux/i2c.h> |
41 | #include <linux/i2c-algo-bit.h> |
42 | |
43 | struct radeon_bo; |
44 | struct radeon_device; |
45 | |
46 | #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) |
47 | #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) |
48 | #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) |
49 | |
50 | #define RADEON_MAX_HPD_PINS 7 |
51 | #define RADEON_MAX_CRTCS 6 |
52 | #define RADEON_MAX_AFMT_BLOCKS 7 |
53 | |
54 | enum radeon_rmx_type { |
55 | RMX_OFF, |
56 | RMX_FULL, |
57 | RMX_CENTER, |
58 | RMX_ASPECT |
59 | }; |
60 | |
61 | enum radeon_tv_std { |
62 | TV_STD_NTSC, |
63 | TV_STD_PAL, |
64 | TV_STD_PAL_M, |
65 | TV_STD_PAL_60, |
66 | TV_STD_NTSC_J, |
67 | TV_STD_SCART_PAL, |
68 | TV_STD_SECAM, |
69 | TV_STD_PAL_CN, |
70 | TV_STD_PAL_N, |
71 | }; |
72 | |
73 | enum radeon_underscan_type { |
74 | UNDERSCAN_OFF, |
75 | UNDERSCAN_ON, |
76 | UNDERSCAN_AUTO, |
77 | }; |
78 | |
79 | enum radeon_hpd_id { |
80 | RADEON_HPD_1 = 0, |
81 | RADEON_HPD_2, |
82 | RADEON_HPD_3, |
83 | RADEON_HPD_4, |
84 | RADEON_HPD_5, |
85 | RADEON_HPD_6, |
86 | RADEON_HPD_NONE = 0xff, |
87 | }; |
88 | |
89 | enum radeon_output_csc { |
90 | RADEON_OUTPUT_CSC_BYPASS = 0, |
91 | RADEON_OUTPUT_CSC_TVRGB = 1, |
92 | RADEON_OUTPUT_CSC_YCBCR601 = 2, |
93 | RADEON_OUTPUT_CSC_YCBCR709 = 3, |
94 | }; |
95 | |
96 | #define RADEON_MAX_I2C_BUS 16 |
97 | |
98 | /* radeon gpio-based i2c |
99 | * 1. "mask" reg and bits |
100 | * grabs the gpio pins for software use |
101 | * 0=not held 1=held |
102 | * 2. "a" reg and bits |
103 | * output pin value |
104 | * 0=low 1=high |
105 | * 3. "en" reg and bits |
106 | * sets the pin direction |
107 | * 0=input 1=output |
108 | * 4. "y" reg and bits |
109 | * input pin value |
110 | * 0=low 1=high |
111 | */ |
112 | struct radeon_i2c_bus_rec { |
113 | bool valid; |
114 | /* id used by atom */ |
115 | uint8_t i2c_id; |
116 | /* id used by atom */ |
117 | enum radeon_hpd_id hpd; |
118 | /* can be used with hw i2c engine */ |
119 | bool hw_capable; |
120 | /* uses multi-media i2c engine */ |
121 | bool mm_i2c; |
122 | /* regs and bits */ |
123 | uint32_t mask_clk_reg; |
124 | uint32_t mask_data_reg; |
125 | uint32_t a_clk_reg; |
126 | uint32_t a_data_reg; |
127 | uint32_t en_clk_reg; |
128 | uint32_t en_data_reg; |
129 | uint32_t y_clk_reg; |
130 | uint32_t y_data_reg; |
131 | uint32_t mask_clk_mask; |
132 | uint32_t mask_data_mask; |
133 | uint32_t a_clk_mask; |
134 | uint32_t a_data_mask; |
135 | uint32_t en_clk_mask; |
136 | uint32_t en_data_mask; |
137 | uint32_t y_clk_mask; |
138 | uint32_t y_data_mask; |
139 | }; |
140 | |
141 | struct radeon_tmds_pll { |
142 | uint32_t freq; |
143 | uint32_t value; |
144 | }; |
145 | |
146 | #define RADEON_MAX_BIOS_CONNECTOR 16 |
147 | |
148 | /* pll flags */ |
149 | #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) |
150 | #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) |
151 | #define RADEON_PLL_USE_REF_DIV (1 << 2) |
152 | #define RADEON_PLL_LEGACY (1 << 3) |
153 | #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) |
154 | #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) |
155 | #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) |
156 | #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) |
157 | #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) |
158 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) |
159 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) |
160 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
161 | #define RADEON_PLL_USE_POST_DIV (1 << 12) |
162 | #define RADEON_PLL_IS_LCD (1 << 13) |
163 | #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) |
164 | |
165 | struct radeon_pll { |
166 | /* reference frequency */ |
167 | uint32_t reference_freq; |
168 | |
169 | /* fixed dividers */ |
170 | uint32_t reference_div; |
171 | uint32_t post_div; |
172 | |
173 | /* pll in/out limits */ |
174 | uint32_t pll_in_min; |
175 | uint32_t pll_in_max; |
176 | uint32_t pll_out_min; |
177 | uint32_t pll_out_max; |
178 | uint32_t lcd_pll_out_min; |
179 | uint32_t lcd_pll_out_max; |
180 | uint32_t best_vco; |
181 | |
182 | /* divider limits */ |
183 | uint32_t min_ref_div; |
184 | uint32_t max_ref_div; |
185 | uint32_t min_post_div; |
186 | uint32_t max_post_div; |
187 | uint32_t min_feedback_div; |
188 | uint32_t max_feedback_div; |
189 | uint32_t min_frac_feedback_div; |
190 | uint32_t max_frac_feedback_div; |
191 | |
192 | /* flags for the current clock */ |
193 | uint32_t flags; |
194 | |
195 | /* pll id */ |
196 | uint32_t id; |
197 | }; |
198 | |
199 | struct radeon_i2c_chan { |
200 | struct i2c_adapter adapter; |
201 | struct drm_device *dev; |
202 | struct i2c_algo_bit_data bit; |
203 | struct radeon_i2c_bus_rec rec; |
204 | struct drm_dp_aux aux; |
205 | bool has_aux; |
206 | struct mutex mutex; |
207 | }; |
208 | |
209 | /* mostly for macs, but really any system without connector tables */ |
210 | enum radeon_connector_table { |
211 | CT_NONE = 0, |
212 | CT_GENERIC, |
213 | CT_IBOOK, |
214 | CT_POWERBOOK_EXTERNAL, |
215 | CT_POWERBOOK_INTERNAL, |
216 | CT_POWERBOOK_VGA, |
217 | CT_MINI_EXTERNAL, |
218 | CT_MINI_INTERNAL, |
219 | CT_IMAC_G5_ISIGHT, |
220 | CT_EMAC, |
221 | CT_RN50_POWER, |
222 | CT_MAC_X800, |
223 | CT_MAC_G5_9600, |
224 | CT_SAM440EP, |
225 | CT_MAC_G4_SILVER |
226 | }; |
227 | |
228 | enum radeon_dvo_chip { |
229 | DVO_SIL164, |
230 | DVO_SIL1178, |
231 | }; |
232 | |
233 | struct radeon_fbdev; |
234 | |
235 | struct radeon_afmt { |
236 | bool enabled; |
237 | int offset; |
238 | bool last_buffer_filled_status; |
239 | int id; |
240 | }; |
241 | |
242 | struct radeon_mode_info { |
243 | struct atom_context *atom_context; |
244 | struct card_info *atom_card_info; |
245 | enum radeon_connector_table connector_table; |
246 | bool mode_config_initialized; |
247 | struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; |
248 | struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; |
249 | /* DVI-I properties */ |
250 | struct drm_property *coherent_mode_property; |
251 | /* DAC enable load detect */ |
252 | struct drm_property *load_detect_property; |
253 | /* TV standard */ |
254 | struct drm_property *tv_std_property; |
255 | /* legacy TMDS PLL detect */ |
256 | struct drm_property *tmds_pll_property; |
257 | /* underscan */ |
258 | struct drm_property *underscan_property; |
259 | struct drm_property *underscan_hborder_property; |
260 | struct drm_property *underscan_vborder_property; |
261 | /* audio */ |
262 | struct drm_property *audio_property; |
263 | /* FMT dithering */ |
264 | struct drm_property *dither_property; |
265 | /* Output CSC */ |
266 | struct drm_property *output_csc_property; |
267 | /* hardcoded DFP edid from BIOS */ |
268 | struct edid *bios_hardcoded_edid; |
269 | int bios_hardcoded_edid_size; |
270 | |
271 | /* pointer to fbdev info structure */ |
272 | struct radeon_fbdev *rfbdev; |
273 | /* firmware flags */ |
274 | u16 firmware_flags; |
275 | /* pointer to backlight encoder */ |
276 | struct radeon_encoder *bl_encoder; |
277 | |
278 | /* bitmask for active encoder frontends */ |
279 | uint32_t active_encoders; |
280 | }; |
281 | |
282 | #define RADEON_MAX_BL_LEVEL 0xFF |
283 | |
284 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) |
285 | |
286 | struct radeon_backlight_privdata { |
287 | struct radeon_encoder *encoder; |
288 | uint8_t negative; |
289 | }; |
290 | |
291 | #endif |
292 | |
293 | #define MAX_H_CODE_TIMING_LEN 32 |
294 | #define MAX_V_CODE_TIMING_LEN 32 |
295 | |
296 | /* need to store these as reading |
297 | back code tables is excessive */ |
298 | struct radeon_tv_regs { |
299 | uint32_t tv_uv_adr; |
300 | uint32_t timing_cntl; |
301 | uint32_t hrestart; |
302 | uint32_t vrestart; |
303 | uint32_t frestart; |
304 | uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; |
305 | uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; |
306 | }; |
307 | |
308 | struct radeon_atom_ss { |
309 | uint16_t percentage; |
310 | uint16_t percentage_divider; |
311 | uint8_t type; |
312 | uint16_t step; |
313 | uint8_t delay; |
314 | uint8_t range; |
315 | uint8_t refdiv; |
316 | /* asic_ss */ |
317 | uint16_t rate; |
318 | uint16_t amount; |
319 | }; |
320 | |
321 | enum radeon_flip_status { |
322 | RADEON_FLIP_NONE, |
323 | RADEON_FLIP_PENDING, |
324 | RADEON_FLIP_SUBMITTED |
325 | }; |
326 | |
327 | struct radeon_crtc { |
328 | struct drm_crtc base; |
329 | int crtc_id; |
330 | u16 lut_r[256], lut_g[256], lut_b[256]; |
331 | bool enabled; |
332 | bool can_tile; |
333 | bool cursor_out_of_bounds; |
334 | uint32_t crtc_offset; |
335 | struct drm_gem_object *cursor_bo; |
336 | uint64_t cursor_addr; |
337 | int cursor_x; |
338 | int cursor_y; |
339 | int cursor_hot_x; |
340 | int cursor_hot_y; |
341 | int cursor_width; |
342 | int cursor_height; |
343 | int max_cursor_width; |
344 | int max_cursor_height; |
345 | uint32_t legacy_display_base_addr; |
346 | enum radeon_rmx_type rmx_type; |
347 | u8 h_border; |
348 | u8 v_border; |
349 | fixed20_12 vsc; |
350 | fixed20_12 hsc; |
351 | struct drm_display_mode native_mode; |
352 | int pll_id; |
353 | /* page flipping */ |
354 | struct workqueue_struct *flip_queue; |
355 | struct radeon_flip_work *flip_work; |
356 | enum radeon_flip_status flip_status; |
357 | /* pll sharing */ |
358 | struct radeon_atom_ss ss; |
359 | bool ss_enabled; |
360 | u32 adjusted_clock; |
361 | int bpc; |
362 | u32 pll_reference_div; |
363 | u32 pll_post_div; |
364 | u32 pll_flags; |
365 | struct drm_encoder *encoder; |
366 | struct drm_connector *connector; |
367 | /* for dpm */ |
368 | u32 line_time; |
369 | u32 wm_low; |
370 | u32 wm_high; |
371 | u32 lb_vblank_lead_lines; |
372 | struct drm_display_mode hw_mode; |
373 | enum radeon_output_csc output_csc; |
374 | }; |
375 | |
376 | struct radeon_encoder_primary_dac { |
377 | /* legacy primary dac */ |
378 | uint32_t ps2_pdac_adj; |
379 | }; |
380 | |
381 | struct radeon_encoder_lvds { |
382 | /* legacy lvds */ |
383 | uint16_t panel_vcc_delay; |
384 | uint8_t panel_pwr_delay; |
385 | uint8_t panel_digon_delay; |
386 | uint8_t panel_blon_delay; |
387 | uint16_t panel_ref_divider; |
388 | uint8_t panel_post_divider; |
389 | uint16_t panel_fb_divider; |
390 | bool use_bios_dividers; |
391 | uint32_t lvds_gen_cntl; |
392 | /* panel mode */ |
393 | struct drm_display_mode native_mode; |
394 | struct backlight_device *bl_dev; |
395 | int dpms_mode; |
396 | uint8_t backlight_level; |
397 | }; |
398 | |
399 | struct radeon_encoder_tv_dac { |
400 | /* legacy tv dac */ |
401 | uint32_t ps2_tvdac_adj; |
402 | uint32_t ntsc_tvdac_adj; |
403 | uint32_t pal_tvdac_adj; |
404 | |
405 | int h_pos; |
406 | int v_pos; |
407 | int h_size; |
408 | int supported_tv_stds; |
409 | bool tv_on; |
410 | enum radeon_tv_std tv_std; |
411 | struct radeon_tv_regs tv; |
412 | }; |
413 | |
414 | struct radeon_encoder_int_tmds { |
415 | /* legacy int tmds */ |
416 | struct radeon_tmds_pll tmds_pll[4]; |
417 | }; |
418 | |
419 | struct radeon_encoder_ext_tmds { |
420 | /* tmds over dvo */ |
421 | struct radeon_i2c_chan *i2c_bus; |
422 | uint8_t slave_addr; |
423 | enum radeon_dvo_chip dvo_chip; |
424 | }; |
425 | |
426 | /* spread spectrum */ |
427 | struct radeon_encoder_atom_dig { |
428 | bool linkb; |
429 | /* atom dig */ |
430 | bool coherent_mode; |
431 | int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ |
432 | /* atom lvds/edp */ |
433 | uint32_t lcd_misc; |
434 | uint16_t panel_pwr_delay; |
435 | uint32_t lcd_ss_id; |
436 | /* panel mode */ |
437 | struct drm_display_mode native_mode; |
438 | struct backlight_device *bl_dev; |
439 | int dpms_mode; |
440 | uint8_t backlight_level; |
441 | int panel_mode; |
442 | struct radeon_afmt *afmt; |
443 | struct r600_audio_pin *pin; |
444 | int active_mst_links; |
445 | }; |
446 | |
447 | struct radeon_encoder_atom_dac { |
448 | enum radeon_tv_std tv_std; |
449 | }; |
450 | |
451 | struct radeon_encoder_mst { |
452 | int crtc; |
453 | struct radeon_encoder *primary; |
454 | struct radeon_connector *connector; |
455 | struct drm_dp_mst_port *port; |
456 | int pbn; |
457 | int fe; |
458 | bool fe_from_be; |
459 | bool enc_active; |
460 | }; |
461 | |
462 | struct radeon_encoder { |
463 | struct drm_encoder base; |
464 | uint32_t encoder_enum; |
465 | uint32_t encoder_id; |
466 | uint32_t devices; |
467 | uint32_t active_device; |
468 | uint32_t flags; |
469 | uint32_t pixel_clock; |
470 | enum radeon_rmx_type rmx_type; |
471 | enum radeon_underscan_type underscan_type; |
472 | uint32_t underscan_hborder; |
473 | uint32_t underscan_vborder; |
474 | struct drm_display_mode native_mode; |
475 | void *enc_priv; |
476 | int audio_polling_active; |
477 | bool is_ext_encoder; |
478 | u16 caps; |
479 | struct radeon_audio_funcs *audio; |
480 | enum radeon_output_csc output_csc; |
481 | bool can_mst; |
482 | uint32_t offset; |
483 | bool is_mst_encoder; |
484 | /* front end for this mst encoder */ |
485 | }; |
486 | |
487 | struct radeon_connector_atom_dig { |
488 | uint32_t igp_lane_info; |
489 | /* displayport */ |
490 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
491 | u8 dp_sink_type; |
492 | int dp_clock; |
493 | int dp_lane_count; |
494 | bool edp_on; |
495 | bool is_mst; |
496 | }; |
497 | |
498 | struct radeon_gpio_rec { |
499 | bool valid; |
500 | u8 id; |
501 | u32 reg; |
502 | u32 mask; |
503 | u32 shift; |
504 | }; |
505 | |
506 | struct radeon_hpd { |
507 | enum radeon_hpd_id hpd; |
508 | u8 plugged_state; |
509 | struct radeon_gpio_rec gpio; |
510 | }; |
511 | |
512 | struct radeon_router { |
513 | u32 router_id; |
514 | struct radeon_i2c_bus_rec i2c_info; |
515 | u8 i2c_addr; |
516 | /* i2c mux */ |
517 | bool ddc_valid; |
518 | u8 ddc_mux_type; |
519 | u8 ddc_mux_control_pin; |
520 | u8 ddc_mux_state; |
521 | /* clock/data mux */ |
522 | bool cd_valid; |
523 | u8 cd_mux_type; |
524 | u8 cd_mux_control_pin; |
525 | u8 cd_mux_state; |
526 | }; |
527 | |
528 | enum radeon_connector_audio { |
529 | RADEON_AUDIO_DISABLE = 0, |
530 | RADEON_AUDIO_ENABLE = 1, |
531 | RADEON_AUDIO_AUTO = 2 |
532 | }; |
533 | |
534 | enum radeon_connector_dither { |
535 | RADEON_FMT_DITHER_DISABLE = 0, |
536 | RADEON_FMT_DITHER_ENABLE = 1, |
537 | }; |
538 | |
539 | struct stream_attribs { |
540 | uint16_t fe; |
541 | uint16_t slots; |
542 | }; |
543 | |
544 | struct radeon_connector { |
545 | struct drm_connector base; |
546 | uint32_t connector_id; |
547 | uint32_t devices; |
548 | struct radeon_i2c_chan *ddc_bus; |
549 | /* some systems have an hdmi and vga port with a shared ddc line */ |
550 | bool shared_ddc; |
551 | bool use_digital; |
552 | /* we need to mind the EDID between detect |
553 | and get modes due to analog/digital/tvencoder */ |
554 | struct edid *edid; |
555 | void *con_priv; |
556 | bool dac_load_detect; |
557 | bool detected_by_load; /* if the connection status was determined by load */ |
558 | bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */ |
559 | uint16_t connector_object_id; |
560 | struct radeon_hpd hpd; |
561 | struct radeon_router router; |
562 | struct radeon_i2c_chan *router_bus; |
563 | enum radeon_connector_audio audio; |
564 | enum radeon_connector_dither dither; |
565 | int pixelclock_for_modeset; |
566 | bool is_mst_connector; |
567 | struct radeon_connector *mst_port; |
568 | struct drm_dp_mst_port *port; |
569 | struct drm_dp_mst_topology_mgr mst_mgr; |
570 | |
571 | struct radeon_encoder *mst_encoder; |
572 | struct stream_attribs cur_stream_attribs[6]; |
573 | int enabled_attribs; |
574 | }; |
575 | |
576 | #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ |
577 | ((em) == ATOM_ENCODER_MODE_DP_MST)) |
578 | |
579 | struct atom_clock_dividers { |
580 | u32 post_div; |
581 | union { |
582 | struct { |
583 | #ifdef __BIG_ENDIAN |
584 | u32 reserved : 6; |
585 | u32 whole_fb_div : 12; |
586 | u32 frac_fb_div : 14; |
587 | #else |
588 | u32 frac_fb_div : 14; |
589 | u32 whole_fb_div : 12; |
590 | u32 reserved : 6; |
591 | #endif |
592 | }; |
593 | u32 fb_div; |
594 | }; |
595 | u32 ref_div; |
596 | bool enable_post_div; |
597 | bool enable_dithen; |
598 | u32 vco_mode; |
599 | u32 real_clock; |
600 | /* added for CI */ |
601 | u32 post_divider; |
602 | u32 flags; |
603 | }; |
604 | |
605 | struct atom_mpll_param { |
606 | union { |
607 | struct { |
608 | #ifdef __BIG_ENDIAN |
609 | u32 reserved : 8; |
610 | u32 clkfrac : 12; |
611 | u32 clkf : 12; |
612 | #else |
613 | u32 clkf : 12; |
614 | u32 clkfrac : 12; |
615 | u32 reserved : 8; |
616 | #endif |
617 | }; |
618 | u32 fb_div; |
619 | }; |
620 | u32 post_div; |
621 | u32 bwcntl; |
622 | u32 dll_speed; |
623 | u32 vco_mode; |
624 | u32 yclk_sel; |
625 | u32 qdr; |
626 | u32 half_rate; |
627 | }; |
628 | |
629 | #define MEM_TYPE_GDDR5 0x50 |
630 | #define MEM_TYPE_GDDR4 0x40 |
631 | #define MEM_TYPE_GDDR3 0x30 |
632 | #define MEM_TYPE_DDR2 0x20 |
633 | #define MEM_TYPE_GDDR1 0x10 |
634 | #define MEM_TYPE_DDR3 0xb0 |
635 | #define MEM_TYPE_MASK 0xf0 |
636 | |
637 | struct atom_memory_info { |
638 | u8 mem_vendor; |
639 | u8 mem_type; |
640 | }; |
641 | |
642 | #define MAX_AC_TIMING_ENTRIES 16 |
643 | |
644 | struct atom_memory_clock_range_table |
645 | { |
646 | u8 num_entries; |
647 | u8 rsv[3]; |
648 | u32 mclk[MAX_AC_TIMING_ENTRIES]; |
649 | }; |
650 | |
651 | #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 |
652 | #define VBIOS_MAX_AC_TIMING_ENTRIES 20 |
653 | |
654 | struct atom_mc_reg_entry { |
655 | u32 mclk_max; |
656 | u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; |
657 | }; |
658 | |
659 | struct atom_mc_register_address { |
660 | u16 s1; |
661 | u8 pre_reg_data; |
662 | }; |
663 | |
664 | struct atom_mc_reg_table { |
665 | u8 last; |
666 | u8 num_entries; |
667 | struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; |
668 | struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; |
669 | }; |
670 | |
671 | #define MAX_VOLTAGE_ENTRIES 32 |
672 | |
673 | struct atom_voltage_table_entry |
674 | { |
675 | u16 value; |
676 | u32 smio_low; |
677 | }; |
678 | |
679 | struct atom_voltage_table |
680 | { |
681 | u32 count; |
682 | u32 mask_low; |
683 | u32 phase_delay; |
684 | struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; |
685 | }; |
686 | |
687 | /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */ |
688 | #define DRM_SCANOUTPOS_VALID (1 << 0) |
689 | #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) |
690 | #define DRM_SCANOUTPOS_ACCURATE (1 << 2) |
691 | #define USE_REAL_VBLANKSTART (1 << 30) |
692 | #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) |
693 | |
694 | extern void |
695 | radeon_add_atom_connector(struct drm_device *dev, |
696 | uint32_t connector_id, |
697 | uint32_t supported_device, |
698 | int connector_type, |
699 | struct radeon_i2c_bus_rec *i2c_bus, |
700 | uint32_t igp_lane_info, |
701 | uint16_t connector_object_id, |
702 | struct radeon_hpd *hpd, |
703 | struct radeon_router *router); |
704 | extern void |
705 | radeon_add_legacy_connector(struct drm_device *dev, |
706 | uint32_t connector_id, |
707 | uint32_t supported_device, |
708 | int connector_type, |
709 | struct radeon_i2c_bus_rec *i2c_bus, |
710 | uint16_t connector_object_id, |
711 | struct radeon_hpd *hpd); |
712 | extern uint32_t |
713 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, |
714 | uint8_t dac); |
715 | extern void radeon_link_encoder_connector(struct drm_device *dev); |
716 | |
717 | extern enum radeon_tv_std |
718 | radeon_combios_get_tv_info(struct radeon_device *rdev); |
719 | extern enum radeon_tv_std |
720 | radeon_atombios_get_tv_info(struct radeon_device *rdev); |
721 | extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, |
722 | u16 *vddc, u16 *vddci, u16 *mvdd); |
723 | |
724 | extern void |
725 | radeon_combios_connected_scratch_regs(struct drm_connector *connector, |
726 | struct drm_encoder *encoder, |
727 | bool connected); |
728 | extern void |
729 | radeon_atombios_connected_scratch_regs(struct drm_connector *connector, |
730 | struct drm_encoder *encoder, |
731 | bool connected); |
732 | |
733 | extern struct drm_connector * |
734 | radeon_get_connector_for_encoder(struct drm_encoder *encoder); |
735 | extern struct drm_connector * |
736 | radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); |
737 | extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, |
738 | u32 pixel_clock); |
739 | |
740 | extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); |
741 | extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); |
742 | extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); |
743 | extern int radeon_get_monitor_bpc(struct drm_connector *connector); |
744 | |
745 | extern struct edid *radeon_connector_edid(struct drm_connector *connector); |
746 | |
747 | extern void radeon_connector_hotplug(struct drm_connector *connector); |
748 | extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
749 | struct drm_display_mode *mode); |
750 | extern void radeon_dp_set_link_config(struct drm_connector *connector, |
751 | const struct drm_display_mode *mode); |
752 | extern void radeon_dp_link_train(struct drm_encoder *encoder, |
753 | struct drm_connector *connector); |
754 | extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); |
755 | extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); |
756 | extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); |
757 | extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
758 | struct drm_connector *connector); |
759 | extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, |
760 | u8 power_state); |
761 | extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); |
762 | extern ssize_t |
763 | radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg); |
764 | |
765 | extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); |
766 | extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override); |
767 | extern void radeon_atom_encoder_init(struct radeon_device *rdev); |
768 | extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); |
769 | extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, |
770 | int action, uint8_t lane_num, |
771 | uint8_t lane_set); |
772 | extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder, |
773 | int action, uint8_t lane_num, |
774 | uint8_t lane_set, int fe); |
775 | extern void atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, |
776 | int fe); |
777 | extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); |
778 | extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); |
779 | void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); |
780 | |
781 | extern void radeon_i2c_init(struct radeon_device *rdev); |
782 | extern void radeon_i2c_fini(struct radeon_device *rdev); |
783 | extern void radeon_combios_i2c_init(struct radeon_device *rdev); |
784 | extern void radeon_atombios_i2c_init(struct radeon_device *rdev); |
785 | extern void radeon_i2c_add(struct radeon_device *rdev, |
786 | struct radeon_i2c_bus_rec *rec, |
787 | const char *name); |
788 | extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, |
789 | struct radeon_i2c_bus_rec *i2c_bus); |
790 | extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
791 | struct radeon_i2c_bus_rec *rec, |
792 | const char *name); |
793 | extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); |
794 | extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, |
795 | u8 slave_addr, |
796 | u8 addr, |
797 | u8 *val); |
798 | extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, |
799 | u8 slave_addr, |
800 | u8 addr, |
801 | u8 val); |
802 | extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); |
803 | extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); |
804 | extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); |
805 | |
806 | extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, |
807 | struct radeon_atom_ss *ss, |
808 | int id); |
809 | extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, |
810 | struct radeon_atom_ss *ss, |
811 | int id, u32 clock); |
812 | extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, |
813 | u8 id); |
814 | |
815 | extern void radeon_compute_pll_legacy(struct radeon_pll *pll, |
816 | uint64_t freq, |
817 | uint32_t *dot_clock_p, |
818 | uint32_t *fb_div_p, |
819 | uint32_t *frac_fb_div_p, |
820 | uint32_t *ref_div_p, |
821 | uint32_t *post_div_p); |
822 | |
823 | extern void radeon_compute_pll_avivo(struct radeon_pll *pll, |
824 | u32 freq, |
825 | u32 *dot_clock_p, |
826 | u32 *fb_div_p, |
827 | u32 *frac_fb_div_p, |
828 | u32 *ref_div_p, |
829 | u32 *post_div_p); |
830 | |
831 | extern void radeon_setup_encoder_clones(struct drm_device *dev); |
832 | |
833 | struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); |
834 | struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
835 | struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
836 | struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); |
837 | struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); |
838 | extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); |
839 | extern void atombios_digital_setup(struct drm_encoder *encoder, int action); |
840 | extern int atombios_get_encoder_mode(struct drm_encoder *encoder); |
841 | extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); |
842 | extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); |
843 | extern bool radeon_encoder_is_digital(struct drm_encoder *encoder); |
844 | |
845 | extern void radeon_crtc_load_lut(struct drm_crtc *crtc); |
846 | extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
847 | struct drm_framebuffer *old_fb); |
848 | extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, |
849 | struct drm_framebuffer *fb, |
850 | int x, int y, |
851 | enum mode_set_atomic state); |
852 | extern int atombios_crtc_mode_set(struct drm_crtc *crtc, |
853 | struct drm_display_mode *mode, |
854 | struct drm_display_mode *adjusted_mode, |
855 | int x, int y, |
856 | struct drm_framebuffer *old_fb); |
857 | extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); |
858 | |
859 | extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
860 | struct drm_framebuffer *old_fb); |
861 | extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, |
862 | struct drm_framebuffer *fb, |
863 | int x, int y, |
864 | enum mode_set_atomic state); |
865 | extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, |
866 | struct drm_framebuffer *fb, |
867 | int x, int y, int atomic); |
868 | extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc, |
869 | struct drm_file *file_priv, |
870 | uint32_t handle, |
871 | uint32_t width, |
872 | uint32_t height, |
873 | int32_t hot_x, |
874 | int32_t hot_y); |
875 | extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, |
876 | int x, int y); |
877 | extern void radeon_cursor_reset(struct drm_crtc *crtc); |
878 | |
879 | extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, |
880 | unsigned int flags, int *vpos, int *hpos, |
881 | ktime_t *stime, ktime_t *etime, |
882 | const struct drm_display_mode *mode); |
883 | |
884 | extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); |
885 | extern struct edid * |
886 | radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); |
887 | extern bool radeon_atom_get_clock_info(struct drm_device *dev); |
888 | extern bool radeon_combios_get_clock_info(struct drm_device *dev); |
889 | extern struct radeon_encoder_atom_dig * |
890 | radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); |
891 | extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
892 | struct radeon_encoder_int_tmds *tmds); |
893 | extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, |
894 | struct radeon_encoder_int_tmds *tmds); |
895 | extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, |
896 | struct radeon_encoder_int_tmds *tmds); |
897 | extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, |
898 | struct radeon_encoder_ext_tmds *tmds); |
899 | extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, |
900 | struct radeon_encoder_ext_tmds *tmds); |
901 | extern struct radeon_encoder_primary_dac * |
902 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); |
903 | extern struct radeon_encoder_tv_dac * |
904 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); |
905 | extern struct radeon_encoder_lvds * |
906 | radeon_combios_get_lvds_info(struct radeon_encoder *encoder); |
907 | extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); |
908 | extern struct radeon_encoder_tv_dac * |
909 | radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); |
910 | extern struct radeon_encoder_primary_dac * |
911 | radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); |
912 | extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); |
913 | extern void radeon_external_tmds_setup(struct drm_encoder *encoder); |
914 | extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); |
915 | extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); |
916 | extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); |
917 | extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); |
918 | extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); |
919 | extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); |
920 | extern void |
921 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
922 | extern void |
923 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
924 | extern void |
925 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
926 | extern void |
927 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
928 | int radeon_framebuffer_init(struct drm_device *dev, |
929 | struct drm_framebuffer *rfb, |
930 | const struct drm_mode_fb_cmd2 *mode_cmd, |
931 | struct drm_gem_object *obj); |
932 | |
933 | int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); |
934 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); |
935 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); |
936 | void radeon_atombios_init_crtc(struct drm_device *dev, |
937 | struct radeon_crtc *radeon_crtc); |
938 | void radeon_legacy_init_crtc(struct drm_device *dev, |
939 | struct radeon_crtc *radeon_crtc); |
940 | |
941 | void radeon_get_clock_info(struct drm_device *dev); |
942 | |
943 | extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); |
944 | extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); |
945 | |
946 | void radeon_enc_destroy(struct drm_encoder *encoder); |
947 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); |
948 | void radeon_combios_asic_init(struct drm_device *dev); |
949 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
950 | const struct drm_display_mode *mode, |
951 | struct drm_display_mode *adjusted_mode); |
952 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, |
953 | struct drm_display_mode *adjusted_mode); |
954 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); |
955 | |
956 | /* legacy tv */ |
957 | void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, |
958 | uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, |
959 | uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); |
960 | void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, |
961 | uint32_t *htotal_cntl, uint32_t *ppll_ref_div, |
962 | uint32_t *ppll_div_3, uint32_t *pixclks_cntl); |
963 | void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, |
964 | uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, |
965 | uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); |
966 | void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, |
967 | struct drm_display_mode *mode, |
968 | struct drm_display_mode *adjusted_mode); |
969 | |
970 | /* fmt blocks */ |
971 | void avivo_program_fmt(struct drm_encoder *encoder); |
972 | void dce3_program_fmt(struct drm_encoder *encoder); |
973 | void dce4_program_fmt(struct drm_encoder *encoder); |
974 | void dce8_program_fmt(struct drm_encoder *encoder); |
975 | |
976 | /* fbdev layer */ |
977 | int radeon_fbdev_init(struct radeon_device *rdev); |
978 | void radeon_fbdev_fini(struct radeon_device *rdev); |
979 | void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); |
980 | bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); |
981 | |
982 | void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); |
983 | |
984 | void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector); |
985 | void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector); |
986 | |
987 | void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); |
988 | |
989 | int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); |
990 | |
991 | /* mst */ |
992 | int radeon_dp_mst_init(struct radeon_connector *radeon_connector); |
993 | int radeon_dp_mst_probe(struct radeon_connector *radeon_connector); |
994 | int radeon_dp_mst_check_status(struct radeon_connector *radeon_connector); |
995 | int radeon_mst_debugfs_init(struct radeon_device *rdev); |
996 | void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode); |
997 | |
998 | void radeon_setup_mst_connector(struct drm_device *dev); |
999 | |
1000 | int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx); |
1001 | void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx); |
1002 | #endif |
1003 | |