1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25#ifndef __RV6XX_DPM_H__
26#define __RV6XX_DPM_H__
27
28#include "r600_dpm.h"
29
30/* Represents a single SCLK step. */
31struct rv6xx_sclk_stepping
32{
33 u32 vco_frequency;
34 u32 post_divider;
35};
36
37struct rv6xx_pm_hw_state {
38 u32 sclks[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
39 u32 mclks[R600_PM_NUMBER_OF_MCLKS];
40 u16 vddc[R600_PM_NUMBER_OF_VOLTAGE_LEVELS];
41 bool backbias[R600_PM_NUMBER_OF_VOLTAGE_LEVELS];
42 bool pcie_gen2[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
43 u8 high_sclk_index;
44 u8 medium_sclk_index;
45 u8 low_sclk_index;
46 u8 high_mclk_index;
47 u8 medium_mclk_index;
48 u8 low_mclk_index;
49 u8 high_vddc_index;
50 u8 medium_vddc_index;
51 u8 low_vddc_index;
52 u8 rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
53 u8 lp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
54};
55
56struct rv6xx_power_info {
57 /* flags */
58 bool voltage_control;
59 bool sclk_ss;
60 bool mclk_ss;
61 bool dynamic_ss;
62 bool dynamic_pcie_gen2;
63 bool thermal_protection;
64 bool display_gap;
65 bool gfx_clock_gating;
66 /* clk values */
67 u32 fb_div_scale;
68 u32 spll_ref_div;
69 u32 mpll_ref_div;
70 u32 bsu;
71 u32 bsp;
72 /* */
73 u32 active_auto_throttle_sources;
74 /* current power state */
75 u32 restricted_levels;
76 struct rv6xx_pm_hw_state hw;
77};
78
79struct rv6xx_pl {
80 u32 sclk;
81 u32 mclk;
82 u16 vddc;
83 u32 flags;
84};
85
86struct rv6xx_ps {
87 struct rv6xx_pl high;
88 struct rv6xx_pl medium;
89 struct rv6xx_pl low;
90};
91
92#define RV6XX_DEFAULT_VCLK_FREQ 40000 /* 10 khz */
93#define RV6XX_DEFAULT_DCLK_FREQ 30000 /* 10 khz */
94
95#endif
96