| 1 | /* |
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| 2 | * Copyright 2011 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | #ifndef RV740_H |
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| 24 | #define RV740_H |
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| 25 | |
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| 26 | #define CG_SPLL_FUNC_CNTL 0x600 |
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| 27 | #define SPLL_RESET (1 << 0) |
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| 28 | #define SPLL_SLEEP (1 << 1) |
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| 29 | #define SPLL_BYPASS_EN (1 << 3) |
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| 30 | #define SPLL_REF_DIV(x) ((x) << 4) |
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| 31 | #define SPLL_REF_DIV_MASK (0x3f << 4) |
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| 32 | #define SPLL_PDIV_A(x) ((x) << 20) |
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| 33 | #define SPLL_PDIV_A_MASK (0x7f << 20) |
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| 34 | #define CG_SPLL_FUNC_CNTL_2 0x604 |
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| 35 | #define SCLK_MUX_SEL(x) ((x) << 0) |
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| 36 | #define SCLK_MUX_SEL_MASK (0x1ff << 0) |
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| 37 | #define CG_SPLL_FUNC_CNTL_3 0x608 |
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| 38 | #define SPLL_FB_DIV(x) ((x) << 0) |
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| 39 | #define SPLL_FB_DIV_MASK (0x3ffffff << 0) |
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| 40 | #define SPLL_DITHEN (1 << 28) |
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| 41 | |
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| 42 | #define MPLL_CNTL_MODE 0x61c |
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| 43 | #define SS_SSEN (1 << 24) |
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| 44 | |
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| 45 | #define MPLL_AD_FUNC_CNTL 0x624 |
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| 46 | #define CLKF(x) ((x) << 0) |
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| 47 | #define CLKF_MASK (0x7f << 0) |
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| 48 | #define CLKR(x) ((x) << 7) |
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| 49 | #define CLKR_MASK (0x1f << 7) |
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| 50 | #define CLKFRAC(x) ((x) << 12) |
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| 51 | #define CLKFRAC_MASK (0x1f << 12) |
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| 52 | #define YCLK_POST_DIV(x) ((x) << 17) |
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| 53 | #define YCLK_POST_DIV_MASK (3 << 17) |
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| 54 | #define IBIAS(x) ((x) << 20) |
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| 55 | #define IBIAS_MASK (0x3ff << 20) |
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| 56 | #define RESET (1 << 30) |
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| 57 | #define PDNB (1 << 31) |
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| 58 | #define MPLL_AD_FUNC_CNTL_2 0x628 |
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| 59 | #define BYPASS (1 << 19) |
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| 60 | #define BIAS_GEN_PDNB (1 << 24) |
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| 61 | #define RESET_EN (1 << 25) |
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| 62 | #define VCO_MODE (1 << 29) |
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| 63 | #define MPLL_DQ_FUNC_CNTL 0x62c |
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| 64 | #define MPLL_DQ_FUNC_CNTL_2 0x630 |
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| 65 | |
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| 66 | #define MCLK_PWRMGT_CNTL 0x648 |
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| 67 | #define DLL_SPEED(x) ((x) << 0) |
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| 68 | #define DLL_SPEED_MASK (0x1f << 0) |
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| 69 | # define MPLL_PWRMGT_OFF (1 << 5) |
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| 70 | # define DLL_READY (1 << 6) |
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| 71 | # define MC_INT_CNTL (1 << 7) |
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| 72 | # define MRDCKA0_SLEEP (1 << 8) |
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| 73 | # define MRDCKA1_SLEEP (1 << 9) |
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| 74 | # define MRDCKB0_SLEEP (1 << 10) |
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| 75 | # define MRDCKB1_SLEEP (1 << 11) |
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| 76 | # define MRDCKC0_SLEEP (1 << 12) |
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| 77 | # define MRDCKC1_SLEEP (1 << 13) |
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| 78 | # define MRDCKD0_SLEEP (1 << 14) |
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| 79 | # define MRDCKD1_SLEEP (1 << 15) |
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| 80 | # define MRDCKA0_RESET (1 << 16) |
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| 81 | # define MRDCKA1_RESET (1 << 17) |
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| 82 | # define MRDCKB0_RESET (1 << 18) |
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| 83 | # define MRDCKB1_RESET (1 << 19) |
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| 84 | # define MRDCKC0_RESET (1 << 20) |
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| 85 | # define MRDCKC1_RESET (1 << 21) |
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| 86 | # define MRDCKD0_RESET (1 << 22) |
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| 87 | # define MRDCKD1_RESET (1 << 23) |
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| 88 | # define DLL_READY_READ (1 << 24) |
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| 89 | # define USE_DISPLAY_GAP (1 << 25) |
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| 90 | # define USE_DISPLAY_URGENT_NORMAL (1 << 26) |
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| 91 | # define MPLL_TURNOFF_D2 (1 << 28) |
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| 92 | #define DLL_CNTL 0x64c |
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| 93 | # define MRDCKA0_BYPASS (1 << 24) |
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| 94 | # define MRDCKA1_BYPASS (1 << 25) |
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| 95 | # define MRDCKB0_BYPASS (1 << 26) |
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| 96 | # define MRDCKB1_BYPASS (1 << 27) |
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| 97 | # define MRDCKC0_BYPASS (1 << 28) |
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| 98 | # define MRDCKC1_BYPASS (1 << 29) |
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| 99 | # define MRDCKD0_BYPASS (1 << 30) |
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| 100 | # define MRDCKD1_BYPASS (1 << 31) |
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| 101 | |
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| 102 | #define CG_SPLL_SPREAD_SPECTRUM 0x790 |
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| 103 | #define SSEN (1 << 0) |
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| 104 | #define CLK_S(x) ((x) << 4) |
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| 105 | #define CLK_S_MASK (0xfff << 4) |
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| 106 | #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 |
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| 107 | #define CLK_V(x) ((x) << 0) |
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| 108 | #define CLK_V_MASK (0x3ffffff << 0) |
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| 109 | |
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| 110 | #define MPLL_SS1 0x85c |
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| 111 | #define CLKV(x) ((x) << 0) |
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| 112 | #define CLKV_MASK (0x3ffffff << 0) |
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| 113 | #define MPLL_SS2 0x860 |
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| 114 | #define CLKS(x) ((x) << 0) |
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| 115 | #define CLKS_MASK (0xfff << 0) |
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| 116 | |
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| 117 | #endif |
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| 118 | |
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