1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Alex Deucher <alexander.deucher@amd.com>
25 */
26
27#include <linux/types.h>
28#include <linux/bug.h>
29#include <linux/kernel.h>
30
31const u32 si_default_state[] =
32{
33 0xc0066900,
34 0x00000000,
35 0x00000060, /* DB_RENDER_CONTROL */
36 0x00000000, /* DB_COUNT_CONTROL */
37 0x00000000, /* DB_DEPTH_VIEW */
38 0x0000002a, /* DB_RENDER_OVERRIDE */
39 0x00000000, /* DB_RENDER_OVERRIDE2 */
40 0x00000000, /* DB_HTILE_DATA_BASE */
41
42 0xc0046900,
43 0x00000008,
44 0x00000000, /* DB_DEPTH_BOUNDS_MIN */
45 0x00000000, /* DB_DEPTH_BOUNDS_MAX */
46 0x00000000, /* DB_STENCIL_CLEAR */
47 0x00000000, /* DB_DEPTH_CLEAR */
48
49 0xc0036900,
50 0x0000000f,
51 0x00000000, /* DB_DEPTH_INFO */
52 0x00000000, /* DB_Z_INFO */
53 0x00000000, /* DB_STENCIL_INFO */
54
55 0xc0016900,
56 0x00000080,
57 0x00000000, /* PA_SC_WINDOW_OFFSET */
58
59 0xc00d6900,
60 0x00000083,
61 0x0000ffff, /* PA_SC_CLIPRECT_RULE */
62 0x00000000, /* PA_SC_CLIPRECT_0_TL */
63 0x20002000, /* PA_SC_CLIPRECT_0_BR */
64 0x00000000,
65 0x20002000,
66 0x00000000,
67 0x20002000,
68 0x00000000,
69 0x20002000,
70 0xaaaaaaaa, /* PA_SC_EDGERULE */
71 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
72 0x0000000f, /* CB_TARGET_MASK */
73 0x0000000f, /* CB_SHADER_MASK */
74
75 0xc0226900,
76 0x00000094,
77 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
78 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
79 0x80000000,
80 0x20002000,
81 0x80000000,
82 0x20002000,
83 0x80000000,
84 0x20002000,
85 0x80000000,
86 0x20002000,
87 0x80000000,
88 0x20002000,
89 0x80000000,
90 0x20002000,
91 0x80000000,
92 0x20002000,
93 0x80000000,
94 0x20002000,
95 0x80000000,
96 0x20002000,
97 0x80000000,
98 0x20002000,
99 0x80000000,
100 0x20002000,
101 0x80000000,
102 0x20002000,
103 0x80000000,
104 0x20002000,
105 0x80000000,
106 0x20002000,
107 0x80000000,
108 0x20002000,
109 0x00000000, /* PA_SC_VPORT_ZMIN_0 */
110 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
111
112 0xc0026900,
113 0x000000d9,
114 0x00000000, /* CP_RINGID */
115 0x00000000, /* CP_VMID */
116
117 0xc0046900,
118 0x00000100,
119 0xffffffff, /* VGT_MAX_VTX_INDX */
120 0x00000000, /* VGT_MIN_VTX_INDX */
121 0x00000000, /* VGT_INDX_OFFSET */
122 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
123
124 0xc0046900,
125 0x00000105,
126 0x00000000, /* CB_BLEND_RED */
127 0x00000000, /* CB_BLEND_GREEN */
128 0x00000000, /* CB_BLEND_BLUE */
129 0x00000000, /* CB_BLEND_ALPHA */
130
131 0xc0016900,
132 0x000001e0,
133 0x00000000, /* CB_BLEND0_CONTROL */
134
135 0xc00e6900,
136 0x00000200,
137 0x00000000, /* DB_DEPTH_CONTROL */
138 0x00000000, /* DB_EQAA */
139 0x00cc0010, /* CB_COLOR_CONTROL */
140 0x00000210, /* DB_SHADER_CONTROL */
141 0x00010000, /* PA_CL_CLIP_CNTL */
142 0x00000004, /* PA_SU_SC_MODE_CNTL */
143 0x00000100, /* PA_CL_VTE_CNTL */
144 0x00000000, /* PA_CL_VS_OUT_CNTL */
145 0x00000000, /* PA_CL_NANINF_CNTL */
146 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
147 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
148 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
149 0x00000000, /* */
150 0x00000000, /* */
151
152 0xc0116900,
153 0x00000280,
154 0x00000000, /* PA_SU_POINT_SIZE */
155 0x00000000, /* PA_SU_POINT_MINMAX */
156 0x00000008, /* PA_SU_LINE_CNTL */
157 0x00000000, /* PA_SC_LINE_STIPPLE */
158 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
159 0x00000000, /* VGT_HOS_CNTL */
160 0x00000000,
161 0x00000000,
162 0x00000000,
163 0x00000000,
164 0x00000000,
165 0x00000000,
166 0x00000000,
167 0x00000000,
168 0x00000000,
169 0x00000000,
170 0x00000000, /* VGT_GS_MODE */
171
172 0xc0026900,
173 0x00000292,
174 0x00000000, /* PA_SC_MODE_CNTL_0 */
175 0x00000000, /* PA_SC_MODE_CNTL_1 */
176
177 0xc0016900,
178 0x000002a1,
179 0x00000000, /* VGT_PRIMITIVEID_EN */
180
181 0xc0016900,
182 0x000002a5,
183 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
184
185 0xc0026900,
186 0x000002a8,
187 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
188 0x00000000,
189
190 0xc0026900,
191 0x000002ad,
192 0x00000000, /* VGT_REUSE_OFF */
193 0x00000000,
194
195 0xc0016900,
196 0x000002d5,
197 0x00000000, /* VGT_SHADER_STAGES_EN */
198
199 0xc0016900,
200 0x000002dc,
201 0x0000aa00, /* DB_ALPHA_TO_MASK */
202
203 0xc0066900,
204 0x000002de,
205 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
206 0x00000000,
207 0x00000000,
208 0x00000000,
209 0x00000000,
210 0x00000000,
211
212 0xc0026900,
213 0x000002e5,
214 0x00000000, /* VGT_STRMOUT_CONFIG */
215 0x00000000,
216
217 0xc01b6900,
218 0x000002f5,
219 0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */
220 0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */
221 0x00000000, /* PA_SC_LINE_CNTL */
222 0x00000000, /* PA_SC_AA_CONFIG */
223 0x00000005, /* PA_SU_VTX_CNTL */
224 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
225 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
226 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
227 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
228 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
229 0x00000000,
230 0x00000000,
231 0x00000000,
232 0x00000000,
233 0x00000000,
234 0x00000000,
235 0x00000000,
236 0x00000000,
237 0x00000000,
238 0x00000000,
239 0x00000000,
240 0x00000000,
241 0x00000000,
242 0x00000000,
243 0x00000000,
244 0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */
245 0xffffffff,
246
247 0xc0026900,
248 0x00000316,
249 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
250 0x00000010, /* */
251};
252
253const u32 si_default_size = ARRAY_SIZE(si_default_state);
254