1	/*
2	* Copyright 2011 Advanced Micro Devices, Inc.
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.
13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20	* OTHER DEALINGS IN THE SOFTWARE.
21	*
22	* Authors: Alex Deucher
23	*/
24	#ifndef SI_H
25	#define SI_H
26
27	#define TAHITI_RB_BITMAP_WIDTH_PER_SH 2
28
29	#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
30	#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
31	#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
32
33	#define SI_MAX_SH_GPRS 256
34	#define SI_MAX_TEMP_GPRS 16
35	#define SI_MAX_SH_THREADS 256
36	#define SI_MAX_SH_STACK_ENTRIES 4096
37	#define SI_MAX_FRC_EOV_CNT 16384
38	#define SI_MAX_BACKENDS 8
39	#define SI_MAX_BACKENDS_MASK 0xFF
40	#define SI_MAX_BACKENDS_PER_SE_MASK 0x0F
41	#define SI_MAX_SIMDS 12
42	#define SI_MAX_SIMDS_MASK 0x0FFF
43	#define SI_MAX_SIMDS_PER_SE_MASK 0x00FF
44	#define SI_MAX_PIPES 8
45	#define SI_MAX_PIPES_MASK 0xFF
46	#define SI_MAX_PIPES_PER_SIMD_MASK 0x3F
47	#define SI_MAX_LDS_NUM 0xFFFF
48	#define SI_MAX_TCC 16
49	#define SI_MAX_TCC_MASK 0xFFFF
50
51	/* SMC IND accessor regs */
52	#define SMC_IND_INDEX_0 0x200
53	#define SMC_IND_DATA_0 0x204
54
55	#define SMC_IND_ACCESS_CNTL 0x228
56	# define AUTO_INCREMENT_IND_0 (1 << 0)
57	#define SMC_MESSAGE_0 0x22c
58	#define SMC_RESP_0 0x230
59
60	/* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */
61	#define SMC_CG_IND_START 0xc0030000
62	#define SMC_CG_IND_END 0xc0040000
63
64	#define CG_CGTT_LOCAL_0 0x400
65	#define CG_CGTT_LOCAL_1 0x401
66
67	/* SMC IND registers */
68	#define SMC_SYSCON_RESET_CNTL 0x80000000
69	# define RST_REG (1 << 0)
70	#define SMC_SYSCON_CLOCK_CNTL_0 0x80000004
71	# define CK_DISABLE (1 << 0)
72	# define CKEN (1 << 24)
73
74	#define VGA_HDP_CONTROL 0x328
75	#define VGA_MEMORY_DISABLE (1 << 4)
76
77	#define DCCG_DISP_SLOW_SELECT_REG 0x4fc
78	#define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0)
79	#define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0)
80	#define DCCG_DISP1_SLOW_SELECT_SHIFT 0
81	#define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4)
82	#define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4)
83	#define DCCG_DISP2_SLOW_SELECT_SHIFT 4
84
85	#define CG_SPLL_FUNC_CNTL 0x600
86	#define SPLL_RESET (1 << 0)
87	#define SPLL_SLEEP (1 << 1)
88	#define SPLL_BYPASS_EN (1 << 3)
89	#define SPLL_REF_DIV(x) ((x) << 4)
90	#define SPLL_REF_DIV_MASK (0x3f << 4)
91	#define SPLL_PDIV_A(x) ((x) << 20)
92	#define SPLL_PDIV_A_MASK (0x7f << 20)
93	#define SPLL_PDIV_A_SHIFT 20
94	#define CG_SPLL_FUNC_CNTL_2 0x604
95	#define SCLK_MUX_SEL(x) ((x) << 0)
96	#define SCLK_MUX_SEL_MASK (0x1ff << 0)
97	#define SPLL_CTLREQ_CHG (1 << 23)
98	#define SCLK_MUX_UPDATE (1 << 26)
99	#define CG_SPLL_FUNC_CNTL_3 0x608
100	#define SPLL_FB_DIV(x) ((x) << 0)
101	#define SPLL_FB_DIV_MASK (0x3ffffff << 0)
102	#define SPLL_FB_DIV_SHIFT 0
103	#define SPLL_DITHEN (1 << 28)
104	#define CG_SPLL_FUNC_CNTL_4 0x60c
105
106	#define SPLL_STATUS 0x614
107	#define SPLL_CHG_STATUS (1 << 1)
108	#define SPLL_CNTL_MODE 0x618
109	#define SPLL_SW_DIR_CONTROL (1 << 0)
110	# define SPLL_REFCLK_SEL(x) ((x) << 26)
111	# define SPLL_REFCLK_SEL_MASK (3 << 26)
112
113	#define CG_SPLL_SPREAD_SPECTRUM 0x620
114	#define SSEN (1 << 0)
115	#define CLK_S(x) ((x) << 4)
116	#define CLK_S_MASK (0xfff << 4)
117	#define CLK_S_SHIFT 4
118	#define CG_SPLL_SPREAD_SPECTRUM_2 0x624
119	#define CLK_V(x) ((x) << 0)
120	#define CLK_V_MASK (0x3ffffff << 0)
121	#define CLK_V_SHIFT 0
122
123	#define CG_SPLL_AUTOSCALE_CNTL 0x62c
124	# define AUTOSCALE_ON_SS_CLEAR (1 << 9)
125
126	/* discrete uvd clocks */
127	#define CG_UPLL_FUNC_CNTL 0x634
128	# define UPLL_RESET_MASK 0x00000001
129	# define UPLL_SLEEP_MASK 0x00000002
130	# define UPLL_BYPASS_EN_MASK 0x00000004
131	# define UPLL_CTLREQ_MASK 0x00000008
132	# define UPLL_VCO_MODE_MASK 0x00000600
133	# define UPLL_REF_DIV_MASK 0x003F0000
134	# define UPLL_CTLACK_MASK 0x40000000
135	# define UPLL_CTLACK2_MASK 0x80000000
136	#define CG_UPLL_FUNC_CNTL_2 0x638
137	# define UPLL_PDIV_A(x) ((x) << 0)
138	# define UPLL_PDIV_A_MASK 0x0000007F
139	# define UPLL_PDIV_B(x) ((x) << 8)
140	# define UPLL_PDIV_B_MASK 0x00007F00
141	# define VCLK_SRC_SEL(x) ((x) << 20)
142	# define VCLK_SRC_SEL_MASK 0x01F00000
143	# define DCLK_SRC_SEL(x) ((x) << 25)
144	# define DCLK_SRC_SEL_MASK 0x3E000000
145	#define CG_UPLL_FUNC_CNTL_3 0x63C
146	# define UPLL_FB_DIV(x) ((x) << 0)
147	# define UPLL_FB_DIV_MASK 0x01FFFFFF
148	#define CG_UPLL_FUNC_CNTL_4 0x644
149	# define UPLL_SPARE_ISPARE9 0x00020000
150	#define CG_UPLL_FUNC_CNTL_5 0x648
151	# define RESET_ANTI_MUX_MASK 0x00000200
152	#define CG_UPLL_SPREAD_SPECTRUM 0x650
153	# define SSEN_MASK 0x00000001
154
155	#define MPLL_BYPASSCLK_SEL 0x65c
156	# define MPLL_CLKOUT_SEL(x) ((x) << 8)
157	# define MPLL_CLKOUT_SEL_MASK 0xFF00
158
159	#define CG_CLKPIN_CNTL 0x660
160	# define XTALIN_DIVIDE (1 << 1)
161	# define BCLK_AS_XCLK (1 << 2)
162	#define CG_CLKPIN_CNTL_2 0x664
163	# define FORCE_BIF_REFCLK_EN (1 << 3)
164	# define MUX_TCLK_TO_XCLK (1 << 8)
165
166	#define THM_CLK_CNTL 0x66c
167	# define CMON_CLK_SEL(x) ((x) << 0)
168	# define CMON_CLK_SEL_MASK 0xFF
169	# define TMON_CLK_SEL(x) ((x) << 8)
170	# define TMON_CLK_SEL_MASK 0xFF00
171	#define MISC_CLK_CNTL 0x670
172	# define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)
173	# define DEEP_SLEEP_CLK_SEL_MASK 0xFF
174	# define ZCLK_SEL(x) ((x) << 8)
175	# define ZCLK_SEL_MASK 0xFF00
176
177	#define CG_THERMAL_CTRL 0x700
178	#define DPM_EVENT_SRC(x) ((x) << 0)
179	#define DPM_EVENT_SRC_MASK (7 << 0)
180	#define DIG_THERM_DPM(x) ((x) << 14)
181	#define DIG_THERM_DPM_MASK 0x003FC000
182	#define DIG_THERM_DPM_SHIFT 14
183	#define CG_THERMAL_STATUS 0x704
184	#define FDO_PWM_DUTY(x) ((x) << 9)
185	#define FDO_PWM_DUTY_MASK (0xff << 9)
186	#define FDO_PWM_DUTY_SHIFT 9
187	#define CG_THERMAL_INT 0x708
188	#define DIG_THERM_INTH(x) ((x) << 8)
189	#define DIG_THERM_INTH_MASK 0x0000FF00
190	#define DIG_THERM_INTH_SHIFT 8
191	#define DIG_THERM_INTL(x) ((x) << 16)
192	#define DIG_THERM_INTL_MASK 0x00FF0000
193	#define DIG_THERM_INTL_SHIFT 16
194	#define THERM_INT_MASK_HIGH (1 << 24)
195	#define THERM_INT_MASK_LOW (1 << 25)
196
197	#define CG_MULT_THERMAL_CTRL 0x710
198	#define TEMP_SEL(x) ((x) << 20)
199	#define TEMP_SEL_MASK (0xff << 20)
200	#define TEMP_SEL_SHIFT 20
201	#define CG_MULT_THERMAL_STATUS 0x714
202	#define ASIC_MAX_TEMP(x) ((x) << 0)
203	#define ASIC_MAX_TEMP_MASK 0x000001ff
204	#define ASIC_MAX_TEMP_SHIFT 0
205	#define CTF_TEMP(x) ((x) << 9)
206	#define CTF_TEMP_MASK 0x0003fe00
207	#define CTF_TEMP_SHIFT 9
208
209	#define CG_FDO_CTRL0 0x754
210	#define FDO_STATIC_DUTY(x) ((x) << 0)
211	#define FDO_STATIC_DUTY_MASK 0x000000FF
212	#define FDO_STATIC_DUTY_SHIFT 0
213	#define CG_FDO_CTRL1 0x758
214	#define FMAX_DUTY100(x) ((x) << 0)
215	#define FMAX_DUTY100_MASK 0x000000FF
216	#define FMAX_DUTY100_SHIFT 0
217	#define CG_FDO_CTRL2 0x75C
218	#define TMIN(x) ((x) << 0)
219	#define TMIN_MASK 0x000000FF
220	#define TMIN_SHIFT 0
221	#define FDO_PWM_MODE(x) ((x) << 11)
222	#define FDO_PWM_MODE_MASK (7 << 11)
223	#define FDO_PWM_MODE_SHIFT 11
224	#define TACH_PWM_RESP_RATE(x) ((x) << 25)
225	#define TACH_PWM_RESP_RATE_MASK (0x7f << 25)
226	#define TACH_PWM_RESP_RATE_SHIFT 25
227
228	#define CG_TACH_CTRL 0x770
229	# define EDGE_PER_REV(x) ((x) << 0)
230	# define EDGE_PER_REV_MASK (0x7 << 0)
231	# define EDGE_PER_REV_SHIFT 0
232	# define TARGET_PERIOD(x) ((x) << 3)
233	# define TARGET_PERIOD_MASK 0xfffffff8
234	# define TARGET_PERIOD_SHIFT 3
235	#define CG_TACH_STATUS 0x774
236	# define TACH_PERIOD(x) ((x) << 0)
237	# define TACH_PERIOD_MASK 0xffffffff
238	# define TACH_PERIOD_SHIFT 0
239
240	#define GENERAL_PWRMGT 0x780
241	# define GLOBAL_PWRMGT_EN (1 << 0)
242	# define STATIC_PM_EN (1 << 1)
243	# define THERMAL_PROTECTION_DIS (1 << 2)
244	# define THERMAL_PROTECTION_TYPE (1 << 3)
245	# define SW_SMIO_INDEX(x) ((x) << 6)
246	# define SW_SMIO_INDEX_MASK (1 << 6)
247	# define SW_SMIO_INDEX_SHIFT 6
248	# define VOLT_PWRMGT_EN (1 << 10)
249	# define DYN_SPREAD_SPECTRUM_EN (1 << 23)
250	#define CG_TPC 0x784
251	#define SCLK_PWRMGT_CNTL 0x788
252	# define SCLK_PWRMGT_OFF (1 << 0)
253	# define SCLK_LOW_D1 (1 << 1)
254	# define FIR_RESET (1 << 4)
255	# define FIR_FORCE_TREND_SEL (1 << 5)
256	# define FIR_TREND_MODE (1 << 6)
257	# define DYN_GFX_CLK_OFF_EN (1 << 7)
258	# define GFX_CLK_FORCE_ON (1 << 8)
259	# define GFX_CLK_REQUEST_OFF (1 << 9)
260	# define GFX_CLK_FORCE_OFF (1 << 10)
261	# define GFX_CLK_OFF_ACPI_D1 (1 << 11)
262	# define GFX_CLK_OFF_ACPI_D2 (1 << 12)
263	# define GFX_CLK_OFF_ACPI_D3 (1 << 13)
264	# define DYN_LIGHT_SLEEP_EN (1 << 14)
265
266	#define TARGET_AND_CURRENT_PROFILE_INDEX 0x798
267	# define CURRENT_STATE_INDEX_MASK (0xf << 4)
268	# define CURRENT_STATE_INDEX_SHIFT 4
269
270	#define CG_FTV 0x7bc
271
272	#define CG_FFCT_0 0x7c0
273	# define UTC_0(x) ((x) << 0)
274	# define UTC_0_MASK (0x3ff << 0)
275	# define DTC_0(x) ((x) << 10)
276	# define DTC_0_MASK (0x3ff << 10)
277
278	#define CG_BSP 0x7fc
279	# define BSP(x) ((x) << 0)
280	# define BSP_MASK (0xffff << 0)
281	# define BSU(x) ((x) << 16)
282	# define BSU_MASK (0xf << 16)
283	#define CG_AT 0x800
284	# define CG_R(x) ((x) << 0)
285	# define CG_R_MASK (0xffff << 0)
286	# define CG_L(x) ((x) << 16)
287	# define CG_L_MASK (0xffff << 16)
288
289	#define CG_GIT 0x804
290	# define CG_GICST(x) ((x) << 0)
291	# define CG_GICST_MASK (0xffff << 0)
292	# define CG_GIPOT(x) ((x) << 16)
293	# define CG_GIPOT_MASK (0xffff << 16)
294
295	#define CG_SSP 0x80c
296	# define SST(x) ((x) << 0)
297	# define SST_MASK (0xffff << 0)
298	# define SSTU(x) ((x) << 16)
299	# define SSTU_MASK (0xf << 16)
300
301	#define CG_DISPLAY_GAP_CNTL 0x828
302	# define DISP1_GAP(x) ((x) << 0)
303	# define DISP1_GAP_MASK (3 << 0)
304	# define DISP2_GAP(x) ((x) << 2)
305	# define DISP2_GAP_MASK (3 << 2)
306	# define VBI_TIMER_COUNT(x) ((x) << 4)
307	# define VBI_TIMER_COUNT_MASK (0x3fff << 4)
308	# define VBI_TIMER_UNIT(x) ((x) << 20)
309	# define VBI_TIMER_UNIT_MASK (7 << 20)
310	# define DISP1_GAP_MCHG(x) ((x) << 24)
311	# define DISP1_GAP_MCHG_MASK (3 << 24)
312	# define DISP2_GAP_MCHG(x) ((x) << 26)
313	# define DISP2_GAP_MCHG_MASK (3 << 26)
314
315	#define CG_ULV_CONTROL 0x878
316	#define CG_ULV_PARAMETER 0x87c
317
318	#define SMC_SCRATCH0 0x884
319
320	#define CG_CAC_CTRL 0x8b8
321	# define CAC_WINDOW(x) ((x) << 0)
322	# define CAC_WINDOW_MASK 0x00ffffff
323
324	#define DMIF_ADDR_CONFIG 0xBD4
325
326	#define DMIF_ADDR_CALC 0xC00
327
328	#define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
329	# define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
330	# define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
331
332	#define SRBM_STATUS 0xE50
333	#define GRBM_RQ_PENDING (1 << 5)
334	#define VMC_BUSY (1 << 8)
335	#define MCB_BUSY (1 << 9)
336	#define MCB_NON_DISPLAY_BUSY (1 << 10)
337	#define MCC_BUSY (1 << 11)
338	#define MCD_BUSY (1 << 12)
339	#define SEM_BUSY (1 << 14)
340	#define IH_BUSY (1 << 17)
341
342	#define SRBM_SOFT_RESET 0x0E60
343	#define SOFT_RESET_BIF (1 << 1)
344	#define SOFT_RESET_DC (1 << 5)
345	#define SOFT_RESET_DMA1 (1 << 6)
346	#define SOFT_RESET_GRBM (1 << 8)
347	#define SOFT_RESET_HDP (1 << 9)
348	#define SOFT_RESET_IH (1 << 10)
349	#define SOFT_RESET_MC (1 << 11)
350	#define SOFT_RESET_ROM (1 << 14)
351	#define SOFT_RESET_SEM (1 << 15)
352	#define SOFT_RESET_VMC (1 << 17)
353	#define SOFT_RESET_DMA (1 << 20)
354	#define SOFT_RESET_TST (1 << 21)
355	#define SOFT_RESET_REGBB (1 << 22)
356	#define SOFT_RESET_ORB (1 << 23)
357
358	#define CC_SYS_RB_BACKEND_DISABLE 0xe80
359	#define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
360
361	#define SRBM_READ_ERROR 0xE98
362	#define SRBM_INT_CNTL 0xEA0
363	#define SRBM_INT_ACK 0xEA8
364
365	#define SRBM_STATUS2 0x0EC4
366	#define DMA_BUSY (1 << 5)
367	#define DMA1_BUSY (1 << 6)
368
369	#define VM_L2_CNTL 0x1400
370	#define ENABLE_L2_CACHE (1 << 0)
371	#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
372	#define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
373	#define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
374	#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
375	#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
376	#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
377	#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
378	#define VM_L2_CNTL2 0x1404
379	#define INVALIDATE_ALL_L1_TLBS (1 << 0)
380	#define INVALIDATE_L2_CACHE (1 << 1)
381	#define INVALIDATE_CACHE_MODE(x) ((x) << 26)
382	#define INVALIDATE_PTE_AND_PDE_CACHES 0
383	#define INVALIDATE_ONLY_PTE_CACHES 1
384	#define INVALIDATE_ONLY_PDE_CACHES 2
385	#define VM_L2_CNTL3 0x1408
386	#define BANK_SELECT(x) ((x) << 0)
387	#define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
388	#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
389	#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
390	#define VM_L2_STATUS 0x140C
391	#define L2_BUSY (1 << 0)
392	#define VM_CONTEXT0_CNTL 0x1410
393	#define ENABLE_CONTEXT (1 << 0)
394	#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
395	#define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
396	#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
397	#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
398	#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
399	#define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
400	#define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
401	#define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
402	#define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
403	#define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
404	#define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
405	#define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
406	#define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
407	#define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24)
408	#define VM_CONTEXT1_CNTL 0x1414
409	#define VM_CONTEXT0_CNTL2 0x1430
410	#define VM_CONTEXT1_CNTL2 0x1434
411	#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
412	#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
413	#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
414	#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
415	#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
416	#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
417	#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
418	#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
419
420	#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
421	#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
422	#define PROTECTIONS_MASK (0xf << 0)
423	#define PROTECTIONS_SHIFT 0
424	/* bit 0: range
425	* bit 1: pde0
426	* bit 2: valid
427	* bit 3: read
428	* bit 4: write
429	*/
430	#define MEMORY_CLIENT_ID_MASK (0xff << 12)
431	#define MEMORY_CLIENT_ID_SHIFT 12
432	#define MEMORY_CLIENT_RW_MASK (1 << 24)
433	#define MEMORY_CLIENT_RW_SHIFT 24
434	#define FAULT_VMID_MASK (0xf << 25)
435	#define FAULT_VMID_SHIFT 25
436
437	#define VM_INVALIDATE_REQUEST 0x1478
438	#define VM_INVALIDATE_RESPONSE 0x147c
439
440	#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
441	#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
442
443	#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
444	#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
445	#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
446	#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
447	#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
448	#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
449	#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
450	#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
451	#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
452	#define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
453
454	#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
455	#define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
456
457	#define VM_L2_CG 0x15c0
458	#define MC_CG_ENABLE (1 << 18)
459	#define MC_LS_ENABLE (1 << 19)
460
461	#define MC_SHARED_CHMAP 0x2004
462	#define NOOFCHAN_SHIFT 12
463	#define NOOFCHAN_MASK 0x0000f000
464	#define MC_SHARED_CHREMAP 0x2008
465
466	#define MC_VM_FB_LOCATION 0x2024
467	#define MC_VM_AGP_TOP 0x2028
468	#define MC_VM_AGP_BOT 0x202C
469	#define MC_VM_AGP_BASE 0x2030
470	#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
471	#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
472	#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
473
474	#define MC_VM_MX_L1_TLB_CNTL 0x2064
475	#define ENABLE_L1_TLB (1 << 0)
476	#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
477	#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
478	#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
479	#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
480	#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
481	#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
482	#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
483
484	#define MC_SHARED_BLACKOUT_CNTL 0x20ac
485
486	#define MC_HUB_MISC_HUB_CG 0x20b8
487	#define MC_HUB_MISC_VM_CG 0x20bc
488
489	#define MC_HUB_MISC_SIP_CG 0x20c0
490
491	#define MC_XPB_CLK_GAT 0x2478
492
493	#define MC_CITF_MISC_RD_CG 0x2648
494	#define MC_CITF_MISC_WR_CG 0x264c
495	#define MC_CITF_MISC_VM_CG 0x2650
496
497	#define MC_ARB_RAMCFG 0x2760
498	#define NOOFBANK_SHIFT 0
499	#define NOOFBANK_MASK 0x00000003
500	#define NOOFRANK_SHIFT 2
501	#define NOOFRANK_MASK 0x00000004
502	#define NOOFROWS_SHIFT 3
503	#define NOOFROWS_MASK 0x00000038
504	#define NOOFCOLS_SHIFT 6
505	#define NOOFCOLS_MASK 0x000000C0
506	#define CHANSIZE_SHIFT 8
507	#define CHANSIZE_MASK 0x00000100
508	#define CHANSIZE_OVERRIDE (1 << 11)
509	#define NOOFGROUPS_SHIFT 12
510	#define NOOFGROUPS_MASK 0x00001000
511
512	#define MC_ARB_DRAM_TIMING 0x2774
513	#define MC_ARB_DRAM_TIMING2 0x2778
514
515	#define MC_ARB_BURST_TIME 0x2808
516	#define STATE0(x) ((x) << 0)
517	#define STATE0_MASK (0x1f << 0)
518	#define STATE0_SHIFT 0
519	#define STATE1(x) ((x) << 5)
520	#define STATE1_MASK (0x1f << 5)
521	#define STATE1_SHIFT 5
522	#define STATE2(x) ((x) << 10)
523	#define STATE2_MASK (0x1f << 10)
524	#define STATE2_SHIFT 10
525	#define STATE3(x) ((x) << 15)
526	#define STATE3_MASK (0x1f << 15)
527	#define STATE3_SHIFT 15
528
529	#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8
530	#define TRAIN_DONE_D0 (1 << 30)
531	#define TRAIN_DONE_D1 (1 << 31)
532
533	#define MC_SEQ_SUP_CNTL 0x28c8
534	#define RUN_MASK (1 << 0)
535	#define MC_SEQ_SUP_PGM 0x28cc
536	#define MC_PMG_AUTO_CMD 0x28d0
537
538	#define MC_IO_PAD_CNTL_D0 0x29d0
539	#define MEM_FALL_OUT_CMD (1 << 8)
540
541	#define MC_SEQ_RAS_TIMING 0x28a0
542	#define MC_SEQ_CAS_TIMING 0x28a4
543	#define MC_SEQ_MISC_TIMING 0x28a8
544	#define MC_SEQ_MISC_TIMING2 0x28ac
545	#define MC_SEQ_PMG_TIMING 0x28b0
546	#define MC_SEQ_RD_CTL_D0 0x28b4
547	#define MC_SEQ_RD_CTL_D1 0x28b8
548	#define MC_SEQ_WR_CTL_D0 0x28bc
549	#define MC_SEQ_WR_CTL_D1 0x28c0
550
551	#define MC_SEQ_MISC0 0x2a00
552	#define MC_SEQ_MISC0_VEN_ID_SHIFT 8
553	#define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00
554	#define MC_SEQ_MISC0_VEN_ID_VALUE 3
555	#define MC_SEQ_MISC0_REV_ID_SHIFT 12
556	#define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000
557	#define MC_SEQ_MISC0_REV_ID_VALUE 1
558	#define MC_SEQ_MISC0_GDDR5_SHIFT 28
559	#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
560	#define MC_SEQ_MISC0_GDDR5_VALUE 5
561	#define MC_SEQ_MISC1 0x2a04
562	#define MC_SEQ_RESERVE_M 0x2a08
563	#define MC_PMG_CMD_EMRS 0x2a0c
564
565	#define MC_SEQ_IO_DEBUG_INDEX 0x2a44
566	#define MC_SEQ_IO_DEBUG_DATA 0x2a48
567
568	#define MC_SEQ_MISC5 0x2a54
569	#define MC_SEQ_MISC6 0x2a58
570
571	#define MC_SEQ_MISC7 0x2a64
572
573	#define MC_SEQ_RAS_TIMING_LP 0x2a6c
574	#define MC_SEQ_CAS_TIMING_LP 0x2a70
575	#define MC_SEQ_MISC_TIMING_LP 0x2a74
576	#define MC_SEQ_MISC_TIMING2_LP 0x2a78
577	#define MC_SEQ_WR_CTL_D0_LP 0x2a7c
578	#define MC_SEQ_WR_CTL_D1_LP 0x2a80
579	#define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
580	#define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
581
582	#define MC_PMG_CMD_MRS 0x2aac
583
584	#define MC_SEQ_RD_CTL_D0_LP 0x2b1c
585	#define MC_SEQ_RD_CTL_D1_LP 0x2b20
586
587	#define MC_PMG_CMD_MRS1 0x2b44
588	#define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
589	#define MC_SEQ_PMG_TIMING_LP 0x2b4c
590
591	#define MC_SEQ_WR_CTL_2 0x2b54
592	#define MC_SEQ_WR_CTL_2_LP 0x2b58
593	#define MC_PMG_CMD_MRS2 0x2b5c
594	#define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60
595
596	#define MCLK_PWRMGT_CNTL 0x2ba0
597	# define DLL_SPEED(x) ((x) << 0)
598	# define DLL_SPEED_MASK (0x1f << 0)
599	# define DLL_READY (1 << 6)
600	# define MC_INT_CNTL (1 << 7)
601	# define MRDCK0_PDNB (1 << 8)
602	# define MRDCK1_PDNB (1 << 9)
603	# define MRDCK0_RESET (1 << 16)
604	# define MRDCK1_RESET (1 << 17)
605	# define DLL_READY_READ (1 << 24)
606	#define DLL_CNTL 0x2ba4
607	# define MRDCK0_BYPASS (1 << 24)
608	# define MRDCK1_BYPASS (1 << 25)
609
610	#define MPLL_CNTL_MODE 0x2bb0
611	# define MPLL_MCLK_SEL (1 << 11)
612	#define MPLL_FUNC_CNTL 0x2bb4
613	#define BWCTRL(x) ((x) << 20)
614	#define BWCTRL_MASK (0xff << 20)
615	#define MPLL_FUNC_CNTL_1 0x2bb8
616	#define VCO_MODE(x) ((x) << 0)
617	#define VCO_MODE_MASK (3 << 0)
618	#define CLKFRAC(x) ((x) << 4)
619	#define CLKFRAC_MASK (0xfff << 4)
620	#define CLKF(x) ((x) << 16)
621	#define CLKF_MASK (0xfff << 16)
622	#define MPLL_FUNC_CNTL_2 0x2bbc
623	#define MPLL_AD_FUNC_CNTL 0x2bc0
624	#define YCLK_POST_DIV(x) ((x) << 0)
625	#define YCLK_POST_DIV_MASK (7 << 0)
626	#define MPLL_DQ_FUNC_CNTL 0x2bc4
627	#define YCLK_SEL(x) ((x) << 4)
628	#define YCLK_SEL_MASK (1 << 4)
629
630	#define MPLL_SS1 0x2bcc
631	#define CLKV(x) ((x) << 0)
632	#define CLKV_MASK (0x3ffffff << 0)
633	#define MPLL_SS2 0x2bd0
634	#define CLKS(x) ((x) << 0)
635	#define CLKS_MASK (0xfff << 0)
636
637	#define HDP_HOST_PATH_CNTL 0x2C00
638	#define CLOCK_GATING_DIS (1 << 23)
639	#define HDP_NONSURFACE_BASE 0x2C04
640	#define HDP_NONSURFACE_INFO 0x2C08
641	#define HDP_NONSURFACE_SIZE 0x2C0C
642
643	#define HDP_ADDR_CONFIG 0x2F48
644	#define HDP_MISC_CNTL 0x2F4C
645	#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
646	#define HDP_MEM_POWER_LS 0x2F50
647	#define HDP_LS_ENABLE (1 << 0)
648
649	#define ATC_MISC_CG 0x3350
650
651	#define IH_RB_CNTL 0x3e00
652	# define IH_RB_ENABLE (1 << 0)
653	# define IH_IB_SIZE(x) ((x) << 1) /* log2 */
654	# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
655	# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
656	# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
657	# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
658	# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
659	#define IH_RB_BASE 0x3e04
660	#define IH_RB_RPTR 0x3e08
661	#define IH_RB_WPTR 0x3e0c
662	# define RB_OVERFLOW (1 << 0)
663	# define WPTR_OFFSET_MASK 0x3fffc
664	#define IH_RB_WPTR_ADDR_HI 0x3e10
665	#define IH_RB_WPTR_ADDR_LO 0x3e14
666	#define IH_CNTL 0x3e18
667	# define ENABLE_INTR (1 << 0)
668	# define IH_MC_SWAP(x) ((x) << 1)
669	# define IH_MC_SWAP_NONE 0
670	# define IH_MC_SWAP_16BIT 1
671	# define IH_MC_SWAP_32BIT 2
672	# define IH_MC_SWAP_64BIT 3
673	# define RPTR_REARM (1 << 4)
674	# define MC_WRREQ_CREDIT(x) ((x) << 15)
675	# define MC_WR_CLEAN_CNT(x) ((x) << 20)
676	# define MC_VMID(x) ((x) << 25)
677
678	#define CONFIG_MEMSIZE 0x5428
679
680	#define INTERRUPT_CNTL 0x5468
681	# define IH_DUMMY_RD_OVERRIDE (1 << 0)
682	# define IH_DUMMY_RD_EN (1 << 1)
683	# define IH_REQ_NONSNOOP_EN (1 << 3)
684	# define GEN_IH_INT_EN (1 << 8)
685	#define INTERRUPT_CNTL2 0x546c
686
687	#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
688
689	#define BIF_FB_EN 0x5490
690	#define FB_READ_EN (1 << 0)
691	#define FB_WRITE_EN (1 << 1)
692
693	#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
694
695	/* DCE6 ELD audio interface */
696	#define AZ_F0_CODEC_ENDPOINT_INDEX 0x5E00
697	# define AZ_ENDPOINT_REG_INDEX(x) (((x) & 0xff) << 0)
698	# define AZ_ENDPOINT_REG_WRITE_EN (1 << 8)
699	#define AZ_F0_CODEC_ENDPOINT_DATA 0x5E04
700
701	#define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25
702	#define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0)
703	#define SPEAKER_ALLOCATION_MASK (0x7f << 0)
704	#define SPEAKER_ALLOCATION_SHIFT 0
705	#define HDMI_CONNECTION (1 << 16)
706	#define DP_CONNECTION (1 << 17)
707
708	#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 /* LPCM */
709	#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 /* AC3 */
710	#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2A /* MPEG1 */
711	#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2B /* MP3 */
712	#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2C /* MPEG2 */
713	#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2D /* AAC */
714	#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2E /* DTS */
715	#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2F /* ATRAC */
716	#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 /* one bit audio - leave at 0 (default) */
717	#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 /* Dolby Digital */
718	#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 /* DTS-HD */
719	#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 /* MAT-MLP */
720	#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 /* DTS */
721	#define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 /* WMA Pro */
722	# define MAX_CHANNELS(x) (((x) & 0x7) << 0)
723	/* max channels minus one. 7 = 8 channels */
724	# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)
725	# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)
726	# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */
727	/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
728	* bit0 = 32 kHz
729	* bit1 = 44.1 kHz
730	* bit2 = 48 kHz
731	* bit3 = 88.2 kHz
732	* bit4 = 96 kHz
733	* bit5 = 176.4 kHz
734	* bit6 = 192 kHz
735	*/
736
737	#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37
738	# define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)
739	# define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)
740	/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
741	* 0 = invalid
742	* x = legal delay value
743	* 255 = sync not supported
744	*/
745	#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38
746	# define HBR_CAPABLE (1 << 0) /* enabled by default */
747
748	#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a
749	# define MANUFACTURER_ID(x) (((x) & 0xffff) << 0)
750	# define PRODUCT_ID(x) (((x) & 0xffff) << 16)
751	#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b
752	# define SINK_DESCRIPTION_LEN(x) (((x) & 0xff) << 0)
753	#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c
754	# define PORT_ID0(x) (((x) & 0xffffffff) << 0)
755	#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d
756	# define PORT_ID1(x) (((x) & 0xffffffff) << 0)
757	#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e
758	# define DESCRIPTION0(x) (((x) & 0xff) << 0)
759	# define DESCRIPTION1(x) (((x) & 0xff) << 8)
760	# define DESCRIPTION2(x) (((x) & 0xff) << 16)
761	# define DESCRIPTION3(x) (((x) & 0xff) << 24)
762	#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f
763	# define DESCRIPTION4(x) (((x) & 0xff) << 0)
764	# define DESCRIPTION5(x) (((x) & 0xff) << 8)
765	# define DESCRIPTION6(x) (((x) & 0xff) << 16)
766	# define DESCRIPTION7(x) (((x) & 0xff) << 24)
767	#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40
768	# define DESCRIPTION8(x) (((x) & 0xff) << 0)
769	# define DESCRIPTION9(x) (((x) & 0xff) << 8)
770	# define DESCRIPTION10(x) (((x) & 0xff) << 16)
771	# define DESCRIPTION11(x) (((x) & 0xff) << 24)
772	#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41
773	# define DESCRIPTION12(x) (((x) & 0xff) << 0)
774	# define DESCRIPTION13(x) (((x) & 0xff) << 8)
775	# define DESCRIPTION14(x) (((x) & 0xff) << 16)
776	# define DESCRIPTION15(x) (((x) & 0xff) << 24)
777	#define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42
778	# define DESCRIPTION16(x) (((x) & 0xff) << 0)
779	# define DESCRIPTION17(x) (((x) & 0xff) << 8)
780
781	#define AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54
782	# define AUDIO_ENABLED (1 << 31)
783
784	#define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56
785	#define PORT_CONNECTIVITY_MASK (3 << 30)
786	#define PORT_CONNECTIVITY_SHIFT 30
787
788	#define DC_LB_MEMORY_SPLIT 0x6b0c
789	#define DC_LB_MEMORY_CONFIG(x) ((x) << 20)
790
791	#define PRIORITY_A_CNT 0x6b18
792	#define PRIORITY_MARK_MASK 0x7fff
793	#define PRIORITY_OFF (1 << 16)
794	#define PRIORITY_ALWAYS_ON (1 << 20)
795	#define PRIORITY_B_CNT 0x6b1c
796
797	#define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8
798	# define LATENCY_WATERMARK_MASK(x) ((x) << 16)
799	#define DPG_PIPE_LATENCY_CONTROL 0x6ccc
800	# define LATENCY_LOW_WATERMARK(x) ((x) << 0)
801	# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
802
803	/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
804	#define VLINE_STATUS 0x6bb8
805	# define VLINE_OCCURRED (1 << 0)
806	# define VLINE_ACK (1 << 4)
807	# define VLINE_STAT (1 << 12)
808	# define VLINE_INTERRUPT (1 << 16)
809	# define VLINE_INTERRUPT_TYPE (1 << 17)
810	/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
811	#define VBLANK_STATUS 0x6bbc
812	# define VBLANK_OCCURRED (1 << 0)
813	# define VBLANK_ACK (1 << 4)
814	# define VBLANK_STAT (1 << 12)
815	# define VBLANK_INTERRUPT (1 << 16)
816	# define VBLANK_INTERRUPT_TYPE (1 << 17)
817
818	/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
819	#define INT_MASK 0x6b40
820	# define VBLANK_INT_MASK (1 << 0)
821	# define VLINE_INT_MASK (1 << 4)
822
823	#define DISP_INTERRUPT_STATUS 0x60f4
824	# define LB_D1_VLINE_INTERRUPT (1 << 2)
825	# define LB_D1_VBLANK_INTERRUPT (1 << 3)
826	# define DC_HPD1_INTERRUPT (1 << 17)
827	# define DC_HPD1_RX_INTERRUPT (1 << 18)
828	# define DACA_AUTODETECT_INTERRUPT (1 << 22)
829	# define DACB_AUTODETECT_INTERRUPT (1 << 23)
830	# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
831	# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
832	#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
833	# define LB_D2_VLINE_INTERRUPT (1 << 2)
834	# define LB_D2_VBLANK_INTERRUPT (1 << 3)
835	# define DC_HPD2_INTERRUPT (1 << 17)
836	# define DC_HPD2_RX_INTERRUPT (1 << 18)
837	# define DISP_TIMER_INTERRUPT (1 << 24)
838	#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
839	# define LB_D3_VLINE_INTERRUPT (1 << 2)
840	# define LB_D3_VBLANK_INTERRUPT (1 << 3)
841	# define DC_HPD3_INTERRUPT (1 << 17)
842	# define DC_HPD3_RX_INTERRUPT (1 << 18)
843	#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
844	# define LB_D4_VLINE_INTERRUPT (1 << 2)
845	# define LB_D4_VBLANK_INTERRUPT (1 << 3)
846	# define DC_HPD4_INTERRUPT (1 << 17)
847	# define DC_HPD4_RX_INTERRUPT (1 << 18)
848	#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
849	# define LB_D5_VLINE_INTERRUPT (1 << 2)
850	# define LB_D5_VBLANK_INTERRUPT (1 << 3)
851	# define DC_HPD5_INTERRUPT (1 << 17)
852	# define DC_HPD5_RX_INTERRUPT (1 << 18)
853	#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
854	# define LB_D6_VLINE_INTERRUPT (1 << 2)
855	# define LB_D6_VBLANK_INTERRUPT (1 << 3)
856	# define DC_HPD6_INTERRUPT (1 << 17)
857	# define DC_HPD6_RX_INTERRUPT (1 << 18)
858
859	/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
860	#define GRPH_INT_STATUS 0x6858
861	# define GRPH_PFLIP_INT_OCCURRED (1 << 0)
862	# define GRPH_PFLIP_INT_CLEAR (1 << 8)
863	/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
864	#define GRPH_INT_CONTROL 0x685c
865	# define GRPH_PFLIP_INT_MASK (1 << 0)
866	# define GRPH_PFLIP_INT_TYPE (1 << 8)
867
868	#define DAC_AUTODETECT_INT_CONTROL 0x67c8
869
870	#define DC_HPD1_INT_STATUS 0x601c
871	#define DC_HPD2_INT_STATUS 0x6028
872	#define DC_HPD3_INT_STATUS 0x6034
873	#define DC_HPD4_INT_STATUS 0x6040
874	#define DC_HPD5_INT_STATUS 0x604c
875	#define DC_HPD6_INT_STATUS 0x6058
876	# define DC_HPDx_INT_STATUS (1 << 0)
877	# define DC_HPDx_SENSE (1 << 1)
878	# define DC_HPDx_RX_INT_STATUS (1 << 8)
879
880	#define DC_HPD1_INT_CONTROL 0x6020
881	#define DC_HPD2_INT_CONTROL 0x602c
882	#define DC_HPD3_INT_CONTROL 0x6038
883	#define DC_HPD4_INT_CONTROL 0x6044
884	#define DC_HPD5_INT_CONTROL 0x6050
885	#define DC_HPD6_INT_CONTROL 0x605c
886	# define DC_HPDx_INT_ACK (1 << 0)
887	# define DC_HPDx_INT_POLARITY (1 << 8)
888	# define DC_HPDx_INT_EN (1 << 16)
889	# define DC_HPDx_RX_INT_ACK (1 << 20)
890	# define DC_HPDx_RX_INT_EN (1 << 24)
891
892	#define DC_HPD1_CONTROL 0x6024
893	#define DC_HPD2_CONTROL 0x6030
894	#define DC_HPD3_CONTROL 0x603c
895	#define DC_HPD4_CONTROL 0x6048
896	#define DC_HPD5_CONTROL 0x6054
897	#define DC_HPD6_CONTROL 0x6060
898	# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
899	# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
900	# define DC_HPDx_EN (1 << 28)
901
902	#define DPG_PIPE_STUTTER_CONTROL 0x6cd4
903	# define STUTTER_ENABLE (1 << 0)
904
905	/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
906	#define CRTC_STATUS_FRAME_COUNT 0x6e98
907
908	/* Audio clocks */
909	#define DCCG_AUDIO_DTO_SOURCE 0x05ac
910	# define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */
911	# define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */
912
913	#define DCCG_AUDIO_DTO0_PHASE 0x05b0
914	#define DCCG_AUDIO_DTO0_MODULE 0x05b4
915	#define DCCG_AUDIO_DTO1_PHASE 0x05c0
916	#define DCCG_AUDIO_DTO1_MODULE 0x05c4
917
918	#define DENTIST_DISPCLK_CNTL 0x0490
919	# define DENTIST_DPREFCLK_WDIVIDER(x) (((x) & 0x7f) << 24)
920	# define DENTIST_DPREFCLK_WDIVIDER_MASK (0x7f << 24)
921	# define DENTIST_DPREFCLK_WDIVIDER_SHIFT 24
922
923	#define AFMT_AUDIO_SRC_CONTROL 0x713c
924	#define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0)
925	/* AFMT_AUDIO_SRC_SELECT
926	* 0 = stream0
927	* 1 = stream1
928	* 2 = stream2
929	* 3 = stream3
930	* 4 = stream4
931	* 5 = stream5
932	*/
933
934	#define GRBM_CNTL 0x8000
935	#define GRBM_READ_TIMEOUT(x) ((x) << 0)
936
937	#define GRBM_STATUS2 0x8008
938	#define RLC_RQ_PENDING (1 << 0)
939	#define RLC_BUSY (1 << 8)
940	#define TC_BUSY (1 << 9)
941
942	#define GRBM_STATUS 0x8010
943	#define CMDFIFO_AVAIL_MASK 0x0000000F
944	#define RING2_RQ_PENDING (1 << 4)
945	#define SRBM_RQ_PENDING (1 << 5)
946	#define RING1_RQ_PENDING (1 << 6)
947	#define CF_RQ_PENDING (1 << 7)
948	#define PF_RQ_PENDING (1 << 8)
949	#define GDS_DMA_RQ_PENDING (1 << 9)
950	#define GRBM_EE_BUSY (1 << 10)
951	#define DB_CLEAN (1 << 12)
952	#define CB_CLEAN (1 << 13)
953	#define TA_BUSY (1 << 14)
954	#define GDS_BUSY (1 << 15)
955	#define VGT_BUSY (1 << 17)
956	#define IA_BUSY_NO_DMA (1 << 18)
957	#define IA_BUSY (1 << 19)
958	#define SX_BUSY (1 << 20)
959	#define SPI_BUSY (1 << 22)
960	#define BCI_BUSY (1 << 23)
961	#define SC_BUSY (1 << 24)
962	#define PA_BUSY (1 << 25)
963	#define DB_BUSY (1 << 26)
964	#define CP_COHERENCY_BUSY (1 << 28)
965	#define CP_BUSY (1 << 29)
966	#define CB_BUSY (1 << 30)
967	#define GUI_ACTIVE (1 << 31)
968	#define GRBM_STATUS_SE0 0x8014
969	#define GRBM_STATUS_SE1 0x8018
970	#define SE_DB_CLEAN (1 << 1)
971	#define SE_CB_CLEAN (1 << 2)
972	#define SE_BCI_BUSY (1 << 22)
973	#define SE_VGT_BUSY (1 << 23)
974	#define SE_PA_BUSY (1 << 24)
975	#define SE_TA_BUSY (1 << 25)
976	#define SE_SX_BUSY (1 << 26)
977	#define SE_SPI_BUSY (1 << 27)
978	#define SE_SC_BUSY (1 << 29)
979	#define SE_DB_BUSY (1 << 30)
980	#define SE_CB_BUSY (1 << 31)
981
982	#define GRBM_SOFT_RESET 0x8020
983	#define SOFT_RESET_CP (1 << 0)
984	#define SOFT_RESET_CB (1 << 1)
985	#define SOFT_RESET_RLC (1 << 2)
986	#define SOFT_RESET_DB (1 << 3)
987	#define SOFT_RESET_GDS (1 << 4)
988	#define SOFT_RESET_PA (1 << 5)
989	#define SOFT_RESET_SC (1 << 6)
990	#define SOFT_RESET_BCI (1 << 7)
991	#define SOFT_RESET_SPI (1 << 8)
992	#define SOFT_RESET_SX (1 << 10)
993	#define SOFT_RESET_TC (1 << 11)
994	#define SOFT_RESET_TA (1 << 12)
995	#define SOFT_RESET_VGT (1 << 14)
996	#define SOFT_RESET_IA (1 << 15)
997
998	#define GRBM_GFX_INDEX 0x802C
999	#define INSTANCE_INDEX(x) ((x) << 0)
1000	#define SH_INDEX(x) ((x) << 8)
1001	#define SE_INDEX(x) ((x) << 16)
1002	#define SH_BROADCAST_WRITES (1 << 29)
1003	#define INSTANCE_BROADCAST_WRITES (1 << 30)
1004	#define SE_BROADCAST_WRITES (1 << 31)
1005
1006	#define GRBM_INT_CNTL 0x8060
1007	# define RDERR_INT_ENABLE (1 << 0)
1008	# define GUI_IDLE_INT_ENABLE (1 << 19)
1009
1010	#define CP_STRMOUT_CNTL 0x84FC
1011	#define SCRATCH_REG0 0x8500
1012	#define SCRATCH_REG1 0x8504
1013	#define SCRATCH_REG2 0x8508
1014	#define SCRATCH_REG3 0x850C
1015	#define SCRATCH_REG4 0x8510
1016	#define SCRATCH_REG5 0x8514
1017	#define SCRATCH_REG6 0x8518
1018	#define SCRATCH_REG7 0x851C
1019
1020	#define SCRATCH_UMSK 0x8540
1021	#define SCRATCH_ADDR 0x8544
1022
1023	#define CP_SEM_WAIT_TIMER 0x85BC
1024
1025	#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
1026
1027	#define CP_ME_CNTL 0x86D8
1028	#define CP_CE_HALT (1 << 24)
1029	#define CP_PFP_HALT (1 << 26)
1030	#define CP_ME_HALT (1 << 28)
1031
1032	#define CP_COHER_CNTL2 0x85E8
1033
1034	#define CP_RB2_RPTR 0x86f8
1035	#define CP_RB1_RPTR 0x86fc
1036	#define CP_RB0_RPTR 0x8700
1037	#define CP_RB_WPTR_DELAY 0x8704
1038
1039	#define CP_QUEUE_THRESHOLDS 0x8760
1040	#define ROQ_IB1_START(x) ((x) << 0)
1041	#define ROQ_IB2_START(x) ((x) << 8)
1042	#define CP_MEQ_THRESHOLDS 0x8764
1043	#define MEQ1_START(x) ((x) << 0)
1044	#define MEQ2_START(x) ((x) << 8)
1045
1046	#define CP_PERFMON_CNTL 0x87FC
1047
1048	#define VGT_VTX_VECT_EJECT_REG 0x88B0
1049
1050	#define VGT_CACHE_INVALIDATION 0x88C4
1051	#define CACHE_INVALIDATION(x) ((x) << 0)
1052	#define VC_ONLY 0
1053	#define TC_ONLY 1
1054	#define VC_AND_TC 2
1055	#define AUTO_INVLD_EN(x) ((x) << 6)
1056	#define NO_AUTO 0
1057	#define ES_AUTO 1
1058	#define GS_AUTO 2
1059	#define ES_AND_GS_AUTO 3
1060	#define VGT_ESGS_RING_SIZE 0x88C8
1061	#define VGT_GSVS_RING_SIZE 0x88CC
1062
1063	#define VGT_GS_VERTEX_REUSE 0x88D4
1064
1065	#define VGT_PRIMITIVE_TYPE 0x8958
1066	#define VGT_INDEX_TYPE 0x895C
1067
1068	#define VGT_NUM_INDICES 0x8970
1069	#define VGT_NUM_INSTANCES 0x8974
1070
1071	#define VGT_TF_RING_SIZE 0x8988
1072
1073	#define VGT_HS_OFFCHIP_PARAM 0x89B0
1074
1075	#define VGT_TF_MEMORY_BASE 0x89B8
1076
1077	#define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
1078	#define INACTIVE_CUS_MASK 0xFFFF0000
1079	#define INACTIVE_CUS_SHIFT 16
1080	#define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
1081
1082	#define PA_CL_ENHANCE 0x8A14
1083	#define CLIP_VTX_REORDER_ENA (1 << 0)
1084	#define NUM_CLIP_SEQ(x) ((x) << 1)
1085
1086	#define PA_SU_LINE_STIPPLE_VALUE 0x8A60
1087
1088	#define PA_SC_LINE_STIPPLE_STATE 0x8B10
1089
1090	#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
1091	#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1092	#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1093
1094	#define PA_SC_FIFO_SIZE 0x8BCC
1095	#define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
1096	#define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
1097	#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
1098	#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
1099
1100	#define PA_SC_ENHANCE 0x8BF0
1101
1102	#define SQ_CONFIG 0x8C00
1103
1104	#define SQC_CACHES 0x8C08
1105
1106	#define SQ_POWER_THROTTLE 0x8e58
1107	#define MIN_POWER(x) ((x) << 0)
1108	#define MIN_POWER_MASK (0x3fff << 0)
1109	#define MIN_POWER_SHIFT 0
1110	#define MAX_POWER(x) ((x) << 16)
1111	#define MAX_POWER_MASK (0x3fff << 16)
1112	#define MAX_POWER_SHIFT 0
1113	#define SQ_POWER_THROTTLE2 0x8e5c
1114	#define MAX_POWER_DELTA(x) ((x) << 0)
1115	#define MAX_POWER_DELTA_MASK (0x3fff << 0)
1116	#define MAX_POWER_DELTA_SHIFT 0
1117	#define STI_SIZE(x) ((x) << 16)
1118	#define STI_SIZE_MASK (0x3ff << 16)
1119	#define STI_SIZE_SHIFT 16
1120	#define LTI_RATIO(x) ((x) << 27)
1121	#define LTI_RATIO_MASK (0xf << 27)
1122	#define LTI_RATIO_SHIFT 27
1123
1124	#define SX_DEBUG_1 0x9060
1125
1126	#define SPI_STATIC_THREAD_MGMT_1 0x90E0
1127	#define SPI_STATIC_THREAD_MGMT_2 0x90E4
1128	#define SPI_STATIC_THREAD_MGMT_3 0x90E8
1129	#define SPI_PS_MAX_WAVE_ID 0x90EC
1130
1131	#define SPI_CONFIG_CNTL 0x9100
1132
1133	#define SPI_CONFIG_CNTL_1 0x913C
1134	#define VTX_DONE_DELAY(x) ((x) << 0)
1135	#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
1136
1137	#define CGTS_TCC_DISABLE 0x9148
1138	#define CGTS_USER_TCC_DISABLE 0x914C
1139	#define TCC_DISABLE_MASK 0xFFFF0000
1140	#define TCC_DISABLE_SHIFT 16
1141	#define CGTS_SM_CTRL_REG 0x9150
1142	#define OVERRIDE (1 << 21)
1143	#define LS_OVERRIDE (1 << 22)
1144
1145	#define SPI_LB_CU_MASK 0x9354
1146
1147	#define TA_CNTL_AUX 0x9508
1148	#define TA_CS_BC_BASE_ADDR 0x950C
1149
1150	#define CC_RB_BACKEND_DISABLE 0x98F4
1151	#define BACKEND_DISABLE(x) ((x) << 16)
1152	#define GB_ADDR_CONFIG 0x98F8
1153	#define NUM_PIPES(x) ((x) << 0)
1154	#define NUM_PIPES_MASK 0x00000007
1155	#define NUM_PIPES_SHIFT 0
1156	#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
1157	#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
1158	#define PIPE_INTERLEAVE_SIZE_SHIFT 4
1159	#define NUM_SHADER_ENGINES(x) ((x) << 12)
1160	#define NUM_SHADER_ENGINES_MASK 0x00003000
1161	#define NUM_SHADER_ENGINES_SHIFT 12
1162	#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
1163	#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
1164	#define SHADER_ENGINE_TILE_SIZE_SHIFT 16
1165	#define NUM_GPUS(x) ((x) << 20)
1166	#define NUM_GPUS_MASK 0x00700000
1167	#define NUM_GPUS_SHIFT 20
1168	#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
1169	#define MULTI_GPU_TILE_SIZE_MASK 0x03000000
1170	#define MULTI_GPU_TILE_SIZE_SHIFT 24
1171	#define ROW_SIZE(x) ((x) << 28)
1172	#define ROW_SIZE_MASK 0x30000000
1173	#define ROW_SIZE_SHIFT 28
1174
1175	#define GB_TILE_MODE0 0x9910
1176	# define MICRO_TILE_MODE(x) ((x) << 0)
1177	# define ADDR_SURF_DISPLAY_MICRO_TILING 0
1178	# define ADDR_SURF_THIN_MICRO_TILING 1
1179	# define ADDR_SURF_DEPTH_MICRO_TILING 2
1180	# define ARRAY_MODE(x) ((x) << 2)
1181	# define ARRAY_LINEAR_GENERAL 0
1182	# define ARRAY_LINEAR_ALIGNED 1
1183	# define ARRAY_1D_TILED_THIN1 2
1184	# define ARRAY_2D_TILED_THIN1 4
1185	# define PIPE_CONFIG(x) ((x) << 6)
1186	# define ADDR_SURF_P2 0
1187	# define ADDR_SURF_P4_8x16 4
1188	# define ADDR_SURF_P4_16x16 5
1189	# define ADDR_SURF_P4_16x32 6
1190	# define ADDR_SURF_P4_32x32 7
1191	# define ADDR_SURF_P8_16x16_8x16 8
1192	# define ADDR_SURF_P8_16x32_8x16 9
1193	# define ADDR_SURF_P8_32x32_8x16 10
1194	# define ADDR_SURF_P8_16x32_16x16 11
1195	# define ADDR_SURF_P8_32x32_16x16 12
1196	# define ADDR_SURF_P8_32x32_16x32 13
1197	# define ADDR_SURF_P8_32x64_32x32 14
1198	# define TILE_SPLIT(x) ((x) << 11)
1199	# define ADDR_SURF_TILE_SPLIT_64B 0
1200	# define ADDR_SURF_TILE_SPLIT_128B 1
1201	# define ADDR_SURF_TILE_SPLIT_256B 2
1202	# define ADDR_SURF_TILE_SPLIT_512B 3
1203	# define ADDR_SURF_TILE_SPLIT_1KB 4
1204	# define ADDR_SURF_TILE_SPLIT_2KB 5
1205	# define ADDR_SURF_TILE_SPLIT_4KB 6
1206	# define BANK_WIDTH(x) ((x) << 14)
1207	# define ADDR_SURF_BANK_WIDTH_1 0
1208	# define ADDR_SURF_BANK_WIDTH_2 1
1209	# define ADDR_SURF_BANK_WIDTH_4 2
1210	# define ADDR_SURF_BANK_WIDTH_8 3
1211	# define BANK_HEIGHT(x) ((x) << 16)
1212	# define ADDR_SURF_BANK_HEIGHT_1 0
1213	# define ADDR_SURF_BANK_HEIGHT_2 1
1214	# define ADDR_SURF_BANK_HEIGHT_4 2
1215	# define ADDR_SURF_BANK_HEIGHT_8 3
1216	# define MACRO_TILE_ASPECT(x) ((x) << 18)
1217	# define ADDR_SURF_MACRO_ASPECT_1 0
1218	# define ADDR_SURF_MACRO_ASPECT_2 1
1219	# define ADDR_SURF_MACRO_ASPECT_4 2
1220	# define ADDR_SURF_MACRO_ASPECT_8 3
1221	# define NUM_BANKS(x) ((x) << 20)
1222	# define ADDR_SURF_2_BANK 0
1223	# define ADDR_SURF_4_BANK 1
1224	# define ADDR_SURF_8_BANK 2
1225	# define ADDR_SURF_16_BANK 3
1226
1227	#define CB_PERFCOUNTER0_SELECT0 0x9a20
1228	#define CB_PERFCOUNTER0_SELECT1 0x9a24
1229	#define CB_PERFCOUNTER1_SELECT0 0x9a28
1230	#define CB_PERFCOUNTER1_SELECT1 0x9a2c
1231	#define CB_PERFCOUNTER2_SELECT0 0x9a30
1232	#define CB_PERFCOUNTER2_SELECT1 0x9a34
1233	#define CB_PERFCOUNTER3_SELECT0 0x9a38
1234	#define CB_PERFCOUNTER3_SELECT1 0x9a3c
1235
1236	#define CB_CGTT_SCLK_CTRL 0x9a60
1237
1238	#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
1239	#define BACKEND_DISABLE_MASK 0x00FF0000
1240	#define BACKEND_DISABLE_SHIFT 16
1241
1242	#define TCP_CHAN_STEER_LO 0xac0c
1243	#define TCP_CHAN_STEER_HI 0xac10
1244
1245	#define CP_RB0_BASE 0xC100
1246	#define CP_RB0_CNTL 0xC104
1247	#define RB_BUFSZ(x) ((x) << 0)
1248	#define RB_BLKSZ(x) ((x) << 8)
1249	#define BUF_SWAP_32BIT (2 << 16)
1250	#define RB_NO_UPDATE (1 << 27)
1251	#define RB_RPTR_WR_ENA (1 << 31)
1252
1253	#define CP_RB0_RPTR_ADDR 0xC10C
1254	#define CP_RB0_RPTR_ADDR_HI 0xC110
1255	#define CP_RB0_WPTR 0xC114
1256
1257	#define CP_PFP_UCODE_ADDR 0xC150
1258	#define CP_PFP_UCODE_DATA 0xC154
1259	#define CP_ME_RAM_RADDR 0xC158
1260	#define CP_ME_RAM_WADDR 0xC15C
1261	#define CP_ME_RAM_DATA 0xC160
1262
1263	#define CP_CE_UCODE_ADDR 0xC168
1264	#define CP_CE_UCODE_DATA 0xC16C
1265
1266	#define CP_RB1_BASE 0xC180
1267	#define CP_RB1_CNTL 0xC184
1268	#define CP_RB1_RPTR_ADDR 0xC188
1269	#define CP_RB1_RPTR_ADDR_HI 0xC18C
1270	#define CP_RB1_WPTR 0xC190
1271	#define CP_RB2_BASE 0xC194
1272	#define CP_RB2_CNTL 0xC198
1273	#define CP_RB2_RPTR_ADDR 0xC19C
1274	#define CP_RB2_RPTR_ADDR_HI 0xC1A0
1275	#define CP_RB2_WPTR 0xC1A4
1276	#define CP_INT_CNTL_RING0 0xC1A8
1277	#define CP_INT_CNTL_RING1 0xC1AC
1278	#define CP_INT_CNTL_RING2 0xC1B0
1279	# define CNTX_BUSY_INT_ENABLE (1 << 19)
1280	# define CNTX_EMPTY_INT_ENABLE (1 << 20)
1281	# define WAIT_MEM_SEM_INT_ENABLE (1 << 21)
1282	# define TIME_STAMP_INT_ENABLE (1 << 26)
1283	# define CP_RINGID2_INT_ENABLE (1 << 29)
1284	# define CP_RINGID1_INT_ENABLE (1 << 30)
1285	# define CP_RINGID0_INT_ENABLE (1 << 31)
1286	#define CP_INT_STATUS_RING0 0xC1B4
1287	#define CP_INT_STATUS_RING1 0xC1B8
1288	#define CP_INT_STATUS_RING2 0xC1BC
1289	# define WAIT_MEM_SEM_INT_STAT (1 << 21)
1290	# define TIME_STAMP_INT_STAT (1 << 26)
1291	# define CP_RINGID2_INT_STAT (1 << 29)
1292	# define CP_RINGID1_INT_STAT (1 << 30)
1293	# define CP_RINGID0_INT_STAT (1 << 31)
1294
1295	#define CP_MEM_SLP_CNTL 0xC1E4
1296	# define CP_MEM_LS_EN (1 << 0)
1297
1298	#define CP_DEBUG 0xC1FC
1299
1300	#define RLC_CNTL 0xC300
1301	# define RLC_ENABLE (1 << 0)
1302	#define RLC_RL_BASE 0xC304
1303	#define RLC_RL_SIZE 0xC308
1304	#define RLC_LB_CNTL 0xC30C
1305	# define LOAD_BALANCE_ENABLE (1 << 0)
1306	#define RLC_SAVE_AND_RESTORE_BASE 0xC310
1307	#define RLC_LB_CNTR_MAX 0xC314
1308	#define RLC_LB_CNTR_INIT 0xC318
1309
1310	#define RLC_CLEAR_STATE_RESTORE_BASE 0xC320
1311
1312	#define RLC_UCODE_ADDR 0xC32C
1313	#define RLC_UCODE_DATA 0xC330
1314
1315	#define RLC_GPU_CLOCK_COUNT_LSB 0xC338
1316	#define RLC_GPU_CLOCK_COUNT_MSB 0xC33C
1317	#define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340
1318	#define RLC_MC_CNTL 0xC344
1319	#define RLC_UCODE_CNTL 0xC348
1320	#define RLC_STAT 0xC34C
1321	# define RLC_BUSY_STATUS (1 << 0)
1322	# define GFX_POWER_STATUS (1 << 1)
1323	# define GFX_CLOCK_STATUS (1 << 2)
1324	# define GFX_LS_STATUS (1 << 3)
1325
1326	#define RLC_PG_CNTL 0xC35C
1327	# define GFX_PG_ENABLE (1 << 0)
1328	# define GFX_PG_SRC (1 << 1)
1329
1330	#define RLC_CGTT_MGCG_OVERRIDE 0xC400
1331	#define RLC_CGCG_CGLS_CTRL 0xC404
1332	# define CGCG_EN (1 << 0)
1333	# define CGLS_EN (1 << 1)
1334
1335	#define RLC_TTOP_D 0xC414
1336	# define RLC_PUD(x) ((x) << 0)
1337	# define RLC_PUD_MASK (0xff << 0)
1338	# define RLC_PDD(x) ((x) << 8)
1339	# define RLC_PDD_MASK (0xff << 8)
1340	# define RLC_TTPD(x) ((x) << 16)
1341	# define RLC_TTPD_MASK (0xff << 16)
1342	# define RLC_MSD(x) ((x) << 24)
1343	# define RLC_MSD_MASK (0xff << 24)
1344
1345	#define RLC_LB_INIT_CU_MASK 0xC41C
1346
1347	#define RLC_PG_AO_CU_MASK 0xC42C
1348	#define RLC_MAX_PG_CU 0xC430
1349	# define MAX_PU_CU(x) ((x) << 0)
1350	# define MAX_PU_CU_MASK (0xff << 0)
1351	#define RLC_AUTO_PG_CTRL 0xC434
1352	# define AUTO_PG_EN (1 << 0)
1353	# define GRBM_REG_SGIT(x) ((x) << 3)
1354	# define GRBM_REG_SGIT_MASK (0xffff << 3)
1355	# define PG_AFTER_GRBM_REG_ST(x) ((x) << 19)
1356	# define PG_AFTER_GRBM_REG_ST_MASK (0x1fff << 19)
1357
1358	#define RLC_SERDES_WR_MASTER_MASK_0 0xC454
1359	#define RLC_SERDES_WR_MASTER_MASK_1 0xC458
1360	#define RLC_SERDES_WR_CTRL 0xC45C
1361
1362	#define RLC_SERDES_MASTER_BUSY_0 0xC464
1363	#define RLC_SERDES_MASTER_BUSY_1 0xC468
1364
1365	#define RLC_GCPM_GENERAL_3 0xC478
1366
1367	#define DB_RENDER_CONTROL 0x28000
1368
1369	#define DB_DEPTH_INFO 0x2803c
1370
1371	#define PA_SC_RASTER_CONFIG 0x28350
1372	# define RASTER_CONFIG_RB_MAP_0 0
1373	# define RASTER_CONFIG_RB_MAP_1 1
1374	# define RASTER_CONFIG_RB_MAP_2 2
1375	# define RASTER_CONFIG_RB_MAP_3 3
1376
1377	#define VGT_EVENT_INITIATOR 0x28a90
1378	# define SAMPLE_STREAMOUTSTATS1 (1 << 0)
1379	# define SAMPLE_STREAMOUTSTATS2 (2 << 0)
1380	# define SAMPLE_STREAMOUTSTATS3 (3 << 0)
1381	# define CACHE_FLUSH_TS (4 << 0)
1382	# define CACHE_FLUSH (6 << 0)
1383	# define CS_PARTIAL_FLUSH (7 << 0)
1384	# define VGT_STREAMOUT_RESET (10 << 0)
1385	# define END_OF_PIPE_INCR_DE (11 << 0)
1386	# define END_OF_PIPE_IB_END (12 << 0)
1387	# define RST_PIX_CNT (13 << 0)
1388	# define VS_PARTIAL_FLUSH (15 << 0)
1389	# define PS_PARTIAL_FLUSH (16 << 0)
1390	# define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
1391	# define ZPASS_DONE (21 << 0)
1392	# define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
1393	# define PERFCOUNTER_START (23 << 0)
1394	# define PERFCOUNTER_STOP (24 << 0)
1395	# define PIPELINESTAT_START (25 << 0)
1396	# define PIPELINESTAT_STOP (26 << 0)
1397	# define PERFCOUNTER_SAMPLE (27 << 0)
1398	# define SAMPLE_PIPELINESTAT (30 << 0)
1399	# define SAMPLE_STREAMOUTSTATS (32 << 0)
1400	# define RESET_VTX_CNT (33 << 0)
1401	# define VGT_FLUSH (36 << 0)
1402	# define BOTTOM_OF_PIPE_TS (40 << 0)
1403	# define DB_CACHE_FLUSH_AND_INV (42 << 0)
1404	# define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
1405	# define FLUSH_AND_INV_DB_META (44 << 0)
1406	# define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
1407	# define FLUSH_AND_INV_CB_META (46 << 0)
1408	# define CS_DONE (47 << 0)
1409	# define PS_DONE (48 << 0)
1410	# define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
1411	# define THREAD_TRACE_START (51 << 0)
1412	# define THREAD_TRACE_STOP (52 << 0)
1413	# define THREAD_TRACE_FLUSH (54 << 0)
1414	# define THREAD_TRACE_FINISH (55 << 0)
1415
1416	/* PIF PHY0 registers idx/data 0x8/0xc */
1417	#define PB0_PIF_CNTL 0x10
1418	# define LS2_EXIT_TIME(x) ((x) << 17)
1419	# define LS2_EXIT_TIME_MASK (0x7 << 17)
1420	# define LS2_EXIT_TIME_SHIFT 17
1421	#define PB0_PIF_PAIRING 0x11
1422	# define MULTI_PIF (1 << 25)
1423	#define PB0_PIF_PWRDOWN_0 0x12
1424	# define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)
1425	# define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
1426	# define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7
1427	# define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)
1428	# define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
1429	# define PLL_POWER_STATE_IN_OFF_0_SHIFT 10
1430	# define PLL_RAMP_UP_TIME_0(x) ((x) << 24)
1431	# define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
1432	# define PLL_RAMP_UP_TIME_0_SHIFT 24
1433	#define PB0_PIF_PWRDOWN_1 0x13
1434	# define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)
1435	# define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
1436	# define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7
1437	# define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)
1438	# define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
1439	# define PLL_POWER_STATE_IN_OFF_1_SHIFT 10
1440	# define PLL_RAMP_UP_TIME_1(x) ((x) << 24)
1441	# define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
1442	# define PLL_RAMP_UP_TIME_1_SHIFT 24
1443
1444	#define PB0_PIF_PWRDOWN_2 0x17
1445	# define PLL_POWER_STATE_IN_TXS2_2(x) ((x) << 7)
1446	# define PLL_POWER_STATE_IN_TXS2_2_MASK (0x7 << 7)
1447	# define PLL_POWER_STATE_IN_TXS2_2_SHIFT 7
1448	# define PLL_POWER_STATE_IN_OFF_2(x) ((x) << 10)
1449	# define PLL_POWER_STATE_IN_OFF_2_MASK (0x7 << 10)
1450	# define PLL_POWER_STATE_IN_OFF_2_SHIFT 10
1451	# define PLL_RAMP_UP_TIME_2(x) ((x) << 24)
1452	# define PLL_RAMP_UP_TIME_2_MASK (0x7 << 24)
1453	# define PLL_RAMP_UP_TIME_2_SHIFT 24
1454	#define PB0_PIF_PWRDOWN_3 0x18
1455	# define PLL_POWER_STATE_IN_TXS2_3(x) ((x) << 7)
1456	# define PLL_POWER_STATE_IN_TXS2_3_MASK (0x7 << 7)
1457	# define PLL_POWER_STATE_IN_TXS2_3_SHIFT 7
1458	# define PLL_POWER_STATE_IN_OFF_3(x) ((x) << 10)
1459	# define PLL_POWER_STATE_IN_OFF_3_MASK (0x7 << 10)
1460	# define PLL_POWER_STATE_IN_OFF_3_SHIFT 10
1461	# define PLL_RAMP_UP_TIME_3(x) ((x) << 24)
1462	# define PLL_RAMP_UP_TIME_3_MASK (0x7 << 24)
1463	# define PLL_RAMP_UP_TIME_3_SHIFT 24
1464	/* PIF PHY1 registers idx/data 0x10/0x14 */
1465	#define PB1_PIF_CNTL 0x10
1466	#define PB1_PIF_PAIRING 0x11
1467	#define PB1_PIF_PWRDOWN_0 0x12
1468	#define PB1_PIF_PWRDOWN_1 0x13
1469
1470	#define PB1_PIF_PWRDOWN_2 0x17
1471	#define PB1_PIF_PWRDOWN_3 0x18
1472	/* PCIE registers idx/data 0x30/0x34 */
1473	#define PCIE_CNTL2 0x1c /* PCIE */
1474	# define SLV_MEM_LS_EN (1 << 16)
1475	# define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)
1476	# define MST_MEM_LS_EN (1 << 18)
1477	# define REPLAY_MEM_LS_EN (1 << 19)
1478	#define PCIE_LC_STATUS1 0x28 /* PCIE */
1479	# define LC_REVERSE_RCVR (1 << 0)
1480	# define LC_REVERSE_XMIT (1 << 1)
1481	# define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)
1482	# define LC_OPERATING_LINK_WIDTH_SHIFT 2
1483	# define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)
1484	# define LC_DETECTED_LINK_WIDTH_SHIFT 5
1485
1486	#define PCIE_P_CNTL 0x40 /* PCIE */
1487	# define P_IGNORE_EDB_ERR (1 << 6)
1488
1489	/* PCIE PORT registers idx/data 0x38/0x3c */
1490	#define PCIE_LC_CNTL 0xa0
1491	# define LC_L0S_INACTIVITY(x) ((x) << 8)
1492	# define LC_L0S_INACTIVITY_MASK (0xf << 8)
1493	# define LC_L0S_INACTIVITY_SHIFT 8
1494	# define LC_L1_INACTIVITY(x) ((x) << 12)
1495	# define LC_L1_INACTIVITY_MASK (0xf << 12)
1496	# define LC_L1_INACTIVITY_SHIFT 12
1497	# define LC_PMI_TO_L1_DIS (1 << 16)
1498	# define LC_ASPM_TO_L1_DIS (1 << 24)
1499	#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
1500	# define LC_LINK_WIDTH_SHIFT 0
1501	# define LC_LINK_WIDTH_MASK 0x7
1502	# define LC_LINK_WIDTH_X0 0
1503	# define LC_LINK_WIDTH_X1 1
1504	# define LC_LINK_WIDTH_X2 2
1505	# define LC_LINK_WIDTH_X4 3
1506	# define LC_LINK_WIDTH_X8 4
1507	# define LC_LINK_WIDTH_X16 6
1508	# define LC_LINK_WIDTH_RD_SHIFT 4
1509	# define LC_LINK_WIDTH_RD_MASK 0x70
1510	# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
1511	# define LC_RECONFIG_NOW (1 << 8)
1512	# define LC_RENEGOTIATION_SUPPORT (1 << 9)
1513	# define LC_RENEGOTIATE_EN (1 << 10)
1514	# define LC_SHORT_RECONFIG_EN (1 << 11)
1515	# define LC_UPCONFIGURE_SUPPORT (1 << 12)
1516	# define LC_UPCONFIGURE_DIS (1 << 13)
1517	# define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)
1518	# define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
1519	# define LC_DYN_LANES_PWR_STATE_SHIFT 21
1520	#define PCIE_LC_N_FTS_CNTL 0xa3 /* PCIE_P */
1521	# define LC_XMIT_N_FTS(x) ((x) << 0)
1522	# define LC_XMIT_N_FTS_MASK (0xff << 0)
1523	# define LC_XMIT_N_FTS_SHIFT 0
1524	# define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
1525	# define LC_N_FTS_MASK (0xff << 24)
1526	#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
1527	# define LC_GEN2_EN_STRAP (1 << 0)
1528	# define LC_GEN3_EN_STRAP (1 << 1)
1529	# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
1530	# define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)
1531	# define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3
1532	# define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
1533	# define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
1534	# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
1535	# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
1536	# define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
1537	# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)
1538	# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10
1539	# define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
1540	# define LC_CURRENT_DATA_RATE_SHIFT 13
1541	# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
1542	# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
1543	# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
1544	# define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
1545	# define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
1546
1547	#define PCIE_LC_CNTL2 0xb1
1548	# define LC_ALLOW_PDWN_IN_L1 (1 << 17)
1549	# define LC_ALLOW_PDWN_IN_L23 (1 << 18)
1550
1551	#define PCIE_LC_CNTL3 0xb5 /* PCIE_P */
1552	# define LC_GO_TO_RECOVERY (1 << 30)
1553	#define PCIE_LC_CNTL4 0xb6 /* PCIE_P */
1554	# define LC_REDO_EQ (1 << 5)
1555	# define LC_SET_QUIESCE (1 << 13)
1556
1557	/*
1558	* UVD
1559	*/
1560	#define UVD_UDEC_ADDR_CONFIG 0xEF4C
1561	#define UVD_UDEC_DB_ADDR_CONFIG 0xEF50
1562	#define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
1563	#define UVD_NO_OP 0xEFFC
1564	#define UVD_RBC_RB_RPTR 0xF690
1565	#define UVD_RBC_RB_WPTR 0xF694
1566	#define UVD_STATUS 0xf6bc
1567
1568	#define UVD_CGC_CTRL 0xF4B0
1569	# define DCM (1 << 0)
1570	# define CG_DT(x) ((x) << 2)
1571	# define CG_DT_MASK (0xf << 2)
1572	# define CLK_OD(x) ((x) << 6)
1573	# define CLK_OD_MASK (0x1f << 6)
1574
1575	/* UVD CTX indirect */
1576	#define UVD_CGC_MEM_CTRL 0xC0
1577	#define UVD_CGC_CTRL2 0xC1
1578	# define DYN_OR_EN (1 << 0)
1579	# define DYN_RR_EN (1 << 1)
1580	# define G_DIV_ID(x) ((x) << 2)
1581	# define G_DIV_ID_MASK (0x7 << 2)
1582
1583	/*
1584	* PM4
1585	*/
1586	#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
1587	(((reg) >> 2) & 0xFFFF) | \
1588	((n) & 0x3FFF) << 16)
1589	#define CP_PACKET2 0x80000000
1590	#define PACKET2_PAD_SHIFT 0
1591	#define PACKET2_PAD_MASK (0x3fffffff << 0)
1592
1593	#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1594
1595	#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
1596	(((op) & 0xFF) << 8) | \
1597	((n) & 0x3FFF) << 16)
1598
1599	#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
1600
1601	/* Packet 3 types */
1602	#define PACKET3_NOP 0x10
1603	#define PACKET3_SET_BASE 0x11
1604	#define PACKET3_BASE_INDEX(x) ((x) << 0)
1605	#define GDS_PARTITION_BASE 2
1606	#define CE_PARTITION_BASE 3
1607	#define PACKET3_CLEAR_STATE 0x12
1608	#define PACKET3_INDEX_BUFFER_SIZE 0x13
1609	#define PACKET3_DISPATCH_DIRECT 0x15
1610	#define PACKET3_DISPATCH_INDIRECT 0x16
1611	#define PACKET3_ALLOC_GDS 0x1B
1612	#define PACKET3_WRITE_GDS_RAM 0x1C
1613	#define PACKET3_ATOMIC_GDS 0x1D
1614	#define PACKET3_ATOMIC 0x1E
1615	#define PACKET3_OCCLUSION_QUERY 0x1F
1616	#define PACKET3_SET_PREDICATION 0x20
1617	#define PACKET3_REG_RMW 0x21
1618	#define PACKET3_COND_EXEC 0x22
1619	#define PACKET3_PRED_EXEC 0x23
1620	#define PACKET3_DRAW_INDIRECT 0x24
1621	#define PACKET3_DRAW_INDEX_INDIRECT 0x25
1622	#define PACKET3_INDEX_BASE 0x26
1623	#define PACKET3_DRAW_INDEX_2 0x27
1624	#define PACKET3_CONTEXT_CONTROL 0x28
1625	#define PACKET3_INDEX_TYPE 0x2A
1626	#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
1627	#define PACKET3_DRAW_INDEX_AUTO 0x2D
1628	#define PACKET3_DRAW_INDEX_IMMD 0x2E
1629	#define PACKET3_NUM_INSTANCES 0x2F
1630	#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1631	#define PACKET3_INDIRECT_BUFFER_CONST 0x31
1632	#define PACKET3_INDIRECT_BUFFER 0x32
1633	#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1634	#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1635	#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
1636	#define PACKET3_WRITE_DATA 0x37
1637	#define WRITE_DATA_DST_SEL(x) ((x) << 8)
1638	/* 0 - register
1639	* 1 - memory (sync - via GRBM)
1640	* 2 - tc/l2
1641	* 3 - gds
1642	* 4 - reserved
1643	* 5 - memory (async - direct)
1644	*/
1645	#define WR_ONE_ADDR (1 << 16)
1646	#define WR_CONFIRM (1 << 20)
1647	#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
1648	/* 0 - me
1649	* 1 - pfp
1650	* 2 - ce
1651	*/
1652	#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
1653	#define PACKET3_MEM_SEMAPHORE 0x39
1654	#define PACKET3_MPEG_INDEX 0x3A
1655	#define PACKET3_COPY_DW 0x3B
1656	#define PACKET3_WAIT_REG_MEM 0x3C
1657	#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
1658	/* 0 - always
1659	* 1 - <
1660	* 2 - <=
1661	* 3 - ==
1662	* 4 - !=
1663	* 5 - >=
1664	* 6 - >
1665	*/
1666	#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
1667	/* 0 - reg
1668	* 1 - mem
1669	*/
1670	#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
1671	/* 0 - me
1672	* 1 - pfp
1673	*/
1674	#define PACKET3_MEM_WRITE 0x3D
1675	#define PACKET3_COPY_DATA 0x40
1676	#define PACKET3_CP_DMA 0x41
1677	/* 1. header
1678	* 2. SRC_ADDR_LO or DATA [31:0]
1679	* 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
1680	* SRC_ADDR_HI [7:0]
1681	* 4. DST_ADDR_LO [31:0]
1682	* 5. DST_ADDR_HI [7:0]
1683	* 6. COMMAND [30:21] | BYTE_COUNT [20:0]
1684	*/
1685	# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
1686	/* 0 - DST_ADDR
1687	* 1 - GDS
1688	*/
1689	# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
1690	/* 0 - ME
1691	* 1 - PFP
1692	*/
1693	# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
1694	/* 0 - SRC_ADDR
1695	* 1 - GDS
1696	* 2 - DATA
1697	*/
1698	# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
1699	/* COMMAND */
1700	# define PACKET3_CP_DMA_DIS_WC (1 << 21)
1701	# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
1702	/* 0 - none
1703	* 1 - 8 in 16
1704	* 2 - 8 in 32
1705	* 3 - 8 in 64
1706	*/
1707	# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
1708	/* 0 - none
1709	* 1 - 8 in 16
1710	* 2 - 8 in 32
1711	* 3 - 8 in 64
1712	*/
1713	# define PACKET3_CP_DMA_CMD_SAS (1 << 26)
1714	/* 0 - memory
1715	* 1 - register
1716	*/
1717	# define PACKET3_CP_DMA_CMD_DAS (1 << 27)
1718	/* 0 - memory
1719	* 1 - register
1720	*/
1721	# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
1722	# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
1723	# define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)
1724	#define PACKET3_PFP_SYNC_ME 0x42
1725	#define PACKET3_SURFACE_SYNC 0x43
1726	# define PACKET3_DEST_BASE_0_ENA (1 << 0)
1727	# define PACKET3_DEST_BASE_1_ENA (1 << 1)
1728	# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1729	# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1730	# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1731	# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1732	# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1733	# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1734	# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1735	# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1736	# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1737	# define PACKET3_DEST_BASE_2_ENA (1 << 19)
1738	# define PACKET3_DEST_BASE_3_ENA (1 << 21)
1739	# define PACKET3_TCL1_ACTION_ENA (1 << 22)
1740	# define PACKET3_TC_ACTION_ENA (1 << 23)
1741	# define PACKET3_CB_ACTION_ENA (1 << 25)
1742	# define PACKET3_DB_ACTION_ENA (1 << 26)
1743	# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
1744	# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
1745	#define PACKET3_ME_INITIALIZE 0x44
1746	#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1747	#define PACKET3_COND_WRITE 0x45
1748	#define PACKET3_EVENT_WRITE 0x46
1749	#define EVENT_TYPE(x) ((x) << 0)
1750	#define EVENT_INDEX(x) ((x) << 8)
1751	/* 0 - any non-TS event
1752	* 1 - ZPASS_DONE
1753	* 2 - SAMPLE_PIPELINESTAT
1754	* 3 - SAMPLE_STREAMOUTSTAT*
1755	* 4 - *S_PARTIAL_FLUSH
1756	* 5 - EOP events
1757	* 6 - EOS events
1758	* 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
1759	*/
1760	#define INV_L2 (1 << 20)
1761	/* INV TC L2 cache when EVENT_INDEX = 7 */
1762	#define PACKET3_EVENT_WRITE_EOP 0x47
1763	#define DATA_SEL(x) ((x) << 29)
1764	/* 0 - discard
1765	* 1 - send low 32bit data
1766	* 2 - send 64bit data
1767	* 3 - send 64bit counter value
1768	*/
1769	#define INT_SEL(x) ((x) << 24)
1770	/* 0 - none
1771	* 1 - interrupt only (DATA_SEL = 0)
1772	* 2 - interrupt when data write is confirmed
1773	*/
1774	#define PACKET3_EVENT_WRITE_EOS 0x48
1775	#define PACKET3_PREAMBLE_CNTL 0x4A
1776	# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
1777	# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
1778	#define PACKET3_ONE_REG_WRITE 0x57
1779	#define PACKET3_LOAD_CONFIG_REG 0x5F
1780	#define PACKET3_LOAD_CONTEXT_REG 0x60
1781	#define PACKET3_LOAD_SH_REG 0x61
1782	#define PACKET3_SET_CONFIG_REG 0x68
1783	#define PACKET3_SET_CONFIG_REG_START 0x00008000
1784	#define PACKET3_SET_CONFIG_REG_END 0x0000b000
1785	#define PACKET3_SET_CONTEXT_REG 0x69
1786	#define PACKET3_SET_CONTEXT_REG_START 0x00028000
1787	#define PACKET3_SET_CONTEXT_REG_END 0x00029000
1788	#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1789	#define PACKET3_SET_RESOURCE_INDIRECT 0x74
1790	#define PACKET3_SET_SH_REG 0x76
1791	#define PACKET3_SET_SH_REG_START 0x0000b000
1792	#define PACKET3_SET_SH_REG_END 0x0000c000
1793	#define PACKET3_SET_SH_REG_OFFSET 0x77
1794	#define PACKET3_ME_WRITE 0x7A
1795	#define PACKET3_SCRATCH_RAM_WRITE 0x7D
1796	#define PACKET3_SCRATCH_RAM_READ 0x7E
1797	#define PACKET3_CE_WRITE 0x7F
1798	#define PACKET3_LOAD_CONST_RAM 0x80
1799	#define PACKET3_WRITE_CONST_RAM 0x81
1800	#define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
1801	#define PACKET3_DUMP_CONST_RAM 0x83
1802	#define PACKET3_INCREMENT_CE_COUNTER 0x84
1803	#define PACKET3_INCREMENT_DE_COUNTER 0x85
1804	#define PACKET3_WAIT_ON_CE_COUNTER 0x86
1805	#define PACKET3_WAIT_ON_DE_COUNTER 0x87
1806	#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
1807	#define PACKET3_SET_CE_DE_COUNTERS 0x89
1808	#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
1809	#define PACKET3_SWITCH_BUFFER 0x8B
1810
1811	/* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
1812	#define DMA0_REGISTER_OFFSET 0x0 /* not a register */
1813	#define DMA1_REGISTER_OFFSET 0x800 /* not a register */
1814
1815	#define DMA_RB_CNTL 0xd000
1816	# define DMA_RB_ENABLE (1 << 0)
1817	# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
1818	# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
1819	# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1820	# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
1821	# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
1822	#define DMA_RB_BASE 0xd004
1823	#define DMA_RB_RPTR 0xd008
1824	#define DMA_RB_WPTR 0xd00c
1825
1826	#define DMA_RB_RPTR_ADDR_HI 0xd01c
1827	#define DMA_RB_RPTR_ADDR_LO 0xd020
1828
1829	#define DMA_IB_CNTL 0xd024
1830	# define DMA_IB_ENABLE (1 << 0)
1831	# define DMA_IB_SWAP_ENABLE (1 << 4)
1832	#define DMA_IB_RPTR 0xd028
1833	#define DMA_CNTL 0xd02c
1834	# define TRAP_ENABLE (1 << 0)
1835	# define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1836	# define SEM_WAIT_INT_ENABLE (1 << 2)
1837	# define DATA_SWAP_ENABLE (1 << 3)
1838	# define FENCE_SWAP_ENABLE (1 << 4)
1839	# define CTXEMPTY_INT_ENABLE (1 << 28)
1840	#define DMA_STATUS_REG 0xd034
1841	# define DMA_IDLE (1 << 0)
1842	#define DMA_TILING_CONFIG 0xd0b8
1843
1844	#define DMA_POWER_CNTL 0xd0bc
1845	# define MEM_POWER_OVERRIDE (1 << 8)
1846	#define DMA_CLK_CTRL 0xd0c0
1847
1848	#define DMA_PG 0xd0d4
1849	# define PG_CNTL_ENABLE (1 << 0)
1850	#define DMA_PGFSM_CONFIG 0xd0d8
1851	#define DMA_PGFSM_WRITE 0xd0dc
1852
1853	#define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \
1854	(((b) & 0x1) << 26) | \
1855	(((t) & 0x1) << 23) | \
1856	(((s) & 0x1) << 22) | \
1857	(((n) & 0xFFFFF) << 0))
1858
1859	#define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \
1860	(((vmid) & 0xF) << 20) | \
1861	(((n) & 0xFFFFF) << 0))
1862
1863	#define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \
1864	(1 << 26) | \
1865	(1 << 21) | \
1866	(((n) & 0xFFFFF) << 0))
1867
1868	/* async DMA Packet types */
1869	#define DMA_PACKET_WRITE 0x2
1870	#define DMA_PACKET_COPY 0x3
1871	#define DMA_PACKET_INDIRECT_BUFFER 0x4
1872	#define DMA_PACKET_SEMAPHORE 0x5
1873	#define DMA_PACKET_FENCE 0x6
1874	#define DMA_PACKET_TRAP 0x7
1875	#define DMA_PACKET_SRBM_WRITE 0x9
1876	#define DMA_PACKET_CONSTANT_FILL 0xd
1877	#define DMA_PACKET_POLL_REG_MEM 0xe
1878	#define DMA_PACKET_NOP 0xf
1879
1880	#define VCE_STATUS 0x20004
1881	#define VCE_VCPU_CNTL 0x20014
1882	#define VCE_CLK_EN (1 << 0)
1883	#define VCE_VCPU_CACHE_OFFSET0 0x20024
1884	#define VCE_VCPU_CACHE_SIZE0 0x20028
1885	#define VCE_VCPU_CACHE_OFFSET1 0x2002c
1886	#define VCE_VCPU_CACHE_SIZE1 0x20030
1887	#define VCE_VCPU_CACHE_OFFSET2 0x20034
1888	#define VCE_VCPU_CACHE_SIZE2 0x20038
1889	#define VCE_VCPU_SCRATCH7 0x200dc
1890	#define VCE_SOFT_RESET 0x20120
1891	#define VCE_ECPU_SOFT_RESET (1 << 0)
1892	#define VCE_FME_SOFT_RESET (1 << 2)
1893	#define VCE_RB_BASE_LO2 0x2016c
1894	#define VCE_RB_BASE_HI2 0x20170
1895	#define VCE_RB_SIZE2 0x20174
1896	#define VCE_RB_RPTR2 0x20178
1897	#define VCE_RB_WPTR2 0x2017c
1898	#define VCE_RB_BASE_LO 0x20180
1899	#define VCE_RB_BASE_HI 0x20184
1900	#define VCE_RB_SIZE 0x20188
1901	#define VCE_RB_RPTR 0x2018c
1902	#define VCE_RB_WPTR 0x20190
1903	#define VCE_CLOCK_GATING_A 0x202f8
1904	# define CGC_DYN_CLOCK_MODE (1 << 16)
1905	#define VCE_CLOCK_GATING_B 0x202fc
1906	#define VCE_UENC_CLOCK_GATING 0x205bc
1907	#define VCE_UENC_REG_CLOCK_GATING 0x205c0
1908	#define VCE_FW_REG_STATUS 0x20e10
1909	# define VCE_FW_REG_STATUS_BUSY (1 << 0)
1910	# define VCE_FW_REG_STATUS_PASS (1 << 3)
1911	# define VCE_FW_REG_STATUS_DONE (1 << 11)
1912	#define VCE_LMI_FW_START_KEYSEL 0x20e18
1913	#define VCE_LMI_FW_PERIODIC_CTRL 0x20e20
1914	#define VCE_LMI_CTRL2 0x20e74
1915	#define VCE_LMI_CTRL 0x20e98
1916	#define VCE_LMI_VM_CTRL 0x20ea0
1917	#define VCE_LMI_SWAP_CNTL 0x20eb4
1918	#define VCE_LMI_SWAP_CNTL1 0x20eb8
1919	#define VCE_LMI_CACHE_CTRL 0x20ef4
1920
1921	#define VCE_CMD_NO_OP 0x00000000
1922	#define VCE_CMD_END 0x00000001
1923	#define VCE_CMD_IB 0x00000002
1924	#define VCE_CMD_FENCE 0x00000003
1925	#define VCE_CMD_TRAP 0x00000004
1926	#define VCE_CMD_IB_AUTO 0x00000005
1927	#define VCE_CMD_SEMAPHORE 0x00000006
1928
1929	/* discrete vce clocks */
1930	#define CG_VCEPLL_FUNC_CNTL 0xc0030600
1931	# define VCEPLL_RESET_MASK 0x00000001
1932	# define VCEPLL_SLEEP_MASK 0x00000002
1933	# define VCEPLL_BYPASS_EN_MASK 0x00000004
1934	# define VCEPLL_CTLREQ_MASK 0x00000008
1935	# define VCEPLL_VCO_MODE_MASK 0x00000600
1936	# define VCEPLL_REF_DIV_MASK 0x003F0000
1937	# define VCEPLL_CTLACK_MASK 0x40000000
1938	# define VCEPLL_CTLACK2_MASK 0x80000000
1939	#define CG_VCEPLL_FUNC_CNTL_2 0xc0030601
1940	# define VCEPLL_PDIV_A(x) ((x) << 0)
1941	# define VCEPLL_PDIV_A_MASK 0x0000007F
1942	# define VCEPLL_PDIV_B(x) ((x) << 8)
1943	# define VCEPLL_PDIV_B_MASK 0x00007F00
1944	# define EVCLK_SRC_SEL(x) ((x) << 20)
1945	# define EVCLK_SRC_SEL_MASK 0x01F00000
1946	# define ECCLK_SRC_SEL(x) ((x) << 25)
1947	# define ECCLK_SRC_SEL_MASK 0x3E000000
1948	#define CG_VCEPLL_FUNC_CNTL_3 0xc0030602
1949	# define VCEPLL_FB_DIV(x) ((x) << 0)
1950	# define VCEPLL_FB_DIV_MASK 0x01FFFFFF
1951	#define CG_VCEPLL_FUNC_CNTL_4 0xc0030603
1952	#define CG_VCEPLL_FUNC_CNTL_5 0xc0030604
1953	#define CG_VCEPLL_SPREAD_SPECTRUM 0xc0030606
1954	# define VCEPLL_SSEN_MASK 0x00000001
1955
1956	#endif
1957