1/*
2 * nct6775 - Driver for the hardware monitoring functionality of
3 * Nuvoton NCT677x Super-I/O chips
4 *
5 * Copyright (C) 2012 Guenter Roeck <linux@roeck-us.net>
6 *
7 * Derived from w83627ehf driver
8 * Copyright (C) 2005-2012 Jean Delvare <jdelvare@suse.de>
9 * Copyright (C) 2006 Yuan Mu (Winbond),
10 * Rudolf Marek <r.marek@assembler.cz>
11 * David Hubbard <david.c.hubbard@gmail.com>
12 * Daniel J Blueman <daniel.blueman@gmail.com>
13 * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
14 *
15 * Shamelessly ripped from the w83627hf driver
16 * Copyright (C) 2003 Mark Studebaker
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31 *
32 *
33 * Supports the following chips:
34 *
35 * Chip #vin #fan #pwm #temp chip IDs man ID
36 * nct6106d 9 3 3 6+3 0xc450 0xc1 0x5ca3
37 * nct6775f 9 4 3 6+3 0xb470 0xc1 0x5ca3
38 * nct6776f 9 5 3 6+3 0xc330 0xc1 0x5ca3
39 * nct6779d 15 5 5 2+6 0xc560 0xc1 0x5ca3
40 * nct6791d 15 6 6 2+6 0xc800 0xc1 0x5ca3
41 * nct6792d 15 6 6 2+6 0xc910 0xc1 0x5ca3
42 * nct6793d 15 6 6 2+6 0xd120 0xc1 0x5ca3
43 * nct6795d 14 6 6 2+6 0xd350 0xc1 0x5ca3
44 * nct6796d 14 7 7 2+6 0xd420 0xc1 0x5ca3
45 * nct6797d 14 7 7 2+6 0xd450 0xc1 0x5ca3
46 * (0xd451)
47 * nct6798d 14 7 7 2+6 0xd428 0xc1 0x5ca3
48 * (0xd429)
49 *
50 * #temp lists the number of monitored temperature sources (first value) plus
51 * the number of directly connectable temperature sensors (second value).
52 */
53
54#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
55
56#include <linux/module.h>
57#include <linux/init.h>
58#include <linux/slab.h>
59#include <linux/jiffies.h>
60#include <linux/platform_device.h>
61#include <linux/hwmon.h>
62#include <linux/hwmon-sysfs.h>
63#include <linux/hwmon-vid.h>
64#include <linux/err.h>
65#include <linux/mutex.h>
66#include <linux/acpi.h>
67#include <linux/bitops.h>
68#include <linux/dmi.h>
69#include <linux/io.h>
70#include <linux/nospec.h>
71#include "lm75.h"
72
73#define USE_ALTERNATE
74
75enum kinds { nct6106, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793,
76 nct6795, nct6796, nct6797, nct6798 };
77
78/* used to set data->name = nct6775_device_names[data->sio_kind] */
79static const char * const nct6775_device_names[] = {
80 "nct6106",
81 "nct6775",
82 "nct6776",
83 "nct6779",
84 "nct6791",
85 "nct6792",
86 "nct6793",
87 "nct6795",
88 "nct6796",
89 "nct6797",
90 "nct6798",
91};
92
93static const char * const nct6775_sio_names[] __initconst = {
94 "NCT6106D",
95 "NCT6775F",
96 "NCT6776D/F",
97 "NCT6779D",
98 "NCT6791D",
99 "NCT6792D",
100 "NCT6793D",
101 "NCT6795D",
102 "NCT6796D",
103 "NCT6797D",
104 "NCT6798D",
105};
106
107static unsigned short force_id;
108module_param(force_id, ushort, 0);
109MODULE_PARM_DESC(force_id, "Override the detected device ID");
110
111static unsigned short fan_debounce;
112module_param(fan_debounce, ushort, 0);
113MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
114
115#define DRVNAME "nct6775"
116
117/*
118 * Super-I/O constants and functions
119 */
120
121#define NCT6775_LD_ACPI 0x0a
122#define NCT6775_LD_HWM 0x0b
123#define NCT6775_LD_VID 0x0d
124#define NCT6775_LD_12 0x12
125
126#define SIO_REG_LDSEL 0x07 /* Logical device select */
127#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
128#define SIO_REG_ENABLE 0x30 /* Logical device enable */
129#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
130
131#define SIO_NCT6106_ID 0xc450
132#define SIO_NCT6775_ID 0xb470
133#define SIO_NCT6776_ID 0xc330
134#define SIO_NCT6779_ID 0xc560
135#define SIO_NCT6791_ID 0xc800
136#define SIO_NCT6792_ID 0xc910
137#define SIO_NCT6793_ID 0xd120
138#define SIO_NCT6795_ID 0xd350
139#define SIO_NCT6796_ID 0xd420
140#define SIO_NCT6797_ID 0xd450
141#define SIO_NCT6798_ID 0xd428
142#define SIO_ID_MASK 0xFFF8
143
144enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 };
145
146static inline void
147superio_outb(int ioreg, int reg, int val)
148{
149 outb(reg, ioreg);
150 outb(val, ioreg + 1);
151}
152
153static inline int
154superio_inb(int ioreg, int reg)
155{
156 outb(reg, ioreg);
157 return inb(ioreg + 1);
158}
159
160static inline void
161superio_select(int ioreg, int ld)
162{
163 outb(SIO_REG_LDSEL, ioreg);
164 outb(ld, ioreg + 1);
165}
166
167static inline int
168superio_enter(int ioreg)
169{
170 /*
171 * Try to reserve <ioreg> and <ioreg + 1> for exclusive access.
172 */
173 if (!request_muxed_region(ioreg, 2, DRVNAME))
174 return -EBUSY;
175
176 outb(0x87, ioreg);
177 outb(0x87, ioreg);
178
179 return 0;
180}
181
182static inline void
183superio_exit(int ioreg)
184{
185 outb(0xaa, ioreg);
186 outb(0x02, ioreg);
187 outb(0x02, ioreg + 1);
188 release_region(ioreg, 2);
189}
190
191/*
192 * ISA constants
193 */
194
195#define IOREGION_ALIGNMENT (~7)
196#define IOREGION_OFFSET 5
197#define IOREGION_LENGTH 2
198#define ADDR_REG_OFFSET 0
199#define DATA_REG_OFFSET 1
200
201#define NCT6775_REG_BANK 0x4E
202#define NCT6775_REG_CONFIG 0x40
203
204/*
205 * Not currently used:
206 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
207 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
208 * REG_MAN_ID is at port 0x4f
209 * REG_CHIP_ID is at port 0x58
210 */
211
212#define NUM_TEMP 10 /* Max number of temp attribute sets w/ limits*/
213#define NUM_TEMP_FIXED 6 /* Max number of fixed temp attribute sets */
214
215#define NUM_REG_ALARM 7 /* Max number of alarm registers */
216#define NUM_REG_BEEP 5 /* Max number of beep registers */
217
218#define NUM_FAN 7
219
220/* Common and NCT6775 specific data */
221
222/* Voltage min/max registers for nr=7..14 are in bank 5 */
223
224static const u16 NCT6775_REG_IN_MAX[] = {
225 0x2b, 0x2d, 0x2f, 0x31, 0x33, 0x35, 0x37, 0x554, 0x556, 0x558, 0x55a,
226 0x55c, 0x55e, 0x560, 0x562 };
227static const u16 NCT6775_REG_IN_MIN[] = {
228 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x555, 0x557, 0x559, 0x55b,
229 0x55d, 0x55f, 0x561, 0x563 };
230static const u16 NCT6775_REG_IN[] = {
231 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x550, 0x551, 0x552
232};
233
234#define NCT6775_REG_VBAT 0x5D
235#define NCT6775_REG_DIODE 0x5E
236#define NCT6775_DIODE_MASK 0x02
237
238#define NCT6775_REG_FANDIV1 0x506
239#define NCT6775_REG_FANDIV2 0x507
240
241#define NCT6775_REG_CR_FAN_DEBOUNCE 0xf0
242
243static const u16 NCT6775_REG_ALARM[NUM_REG_ALARM] = { 0x459, 0x45A, 0x45B };
244
245/* 0..15 voltages, 16..23 fans, 24..29 temperatures, 30..31 intrusion */
246
247static const s8 NCT6775_ALARM_BITS[] = {
248 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
249 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
250 -1, /* unused */
251 6, 7, 11, -1, -1, /* fan1..fan5 */
252 -1, -1, -1, /* unused */
253 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
254 12, -1 }; /* intrusion0, intrusion1 */
255
256#define FAN_ALARM_BASE 16
257#define TEMP_ALARM_BASE 24
258#define INTRUSION_ALARM_BASE 30
259
260static const u16 NCT6775_REG_BEEP[NUM_REG_BEEP] = { 0x56, 0x57, 0x453, 0x4e };
261
262/*
263 * 0..14 voltages, 15 global beep enable, 16..23 fans, 24..29 temperatures,
264 * 30..31 intrusion
265 */
266static const s8 NCT6775_BEEP_BITS[] = {
267 0, 1, 2, 3, 8, 9, 10, 16, /* in0.. in7 */
268 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
269 21, /* global beep enable */
270 6, 7, 11, 28, -1, /* fan1..fan5 */
271 -1, -1, -1, /* unused */
272 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
273 12, -1 }; /* intrusion0, intrusion1 */
274
275#define BEEP_ENABLE_BASE 15
276
277static const u8 NCT6775_REG_CR_CASEOPEN_CLR[] = { 0xe6, 0xee };
278static const u8 NCT6775_CR_CASEOPEN_CLR_MASK[] = { 0x20, 0x01 };
279
280/* DC or PWM output fan configuration */
281static const u8 NCT6775_REG_PWM_MODE[] = { 0x04, 0x04, 0x12 };
282static const u8 NCT6775_PWM_MODE_MASK[] = { 0x01, 0x02, 0x01 };
283
284/* Advanced Fan control, some values are common for all fans */
285
286static const u16 NCT6775_REG_TARGET[] = {
287 0x101, 0x201, 0x301, 0x801, 0x901, 0xa01, 0xb01 };
288static const u16 NCT6775_REG_FAN_MODE[] = {
289 0x102, 0x202, 0x302, 0x802, 0x902, 0xa02, 0xb02 };
290static const u16 NCT6775_REG_FAN_STEP_DOWN_TIME[] = {
291 0x103, 0x203, 0x303, 0x803, 0x903, 0xa03, 0xb03 };
292static const u16 NCT6775_REG_FAN_STEP_UP_TIME[] = {
293 0x104, 0x204, 0x304, 0x804, 0x904, 0xa04, 0xb04 };
294static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = {
295 0x105, 0x205, 0x305, 0x805, 0x905, 0xa05, 0xb05 };
296static const u16 NCT6775_REG_FAN_START_OUTPUT[] = {
297 0x106, 0x206, 0x306, 0x806, 0x906, 0xa06, 0xb06 };
298static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
299static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
300
301static const u16 NCT6775_REG_FAN_STOP_TIME[] = {
302 0x107, 0x207, 0x307, 0x807, 0x907, 0xa07, 0xb07 };
303static const u16 NCT6775_REG_PWM[] = {
304 0x109, 0x209, 0x309, 0x809, 0x909, 0xa09, 0xb09 };
305static const u16 NCT6775_REG_PWM_READ[] = {
306 0x01, 0x03, 0x11, 0x13, 0x15, 0xa09, 0xb09 };
307
308static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
309static const u16 NCT6775_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d };
310static const u16 NCT6775_REG_FAN_PULSES[NUM_FAN] = {
311 0x641, 0x642, 0x643, 0x644 };
312static const u16 NCT6775_FAN_PULSE_SHIFT[NUM_FAN] = { };
313
314static const u16 NCT6775_REG_TEMP[] = {
315 0x27, 0x150, 0x250, 0x62b, 0x62c, 0x62d };
316
317static const u16 NCT6775_REG_TEMP_MON[] = { 0x73, 0x75, 0x77 };
318
319static const u16 NCT6775_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
320 0, 0x152, 0x252, 0x628, 0x629, 0x62A };
321static const u16 NCT6775_REG_TEMP_HYST[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
322 0x3a, 0x153, 0x253, 0x673, 0x678, 0x67D };
323static const u16 NCT6775_REG_TEMP_OVER[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
324 0x39, 0x155, 0x255, 0x672, 0x677, 0x67C };
325
326static const u16 NCT6775_REG_TEMP_SOURCE[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
327 0x621, 0x622, 0x623, 0x624, 0x625, 0x626 };
328
329static const u16 NCT6775_REG_TEMP_SEL[] = {
330 0x100, 0x200, 0x300, 0x800, 0x900, 0xa00, 0xb00 };
331
332static const u16 NCT6775_REG_WEIGHT_TEMP_SEL[] = {
333 0x139, 0x239, 0x339, 0x839, 0x939, 0xa39 };
334static const u16 NCT6775_REG_WEIGHT_TEMP_STEP[] = {
335 0x13a, 0x23a, 0x33a, 0x83a, 0x93a, 0xa3a };
336static const u16 NCT6775_REG_WEIGHT_TEMP_STEP_TOL[] = {
337 0x13b, 0x23b, 0x33b, 0x83b, 0x93b, 0xa3b };
338static const u16 NCT6775_REG_WEIGHT_DUTY_STEP[] = {
339 0x13c, 0x23c, 0x33c, 0x83c, 0x93c, 0xa3c };
340static const u16 NCT6775_REG_WEIGHT_TEMP_BASE[] = {
341 0x13d, 0x23d, 0x33d, 0x83d, 0x93d, 0xa3d };
342
343static const u16 NCT6775_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
344
345static const u16 NCT6775_REG_AUTO_TEMP[] = {
346 0x121, 0x221, 0x321, 0x821, 0x921, 0xa21, 0xb21 };
347static const u16 NCT6775_REG_AUTO_PWM[] = {
348 0x127, 0x227, 0x327, 0x827, 0x927, 0xa27, 0xb27 };
349
350#define NCT6775_AUTO_TEMP(data, nr, p) ((data)->REG_AUTO_TEMP[nr] + (p))
351#define NCT6775_AUTO_PWM(data, nr, p) ((data)->REG_AUTO_PWM[nr] + (p))
352
353static const u16 NCT6775_REG_CRITICAL_ENAB[] = { 0x134, 0x234, 0x334 };
354
355static const u16 NCT6775_REG_CRITICAL_TEMP[] = {
356 0x135, 0x235, 0x335, 0x835, 0x935, 0xa35, 0xb35 };
357static const u16 NCT6775_REG_CRITICAL_TEMP_TOLERANCE[] = {
358 0x138, 0x238, 0x338, 0x838, 0x938, 0xa38, 0xb38 };
359
360static const char *const nct6775_temp_label[] = {
361 "",
362 "SYSTIN",
363 "CPUTIN",
364 "AUXTIN",
365 "AMD SB-TSI",
366 "PECI Agent 0",
367 "PECI Agent 1",
368 "PECI Agent 2",
369 "PECI Agent 3",
370 "PECI Agent 4",
371 "PECI Agent 5",
372 "PECI Agent 6",
373 "PECI Agent 7",
374 "PCH_CHIP_CPU_MAX_TEMP",
375 "PCH_CHIP_TEMP",
376 "PCH_CPU_TEMP",
377 "PCH_MCH_TEMP",
378 "PCH_DIM0_TEMP",
379 "PCH_DIM1_TEMP",
380 "PCH_DIM2_TEMP",
381 "PCH_DIM3_TEMP"
382};
383
384#define NCT6775_TEMP_MASK 0x001ffffe
385#define NCT6775_VIRT_TEMP_MASK 0x00000000
386
387static const u16 NCT6775_REG_TEMP_ALTERNATE[32] = {
388 [13] = 0x661,
389 [14] = 0x662,
390 [15] = 0x664,
391};
392
393static const u16 NCT6775_REG_TEMP_CRIT[32] = {
394 [4] = 0xa00,
395 [5] = 0xa01,
396 [6] = 0xa02,
397 [7] = 0xa03,
398 [8] = 0xa04,
399 [9] = 0xa05,
400 [10] = 0xa06,
401 [11] = 0xa07
402};
403
404/* NCT6776 specific data */
405
406/* STEP_UP_TIME and STEP_DOWN_TIME regs are swapped for all chips but NCT6775 */
407#define NCT6776_REG_FAN_STEP_UP_TIME NCT6775_REG_FAN_STEP_DOWN_TIME
408#define NCT6776_REG_FAN_STEP_DOWN_TIME NCT6775_REG_FAN_STEP_UP_TIME
409
410static const s8 NCT6776_ALARM_BITS[] = {
411 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
412 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
413 -1, /* unused */
414 6, 7, 11, 10, 23, /* fan1..fan5 */
415 -1, -1, -1, /* unused */
416 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
417 12, 9 }; /* intrusion0, intrusion1 */
418
419static const u16 NCT6776_REG_BEEP[NUM_REG_BEEP] = { 0xb2, 0xb3, 0xb4, 0xb5 };
420
421static const s8 NCT6776_BEEP_BITS[] = {
422 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
423 8, -1, -1, -1, -1, -1, -1, /* in8..in14 */
424 24, /* global beep enable */
425 25, 26, 27, 28, 29, /* fan1..fan5 */
426 -1, -1, -1, /* unused */
427 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
428 30, 31 }; /* intrusion0, intrusion1 */
429
430static const u16 NCT6776_REG_TOLERANCE_H[] = {
431 0x10c, 0x20c, 0x30c, 0x80c, 0x90c, 0xa0c, 0xb0c };
432
433static const u8 NCT6776_REG_PWM_MODE[] = { 0x04, 0, 0, 0, 0, 0 };
434static const u8 NCT6776_PWM_MODE_MASK[] = { 0x01, 0, 0, 0, 0, 0 };
435
436static const u16 NCT6776_REG_FAN_MIN[] = {
437 0x63a, 0x63c, 0x63e, 0x640, 0x642, 0x64a, 0x64c };
438static const u16 NCT6776_REG_FAN_PULSES[NUM_FAN] = {
439 0x644, 0x645, 0x646, 0x647, 0x648, 0x649 };
440
441static const u16 NCT6776_REG_WEIGHT_DUTY_BASE[] = {
442 0x13e, 0x23e, 0x33e, 0x83e, 0x93e, 0xa3e };
443
444static const u16 NCT6776_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
445 0x18, 0x152, 0x252, 0x628, 0x629, 0x62A };
446
447static const char *const nct6776_temp_label[] = {
448 "",
449 "SYSTIN",
450 "CPUTIN",
451 "AUXTIN",
452 "SMBUSMASTER 0",
453 "SMBUSMASTER 1",
454 "SMBUSMASTER 2",
455 "SMBUSMASTER 3",
456 "SMBUSMASTER 4",
457 "SMBUSMASTER 5",
458 "SMBUSMASTER 6",
459 "SMBUSMASTER 7",
460 "PECI Agent 0",
461 "PECI Agent 1",
462 "PCH_CHIP_CPU_MAX_TEMP",
463 "PCH_CHIP_TEMP",
464 "PCH_CPU_TEMP",
465 "PCH_MCH_TEMP",
466 "PCH_DIM0_TEMP",
467 "PCH_DIM1_TEMP",
468 "PCH_DIM2_TEMP",
469 "PCH_DIM3_TEMP",
470 "BYTE_TEMP"
471};
472
473#define NCT6776_TEMP_MASK 0x007ffffe
474#define NCT6776_VIRT_TEMP_MASK 0x00000000
475
476static const u16 NCT6776_REG_TEMP_ALTERNATE[32] = {
477 [14] = 0x401,
478 [15] = 0x402,
479 [16] = 0x404,
480};
481
482static const u16 NCT6776_REG_TEMP_CRIT[32] = {
483 [11] = 0x709,
484 [12] = 0x70a,
485};
486
487/* NCT6779 specific data */
488
489static const u16 NCT6779_REG_IN[] = {
490 0x480, 0x481, 0x482, 0x483, 0x484, 0x485, 0x486, 0x487,
491 0x488, 0x489, 0x48a, 0x48b, 0x48c, 0x48d, 0x48e };
492
493static const u16 NCT6779_REG_ALARM[NUM_REG_ALARM] = {
494 0x459, 0x45A, 0x45B, 0x568 };
495
496static const s8 NCT6779_ALARM_BITS[] = {
497 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
498 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
499 -1, /* unused */
500 6, 7, 11, 10, 23, /* fan1..fan5 */
501 -1, -1, -1, /* unused */
502 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
503 12, 9 }; /* intrusion0, intrusion1 */
504
505static const s8 NCT6779_BEEP_BITS[] = {
506 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
507 8, 9, 10, 11, 12, 13, 14, /* in8..in14 */
508 24, /* global beep enable */
509 25, 26, 27, 28, 29, /* fan1..fan5 */
510 -1, -1, -1, /* unused */
511 16, 17, -1, -1, -1, -1, /* temp1..temp6 */
512 30, 31 }; /* intrusion0, intrusion1 */
513
514static const u16 NCT6779_REG_FAN[] = {
515 0x4c0, 0x4c2, 0x4c4, 0x4c6, 0x4c8, 0x4ca, 0x4ce };
516static const u16 NCT6779_REG_FAN_PULSES[NUM_FAN] = {
517 0x644, 0x645, 0x646, 0x647, 0x648, 0x649, 0x64f };
518
519static const u16 NCT6779_REG_CRITICAL_PWM_ENABLE[] = {
520 0x136, 0x236, 0x336, 0x836, 0x936, 0xa36, 0xb36 };
521#define NCT6779_CRITICAL_PWM_ENABLE_MASK 0x01
522static const u16 NCT6779_REG_CRITICAL_PWM[] = {
523 0x137, 0x237, 0x337, 0x837, 0x937, 0xa37, 0xb37 };
524
525static const u16 NCT6779_REG_TEMP[] = { 0x27, 0x150 };
526static const u16 NCT6779_REG_TEMP_MON[] = { 0x73, 0x75, 0x77, 0x79, 0x7b };
527static const u16 NCT6779_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
528 0x18, 0x152 };
529static const u16 NCT6779_REG_TEMP_HYST[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
530 0x3a, 0x153 };
531static const u16 NCT6779_REG_TEMP_OVER[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
532 0x39, 0x155 };
533
534static const u16 NCT6779_REG_TEMP_OFFSET[] = {
535 0x454, 0x455, 0x456, 0x44a, 0x44b, 0x44c };
536
537static const char *const nct6779_temp_label[] = {
538 "",
539 "SYSTIN",
540 "CPUTIN",
541 "AUXTIN0",
542 "AUXTIN1",
543 "AUXTIN2",
544 "AUXTIN3",
545 "",
546 "SMBUSMASTER 0",
547 "SMBUSMASTER 1",
548 "SMBUSMASTER 2",
549 "SMBUSMASTER 3",
550 "SMBUSMASTER 4",
551 "SMBUSMASTER 5",
552 "SMBUSMASTER 6",
553 "SMBUSMASTER 7",
554 "PECI Agent 0",
555 "PECI Agent 1",
556 "PCH_CHIP_CPU_MAX_TEMP",
557 "PCH_CHIP_TEMP",
558 "PCH_CPU_TEMP",
559 "PCH_MCH_TEMP",
560 "PCH_DIM0_TEMP",
561 "PCH_DIM1_TEMP",
562 "PCH_DIM2_TEMP",
563 "PCH_DIM3_TEMP",
564 "BYTE_TEMP",
565 "",
566 "",
567 "",
568 "",
569 "Virtual_TEMP"
570};
571
572#define NCT6779_TEMP_MASK 0x07ffff7e
573#define NCT6779_VIRT_TEMP_MASK 0x00000000
574#define NCT6791_TEMP_MASK 0x87ffff7e
575#define NCT6791_VIRT_TEMP_MASK 0x80000000
576
577static const u16 NCT6779_REG_TEMP_ALTERNATE[32]
578 = { 0x490, 0x491, 0x492, 0x493, 0x494, 0x495, 0, 0,
579 0, 0, 0, 0, 0, 0, 0, 0,
580 0, 0x400, 0x401, 0x402, 0x404, 0x405, 0x406, 0x407,
581 0x408, 0 };
582
583static const u16 NCT6779_REG_TEMP_CRIT[32] = {
584 [15] = 0x709,
585 [16] = 0x70a,
586};
587
588/* NCT6791 specific data */
589
590#define NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE 0x28
591
592static const u16 NCT6791_REG_WEIGHT_TEMP_SEL[NUM_FAN] = { 0, 0x239 };
593static const u16 NCT6791_REG_WEIGHT_TEMP_STEP[NUM_FAN] = { 0, 0x23a };
594static const u16 NCT6791_REG_WEIGHT_TEMP_STEP_TOL[NUM_FAN] = { 0, 0x23b };
595static const u16 NCT6791_REG_WEIGHT_DUTY_STEP[NUM_FAN] = { 0, 0x23c };
596static const u16 NCT6791_REG_WEIGHT_TEMP_BASE[NUM_FAN] = { 0, 0x23d };
597static const u16 NCT6791_REG_WEIGHT_DUTY_BASE[NUM_FAN] = { 0, 0x23e };
598
599static const u16 NCT6791_REG_ALARM[NUM_REG_ALARM] = {
600 0x459, 0x45A, 0x45B, 0x568, 0x45D };
601
602static const s8 NCT6791_ALARM_BITS[] = {
603 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
604 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
605 -1, /* unused */
606 6, 7, 11, 10, 23, 33, /* fan1..fan6 */
607 -1, -1, /* unused */
608 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
609 12, 9 }; /* intrusion0, intrusion1 */
610
611/* NCT6792/NCT6793 specific data */
612
613static const u16 NCT6792_REG_TEMP_MON[] = {
614 0x73, 0x75, 0x77, 0x79, 0x7b, 0x7d };
615static const u16 NCT6792_REG_BEEP[NUM_REG_BEEP] = {
616 0xb2, 0xb3, 0xb4, 0xb5, 0xbf };
617
618static const char *const nct6792_temp_label[] = {
619 "",
620 "SYSTIN",
621 "CPUTIN",
622 "AUXTIN0",
623 "AUXTIN1",
624 "AUXTIN2",
625 "AUXTIN3",
626 "",
627 "SMBUSMASTER 0",
628 "SMBUSMASTER 1",
629 "SMBUSMASTER 2",
630 "SMBUSMASTER 3",
631 "SMBUSMASTER 4",
632 "SMBUSMASTER 5",
633 "SMBUSMASTER 6",
634 "SMBUSMASTER 7",
635 "PECI Agent 0",
636 "PECI Agent 1",
637 "PCH_CHIP_CPU_MAX_TEMP",
638 "PCH_CHIP_TEMP",
639 "PCH_CPU_TEMP",
640 "PCH_MCH_TEMP",
641 "PCH_DIM0_TEMP",
642 "PCH_DIM1_TEMP",
643 "PCH_DIM2_TEMP",
644 "PCH_DIM3_TEMP",
645 "BYTE_TEMP",
646 "PECI Agent 0 Calibration",
647 "PECI Agent 1 Calibration",
648 "",
649 "",
650 "Virtual_TEMP"
651};
652
653#define NCT6792_TEMP_MASK 0x9fffff7e
654#define NCT6792_VIRT_TEMP_MASK 0x80000000
655
656static const char *const nct6793_temp_label[] = {
657 "",
658 "SYSTIN",
659 "CPUTIN",
660 "AUXTIN0",
661 "AUXTIN1",
662 "AUXTIN2",
663 "AUXTIN3",
664 "",
665 "SMBUSMASTER 0",
666 "SMBUSMASTER 1",
667 "",
668 "",
669 "",
670 "",
671 "",
672 "",
673 "PECI Agent 0",
674 "PECI Agent 1",
675 "PCH_CHIP_CPU_MAX_TEMP",
676 "PCH_CHIP_TEMP",
677 "PCH_CPU_TEMP",
678 "PCH_MCH_TEMP",
679 "Agent0 Dimm0 ",
680 "Agent0 Dimm1",
681 "Agent1 Dimm0",
682 "Agent1 Dimm1",
683 "BYTE_TEMP0",
684 "BYTE_TEMP1",
685 "PECI Agent 0 Calibration",
686 "PECI Agent 1 Calibration",
687 "",
688 "Virtual_TEMP"
689};
690
691#define NCT6793_TEMP_MASK 0xbfff037e
692#define NCT6793_VIRT_TEMP_MASK 0x80000000
693
694static const char *const nct6795_temp_label[] = {
695 "",
696 "SYSTIN",
697 "CPUTIN",
698 "AUXTIN0",
699 "AUXTIN1",
700 "AUXTIN2",
701 "AUXTIN3",
702 "",
703 "SMBUSMASTER 0",
704 "SMBUSMASTER 1",
705 "SMBUSMASTER 2",
706 "SMBUSMASTER 3",
707 "SMBUSMASTER 4",
708 "SMBUSMASTER 5",
709 "SMBUSMASTER 6",
710 "SMBUSMASTER 7",
711 "PECI Agent 0",
712 "PECI Agent 1",
713 "PCH_CHIP_CPU_MAX_TEMP",
714 "PCH_CHIP_TEMP",
715 "PCH_CPU_TEMP",
716 "PCH_MCH_TEMP",
717 "Agent0 Dimm0",
718 "Agent0 Dimm1",
719 "Agent1 Dimm0",
720 "Agent1 Dimm1",
721 "BYTE_TEMP0",
722 "BYTE_TEMP1",
723 "PECI Agent 0 Calibration",
724 "PECI Agent 1 Calibration",
725 "",
726 "Virtual_TEMP"
727};
728
729#define NCT6795_TEMP_MASK 0xbfffff7e
730#define NCT6795_VIRT_TEMP_MASK 0x80000000
731
732static const char *const nct6796_temp_label[] = {
733 "",
734 "SYSTIN",
735 "CPUTIN",
736 "AUXTIN0",
737 "AUXTIN1",
738 "AUXTIN2",
739 "AUXTIN3",
740 "AUXTIN4",
741 "SMBUSMASTER 0",
742 "SMBUSMASTER 1",
743 "Virtual_TEMP",
744 "Virtual_TEMP",
745 "",
746 "",
747 "",
748 "",
749 "PECI Agent 0",
750 "PECI Agent 1",
751 "PCH_CHIP_CPU_MAX_TEMP",
752 "PCH_CHIP_TEMP",
753 "PCH_CPU_TEMP",
754 "PCH_MCH_TEMP",
755 "Agent0 Dimm0",
756 "Agent0 Dimm1",
757 "Agent1 Dimm0",
758 "Agent1 Dimm1",
759 "BYTE_TEMP0",
760 "BYTE_TEMP1",
761 "PECI Agent 0 Calibration",
762 "PECI Agent 1 Calibration",
763 "",
764 "Virtual_TEMP"
765};
766
767#define NCT6796_TEMP_MASK 0xbfff0ffe
768#define NCT6796_VIRT_TEMP_MASK 0x80000c00
769
770static const char *const nct6798_temp_label[] = {
771 "",
772 "SYSTIN",
773 "CPUTIN",
774 "AUXTIN0",
775 "AUXTIN1",
776 "AUXTIN2",
777 "AUXTIN3",
778 "AUXTIN4",
779 "SMBUSMASTER 0",
780 "SMBUSMASTER 1",
781 "Virtual_TEMP",
782 "Virtual_TEMP",
783 "",
784 "",
785 "",
786 "",
787 "PECI Agent 0",
788 "PECI Agent 1",
789 "PCH_CHIP_CPU_MAX_TEMP",
790 "PCH_CHIP_TEMP",
791 "PCH_CPU_TEMP",
792 "PCH_MCH_TEMP",
793 "Agent0 Dimm0",
794 "Agent0 Dimm1",
795 "Agent1 Dimm0",
796 "Agent1 Dimm1",
797 "BYTE_TEMP0",
798 "BYTE_TEMP1",
799 "",
800 "",
801 "",
802 "Virtual_TEMP"
803};
804
805#define NCT6798_TEMP_MASK 0x8fff0ffe
806#define NCT6798_VIRT_TEMP_MASK 0x80000c00
807
808/* NCT6102D/NCT6106D specific data */
809
810#define NCT6106_REG_VBAT 0x318
811#define NCT6106_REG_DIODE 0x319
812#define NCT6106_DIODE_MASK 0x01
813
814static const u16 NCT6106_REG_IN_MAX[] = {
815 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9e, 0xa0, 0xa2 };
816static const u16 NCT6106_REG_IN_MIN[] = {
817 0x91, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9f, 0xa1, 0xa3 };
818static const u16 NCT6106_REG_IN[] = {
819 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x07, 0x08, 0x09 };
820
821static const u16 NCT6106_REG_TEMP[] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15 };
822static const u16 NCT6106_REG_TEMP_MON[] = { 0x18, 0x19, 0x1a };
823static const u16 NCT6106_REG_TEMP_HYST[] = {
824 0xc3, 0xc7, 0xcb, 0xcf, 0xd3, 0xd7 };
825static const u16 NCT6106_REG_TEMP_OVER[] = {
826 0xc2, 0xc6, 0xca, 0xce, 0xd2, 0xd6 };
827static const u16 NCT6106_REG_TEMP_CRIT_L[] = {
828 0xc0, 0xc4, 0xc8, 0xcc, 0xd0, 0xd4 };
829static const u16 NCT6106_REG_TEMP_CRIT_H[] = {
830 0xc1, 0xc5, 0xc9, 0xcf, 0xd1, 0xd5 };
831static const u16 NCT6106_REG_TEMP_OFFSET[] = { 0x311, 0x312, 0x313 };
832static const u16 NCT6106_REG_TEMP_CONFIG[] = {
833 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc };
834
835static const u16 NCT6106_REG_FAN[] = { 0x20, 0x22, 0x24 };
836static const u16 NCT6106_REG_FAN_MIN[] = { 0xe0, 0xe2, 0xe4 };
837static const u16 NCT6106_REG_FAN_PULSES[] = { 0xf6, 0xf6, 0xf6 };
838static const u16 NCT6106_FAN_PULSE_SHIFT[] = { 0, 2, 4 };
839
840static const u8 NCT6106_REG_PWM_MODE[] = { 0xf3, 0xf3, 0xf3 };
841static const u8 NCT6106_PWM_MODE_MASK[] = { 0x01, 0x02, 0x04 };
842static const u16 NCT6106_REG_PWM[] = { 0x119, 0x129, 0x139 };
843static const u16 NCT6106_REG_PWM_READ[] = { 0x4a, 0x4b, 0x4c };
844static const u16 NCT6106_REG_FAN_MODE[] = { 0x113, 0x123, 0x133 };
845static const u16 NCT6106_REG_TEMP_SEL[] = { 0x110, 0x120, 0x130 };
846static const u16 NCT6106_REG_TEMP_SOURCE[] = {
847 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5 };
848
849static const u16 NCT6106_REG_CRITICAL_TEMP[] = { 0x11a, 0x12a, 0x13a };
850static const u16 NCT6106_REG_CRITICAL_TEMP_TOLERANCE[] = {
851 0x11b, 0x12b, 0x13b };
852
853static const u16 NCT6106_REG_CRITICAL_PWM_ENABLE[] = { 0x11c, 0x12c, 0x13c };
854#define NCT6106_CRITICAL_PWM_ENABLE_MASK 0x10
855static const u16 NCT6106_REG_CRITICAL_PWM[] = { 0x11d, 0x12d, 0x13d };
856
857static const u16 NCT6106_REG_FAN_STEP_UP_TIME[] = { 0x114, 0x124, 0x134 };
858static const u16 NCT6106_REG_FAN_STEP_DOWN_TIME[] = { 0x115, 0x125, 0x135 };
859static const u16 NCT6106_REG_FAN_STOP_OUTPUT[] = { 0x116, 0x126, 0x136 };
860static const u16 NCT6106_REG_FAN_START_OUTPUT[] = { 0x117, 0x127, 0x137 };
861static const u16 NCT6106_REG_FAN_STOP_TIME[] = { 0x118, 0x128, 0x138 };
862static const u16 NCT6106_REG_TOLERANCE_H[] = { 0x112, 0x122, 0x132 };
863
864static const u16 NCT6106_REG_TARGET[] = { 0x111, 0x121, 0x131 };
865
866static const u16 NCT6106_REG_WEIGHT_TEMP_SEL[] = { 0x168, 0x178, 0x188 };
867static const u16 NCT6106_REG_WEIGHT_TEMP_STEP[] = { 0x169, 0x179, 0x189 };
868static const u16 NCT6106_REG_WEIGHT_TEMP_STEP_TOL[] = { 0x16a, 0x17a, 0x18a };
869static const u16 NCT6106_REG_WEIGHT_DUTY_STEP[] = { 0x16b, 0x17b, 0x17c };
870static const u16 NCT6106_REG_WEIGHT_TEMP_BASE[] = { 0x16c, 0x17c, 0x18c };
871static const u16 NCT6106_REG_WEIGHT_DUTY_BASE[] = { 0x16d, 0x17d, 0x18d };
872
873static const u16 NCT6106_REG_AUTO_TEMP[] = { 0x160, 0x170, 0x180 };
874static const u16 NCT6106_REG_AUTO_PWM[] = { 0x164, 0x174, 0x184 };
875
876static const u16 NCT6106_REG_ALARM[NUM_REG_ALARM] = {
877 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d };
878
879static const s8 NCT6106_ALARM_BITS[] = {
880 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
881 9, -1, -1, -1, -1, -1, -1, /* in8..in14 */
882 -1, /* unused */
883 32, 33, 34, -1, -1, /* fan1..fan5 */
884 -1, -1, -1, /* unused */
885 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
886 48, -1 /* intrusion0, intrusion1 */
887};
888
889static const u16 NCT6106_REG_BEEP[NUM_REG_BEEP] = {
890 0x3c0, 0x3c1, 0x3c2, 0x3c3, 0x3c4 };
891
892static const s8 NCT6106_BEEP_BITS[] = {
893 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
894 9, 10, 11, 12, -1, -1, -1, /* in8..in14 */
895 32, /* global beep enable */
896 24, 25, 26, 27, 28, /* fan1..fan5 */
897 -1, -1, -1, /* unused */
898 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
899 34, -1 /* intrusion0, intrusion1 */
900};
901
902static const u16 NCT6106_REG_TEMP_ALTERNATE[32] = {
903 [14] = 0x51,
904 [15] = 0x52,
905 [16] = 0x54,
906};
907
908static const u16 NCT6106_REG_TEMP_CRIT[32] = {
909 [11] = 0x204,
910 [12] = 0x205,
911};
912
913static enum pwm_enable reg_to_pwm_enable(int pwm, int mode)
914{
915 if (mode == 0 && pwm == 255)
916 return off;
917 return mode + 1;
918}
919
920static int pwm_enable_to_reg(enum pwm_enable mode)
921{
922 if (mode == off)
923 return 0;
924 return mode - 1;
925}
926
927/*
928 * Conversions
929 */
930
931/* 1 is DC mode, output in ms */
932static unsigned int step_time_from_reg(u8 reg, u8 mode)
933{
934 return mode ? 400 * reg : 100 * reg;
935}
936
937static u8 step_time_to_reg(unsigned int msec, u8 mode)
938{
939 return clamp_val((mode ? (msec + 200) / 400 :
940 (msec + 50) / 100), 1, 255);
941}
942
943static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
944{
945 if (reg == 0 || reg == 255)
946 return 0;
947 return 1350000U / (reg << divreg);
948}
949
950static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
951{
952 if ((reg & 0xff1f) == 0xff1f)
953 return 0;
954
955 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
956
957 if (reg == 0)
958 return 0;
959
960 return 1350000U / reg;
961}
962
963static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
964{
965 if (reg == 0 || reg == 0xffff)
966 return 0;
967
968 /*
969 * Even though the registers are 16 bit wide, the fan divisor
970 * still applies.
971 */
972 return 1350000U / (reg << divreg);
973}
974
975static unsigned int fan_from_reg_rpm(u16 reg, unsigned int divreg)
976{
977 return reg;
978}
979
980static u16 fan_to_reg(u32 fan, unsigned int divreg)
981{
982 if (!fan)
983 return 0;
984
985 return (1350000U / fan) >> divreg;
986}
987
988static inline unsigned int
989div_from_reg(u8 reg)
990{
991 return BIT(reg);
992}
993
994/*
995 * Some of the voltage inputs have internal scaling, the tables below
996 * contain 8 (the ADC LSB in mV) * scaling factor * 100
997 */
998static const u16 scale_in[15] = {
999 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800, 800, 800, 800,
1000 800, 800
1001};
1002
1003static inline long in_from_reg(u8 reg, u8 nr)
1004{
1005 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
1006}
1007
1008static inline u8 in_to_reg(u32 val, u8 nr)
1009{
1010 return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
1011}
1012
1013/*
1014 * Data structures and manipulation thereof
1015 */
1016
1017struct nct6775_data {
1018 int addr; /* IO base of hw monitor block */
1019 int sioreg; /* SIO register address */
1020 enum kinds kind;
1021 const char *name;
1022
1023 const struct attribute_group *groups[6];
1024
1025 u16 reg_temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
1026 * 3=temp_crit, 4=temp_lcrit
1027 */
1028 u8 temp_src[NUM_TEMP];
1029 u16 reg_temp_config[NUM_TEMP];
1030 const char * const *temp_label;
1031 u32 temp_mask;
1032 u32 virt_temp_mask;
1033
1034 u16 REG_CONFIG;
1035 u16 REG_VBAT;
1036 u16 REG_DIODE;
1037 u8 DIODE_MASK;
1038
1039 const s8 *ALARM_BITS;
1040 const s8 *BEEP_BITS;
1041
1042 const u16 *REG_VIN;
1043 const u16 *REG_IN_MINMAX[2];
1044
1045 const u16 *REG_TARGET;
1046 const u16 *REG_FAN;
1047 const u16 *REG_FAN_MODE;
1048 const u16 *REG_FAN_MIN;
1049 const u16 *REG_FAN_PULSES;
1050 const u16 *FAN_PULSE_SHIFT;
1051 const u16 *REG_FAN_TIME[3];
1052
1053 const u16 *REG_TOLERANCE_H;
1054
1055 const u8 *REG_PWM_MODE;
1056 const u8 *PWM_MODE_MASK;
1057
1058 const u16 *REG_PWM[7]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1059 * [3]=pwm_max, [4]=pwm_step,
1060 * [5]=weight_duty_step, [6]=weight_duty_base
1061 */
1062 const u16 *REG_PWM_READ;
1063
1064 const u16 *REG_CRITICAL_PWM_ENABLE;
1065 u8 CRITICAL_PWM_ENABLE_MASK;
1066 const u16 *REG_CRITICAL_PWM;
1067
1068 const u16 *REG_AUTO_TEMP;
1069 const u16 *REG_AUTO_PWM;
1070
1071 const u16 *REG_CRITICAL_TEMP;
1072 const u16 *REG_CRITICAL_TEMP_TOLERANCE;
1073
1074 const u16 *REG_TEMP_SOURCE; /* temp register sources */
1075 const u16 *REG_TEMP_SEL;
1076 const u16 *REG_WEIGHT_TEMP_SEL;
1077 const u16 *REG_WEIGHT_TEMP[3]; /* 0=base, 1=tolerance, 2=step */
1078
1079 const u16 *REG_TEMP_OFFSET;
1080
1081 const u16 *REG_ALARM;
1082 const u16 *REG_BEEP;
1083
1084 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
1085 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
1086
1087 struct mutex update_lock;
1088 bool valid; /* true if following fields are valid */
1089 unsigned long last_updated; /* In jiffies */
1090
1091 /* Register values */
1092 u8 bank; /* current register bank */
1093 u8 in_num; /* number of in inputs we have */
1094 u8 in[15][3]; /* [0]=in, [1]=in_max, [2]=in_min */
1095 unsigned int rpm[NUM_FAN];
1096 u16 fan_min[NUM_FAN];
1097 u8 fan_pulses[NUM_FAN];
1098 u8 fan_div[NUM_FAN];
1099 u8 has_pwm;
1100 u8 has_fan; /* some fan inputs can be disabled */
1101 u8 has_fan_min; /* some fans don't have min register */
1102 bool has_fan_div;
1103
1104 u8 num_temp_alarms; /* 2, 3, or 6 */
1105 u8 num_temp_beeps; /* 2, 3, or 6 */
1106 u8 temp_fixed_num; /* 3 or 6 */
1107 u8 temp_type[NUM_TEMP_FIXED];
1108 s8 temp_offset[NUM_TEMP_FIXED];
1109 s16 temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
1110 * 3=temp_crit, 4=temp_lcrit */
1111 u64 alarms;
1112 u64 beeps;
1113
1114 u8 pwm_num; /* number of pwm */
1115 u8 pwm_mode[NUM_FAN]; /* 0->DC variable voltage,
1116 * 1->PWM variable duty cycle
1117 */
1118 enum pwm_enable pwm_enable[NUM_FAN];
1119 /* 0->off
1120 * 1->manual
1121 * 2->thermal cruise mode (also called SmartFan I)
1122 * 3->fan speed cruise mode
1123 * 4->SmartFan III
1124 * 5->enhanced variable thermal cruise (SmartFan IV)
1125 */
1126 u8 pwm[7][NUM_FAN]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1127 * [3]=pwm_max, [4]=pwm_step,
1128 * [5]=weight_duty_step, [6]=weight_duty_base
1129 */
1130
1131 u8 target_temp[NUM_FAN];
1132 u8 target_temp_mask;
1133 u32 target_speed[NUM_FAN];
1134 u32 target_speed_tolerance[NUM_FAN];
1135 u8 speed_tolerance_limit;
1136
1137 u8 temp_tolerance[2][NUM_FAN];
1138 u8 tolerance_mask;
1139
1140 u8 fan_time[3][NUM_FAN]; /* 0 = stop_time, 1 = step_up, 2 = step_down */
1141
1142 /* Automatic fan speed control registers */
1143 int auto_pwm_num;
1144 u8 auto_pwm[NUM_FAN][7];
1145 u8 auto_temp[NUM_FAN][7];
1146 u8 pwm_temp_sel[NUM_FAN];
1147 u8 pwm_weight_temp_sel[NUM_FAN];
1148 u8 weight_temp[3][NUM_FAN]; /* 0->temp_step, 1->temp_step_tol,
1149 * 2->temp_base
1150 */
1151
1152 u8 vid;
1153 u8 vrm;
1154
1155 bool have_vid;
1156
1157 u16 have_temp;
1158 u16 have_temp_fixed;
1159 u16 have_in;
1160
1161 /* Remember extra register values over suspend/resume */
1162 u8 vbat;
1163 u8 fandiv1;
1164 u8 fandiv2;
1165 u8 sio_reg_enable;
1166};
1167
1168struct nct6775_sio_data {
1169 int sioreg;
1170 enum kinds kind;
1171};
1172
1173struct sensor_device_template {
1174 struct device_attribute dev_attr;
1175 union {
1176 struct {
1177 u8 nr;
1178 u8 index;
1179 } s;
1180 int index;
1181 } u;
1182 bool s2; /* true if both index and nr are used */
1183};
1184
1185struct sensor_device_attr_u {
1186 union {
1187 struct sensor_device_attribute a1;
1188 struct sensor_device_attribute_2 a2;
1189 } u;
1190 char name[32];
1191};
1192
1193#define __TEMPLATE_ATTR(_template, _mode, _show, _store) { \
1194 .attr = {.name = _template, .mode = _mode }, \
1195 .show = _show, \
1196 .store = _store, \
1197}
1198
1199#define SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, _index) \
1200 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1201 .u.index = _index, \
1202 .s2 = false }
1203
1204#define SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1205 _nr, _index) \
1206 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1207 .u.s.index = _index, \
1208 .u.s.nr = _nr, \
1209 .s2 = true }
1210
1211#define SENSOR_TEMPLATE(_name, _template, _mode, _show, _store, _index) \
1212static struct sensor_device_template sensor_dev_template_##_name \
1213 = SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, \
1214 _index)
1215
1216#define SENSOR_TEMPLATE_2(_name, _template, _mode, _show, _store, \
1217 _nr, _index) \
1218static struct sensor_device_template sensor_dev_template_##_name \
1219 = SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1220 _nr, _index)
1221
1222struct sensor_template_group {
1223 struct sensor_device_template **templates;
1224 umode_t (*is_visible)(struct kobject *, struct attribute *, int);
1225 int base;
1226};
1227
1228static struct attribute_group *
1229nct6775_create_attr_group(struct device *dev,
1230 const struct sensor_template_group *tg,
1231 int repeat)
1232{
1233 struct attribute_group *group;
1234 struct sensor_device_attr_u *su;
1235 struct sensor_device_attribute *a;
1236 struct sensor_device_attribute_2 *a2;
1237 struct attribute **attrs;
1238 struct sensor_device_template **t;
1239 int i, count;
1240
1241 if (repeat <= 0)
1242 return ERR_PTR(-EINVAL);
1243
1244 t = tg->templates;
1245 for (count = 0; *t; t++, count++)
1246 ;
1247
1248 if (count == 0)
1249 return ERR_PTR(-EINVAL);
1250
1251 group = devm_kzalloc(dev, sizeof(*group), GFP_KERNEL);
1252 if (group == NULL)
1253 return ERR_PTR(-ENOMEM);
1254
1255 attrs = devm_kcalloc(dev, repeat * count + 1, sizeof(*attrs),
1256 GFP_KERNEL);
1257 if (attrs == NULL)
1258 return ERR_PTR(-ENOMEM);
1259
1260 su = devm_kzalloc(dev, array3_size(repeat, count, sizeof(*su)),
1261 GFP_KERNEL);
1262 if (su == NULL)
1263 return ERR_PTR(-ENOMEM);
1264
1265 group->attrs = attrs;
1266 group->is_visible = tg->is_visible;
1267
1268 for (i = 0; i < repeat; i++) {
1269 t = tg->templates;
1270 while (*t != NULL) {
1271 snprintf(su->name, sizeof(su->name),
1272 (*t)->dev_attr.attr.name, tg->base + i);
1273 if ((*t)->s2) {
1274 a2 = &su->u.a2;
1275 sysfs_attr_init(&a2->dev_attr.attr);
1276 a2->dev_attr.attr.name = su->name;
1277 a2->nr = (*t)->u.s.nr + i;
1278 a2->index = (*t)->u.s.index;
1279 a2->dev_attr.attr.mode =
1280 (*t)->dev_attr.attr.mode;
1281 a2->dev_attr.show = (*t)->dev_attr.show;
1282 a2->dev_attr.store = (*t)->dev_attr.store;
1283 *attrs = &a2->dev_attr.attr;
1284 } else {
1285 a = &su->u.a1;
1286 sysfs_attr_init(&a->dev_attr.attr);
1287 a->dev_attr.attr.name = su->name;
1288 a->index = (*t)->u.index + i;
1289 a->dev_attr.attr.mode =
1290 (*t)->dev_attr.attr.mode;
1291 a->dev_attr.show = (*t)->dev_attr.show;
1292 a->dev_attr.store = (*t)->dev_attr.store;
1293 *attrs = &a->dev_attr.attr;
1294 }
1295 attrs++;
1296 su++;
1297 t++;
1298 }
1299 }
1300
1301 return group;
1302}
1303
1304static bool is_word_sized(struct nct6775_data *data, u16 reg)
1305{
1306 switch (data->kind) {
1307 case nct6106:
1308 return reg == 0x20 || reg == 0x22 || reg == 0x24 ||
1309 reg == 0xe0 || reg == 0xe2 || reg == 0xe4 ||
1310 reg == 0x111 || reg == 0x121 || reg == 0x131;
1311 case nct6775:
1312 return (((reg & 0xff00) == 0x100 ||
1313 (reg & 0xff00) == 0x200) &&
1314 ((reg & 0x00ff) == 0x50 ||
1315 (reg & 0x00ff) == 0x53 ||
1316 (reg & 0x00ff) == 0x55)) ||
1317 (reg & 0xfff0) == 0x630 ||
1318 reg == 0x640 || reg == 0x642 ||
1319 reg == 0x662 ||
1320 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1321 reg == 0x73 || reg == 0x75 || reg == 0x77;
1322 case nct6776:
1323 return (((reg & 0xff00) == 0x100 ||
1324 (reg & 0xff00) == 0x200) &&
1325 ((reg & 0x00ff) == 0x50 ||
1326 (reg & 0x00ff) == 0x53 ||
1327 (reg & 0x00ff) == 0x55)) ||
1328 (reg & 0xfff0) == 0x630 ||
1329 reg == 0x402 ||
1330 reg == 0x640 || reg == 0x642 ||
1331 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1332 reg == 0x73 || reg == 0x75 || reg == 0x77;
1333 case nct6779:
1334 case nct6791:
1335 case nct6792:
1336 case nct6793:
1337 case nct6795:
1338 case nct6796:
1339 case nct6797:
1340 case nct6798:
1341 return reg == 0x150 || reg == 0x153 || reg == 0x155 ||
1342 (reg & 0xfff0) == 0x4c0 ||
1343 reg == 0x402 ||
1344 reg == 0x63a || reg == 0x63c || reg == 0x63e ||
1345 reg == 0x640 || reg == 0x642 || reg == 0x64a ||
1346 reg == 0x64c ||
1347 reg == 0x73 || reg == 0x75 || reg == 0x77 || reg == 0x79 ||
1348 reg == 0x7b || reg == 0x7d;
1349 }
1350 return false;
1351}
1352
1353/*
1354 * On older chips, only registers 0x50-0x5f are banked.
1355 * On more recent chips, all registers are banked.
1356 * Assume that is the case and set the bank number for each access.
1357 * Cache the bank number so it only needs to be set if it changes.
1358 */
1359static inline void nct6775_set_bank(struct nct6775_data *data, u16 reg)
1360{
1361 u8 bank = reg >> 8;
1362
1363 if (data->bank != bank) {
1364 outb_p(NCT6775_REG_BANK, data->addr + ADDR_REG_OFFSET);
1365 outb_p(bank, data->addr + DATA_REG_OFFSET);
1366 data->bank = bank;
1367 }
1368}
1369
1370static u16 nct6775_read_value(struct nct6775_data *data, u16 reg)
1371{
1372 int res, word_sized = is_word_sized(data, reg);
1373
1374 nct6775_set_bank(data, reg);
1375 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1376 res = inb_p(data->addr + DATA_REG_OFFSET);
1377 if (word_sized) {
1378 outb_p((reg & 0xff) + 1,
1379 data->addr + ADDR_REG_OFFSET);
1380 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
1381 }
1382 return res;
1383}
1384
1385static int nct6775_write_value(struct nct6775_data *data, u16 reg, u16 value)
1386{
1387 int word_sized = is_word_sized(data, reg);
1388
1389 nct6775_set_bank(data, reg);
1390 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1391 if (word_sized) {
1392 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
1393 outb_p((reg & 0xff) + 1,
1394 data->addr + ADDR_REG_OFFSET);
1395 }
1396 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
1397 return 0;
1398}
1399
1400/* We left-align 8-bit temperature values to make the code simpler */
1401static u16 nct6775_read_temp(struct nct6775_data *data, u16 reg)
1402{
1403 u16 res;
1404
1405 res = nct6775_read_value(data, reg);
1406 if (!is_word_sized(data, reg))
1407 res <<= 8;
1408
1409 return res;
1410}
1411
1412static int nct6775_write_temp(struct nct6775_data *data, u16 reg, u16 value)
1413{
1414 if (!is_word_sized(data, reg))
1415 value >>= 8;
1416 return nct6775_write_value(data, reg, value);
1417}
1418
1419/* This function assumes that the caller holds data->update_lock */
1420static void nct6775_write_fan_div(struct nct6775_data *data, int nr)
1421{
1422 u8 reg;
1423
1424 switch (nr) {
1425 case 0:
1426 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
1427 | (data->fan_div[0] & 0x7);
1428 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1429 break;
1430 case 1:
1431 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
1432 | ((data->fan_div[1] << 4) & 0x70);
1433 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1434 break;
1435 case 2:
1436 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
1437 | (data->fan_div[2] & 0x7);
1438 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1439 break;
1440 case 3:
1441 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
1442 | ((data->fan_div[3] << 4) & 0x70);
1443 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1444 break;
1445 }
1446}
1447
1448static void nct6775_write_fan_div_common(struct nct6775_data *data, int nr)
1449{
1450 if (data->kind == nct6775)
1451 nct6775_write_fan_div(data, nr);
1452}
1453
1454static void nct6775_update_fan_div(struct nct6775_data *data)
1455{
1456 u8 i;
1457
1458 i = nct6775_read_value(data, NCT6775_REG_FANDIV1);
1459 data->fan_div[0] = i & 0x7;
1460 data->fan_div[1] = (i & 0x70) >> 4;
1461 i = nct6775_read_value(data, NCT6775_REG_FANDIV2);
1462 data->fan_div[2] = i & 0x7;
1463 if (data->has_fan & BIT(3))
1464 data->fan_div[3] = (i & 0x70) >> 4;
1465}
1466
1467static void nct6775_update_fan_div_common(struct nct6775_data *data)
1468{
1469 if (data->kind == nct6775)
1470 nct6775_update_fan_div(data);
1471}
1472
1473static void nct6775_init_fan_div(struct nct6775_data *data)
1474{
1475 int i;
1476
1477 nct6775_update_fan_div_common(data);
1478 /*
1479 * For all fans, start with highest divider value if the divider
1480 * register is not initialized. This ensures that we get a
1481 * reading from the fan count register, even if it is not optimal.
1482 * We'll compute a better divider later on.
1483 */
1484 for (i = 0; i < ARRAY_SIZE(data->fan_div); i++) {
1485 if (!(data->has_fan & BIT(i)))
1486 continue;
1487 if (data->fan_div[i] == 0) {
1488 data->fan_div[i] = 7;
1489 nct6775_write_fan_div_common(data, i);
1490 }
1491 }
1492}
1493
1494static void nct6775_init_fan_common(struct device *dev,
1495 struct nct6775_data *data)
1496{
1497 int i;
1498 u8 reg;
1499
1500 if (data->has_fan_div)
1501 nct6775_init_fan_div(data);
1502
1503 /*
1504 * If fan_min is not set (0), set it to 0xff to disable it. This
1505 * prevents the unnecessary warning when fanX_min is reported as 0.
1506 */
1507 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
1508 if (data->has_fan_min & BIT(i)) {
1509 reg = nct6775_read_value(data, data->REG_FAN_MIN[i]);
1510 if (!reg)
1511 nct6775_write_value(data, data->REG_FAN_MIN[i],
1512 data->has_fan_div ? 0xff
1513 : 0xff1f);
1514 }
1515 }
1516}
1517
1518static void nct6775_select_fan_div(struct device *dev,
1519 struct nct6775_data *data, int nr, u16 reg)
1520{
1521 u8 fan_div = data->fan_div[nr];
1522 u16 fan_min;
1523
1524 if (!data->has_fan_div)
1525 return;
1526
1527 /*
1528 * If we failed to measure the fan speed, or the reported value is not
1529 * in the optimal range, and the clock divider can be modified,
1530 * let's try that for next time.
1531 */
1532 if (reg == 0x00 && fan_div < 0x07)
1533 fan_div++;
1534 else if (reg != 0x00 && reg < 0x30 && fan_div > 0)
1535 fan_div--;
1536
1537 if (fan_div != data->fan_div[nr]) {
1538 dev_dbg(dev, "Modifying fan%d clock divider from %u to %u\n",
1539 nr + 1, div_from_reg(data->fan_div[nr]),
1540 div_from_reg(fan_div));
1541
1542 /* Preserve min limit if possible */
1543 if (data->has_fan_min & BIT(nr)) {
1544 fan_min = data->fan_min[nr];
1545 if (fan_div > data->fan_div[nr]) {
1546 if (fan_min != 255 && fan_min > 1)
1547 fan_min >>= 1;
1548 } else {
1549 if (fan_min != 255) {
1550 fan_min <<= 1;
1551 if (fan_min > 254)
1552 fan_min = 254;
1553 }
1554 }
1555 if (fan_min != data->fan_min[nr]) {
1556 data->fan_min[nr] = fan_min;
1557 nct6775_write_value(data, data->REG_FAN_MIN[nr],
1558 fan_min);
1559 }
1560 }
1561 data->fan_div[nr] = fan_div;
1562 nct6775_write_fan_div_common(data, nr);
1563 }
1564}
1565
1566static void nct6775_update_pwm(struct device *dev)
1567{
1568 struct nct6775_data *data = dev_get_drvdata(dev);
1569 int i, j;
1570 int fanmodecfg, reg;
1571 bool duty_is_dc;
1572
1573 for (i = 0; i < data->pwm_num; i++) {
1574 if (!(data->has_pwm & BIT(i)))
1575 continue;
1576
1577 duty_is_dc = data->REG_PWM_MODE[i] &&
1578 (nct6775_read_value(data, data->REG_PWM_MODE[i])
1579 & data->PWM_MODE_MASK[i]);
1580 data->pwm_mode[i] = !duty_is_dc;
1581
1582 fanmodecfg = nct6775_read_value(data, data->REG_FAN_MODE[i]);
1583 for (j = 0; j < ARRAY_SIZE(data->REG_PWM); j++) {
1584 if (data->REG_PWM[j] && data->REG_PWM[j][i]) {
1585 data->pwm[j][i]
1586 = nct6775_read_value(data,
1587 data->REG_PWM[j][i]);
1588 }
1589 }
1590
1591 data->pwm_enable[i] = reg_to_pwm_enable(data->pwm[0][i],
1592 (fanmodecfg >> 4) & 7);
1593
1594 if (!data->temp_tolerance[0][i] ||
1595 data->pwm_enable[i] != speed_cruise)
1596 data->temp_tolerance[0][i] = fanmodecfg & 0x0f;
1597 if (!data->target_speed_tolerance[i] ||
1598 data->pwm_enable[i] == speed_cruise) {
1599 u8 t = fanmodecfg & 0x0f;
1600
1601 if (data->REG_TOLERANCE_H) {
1602 t |= (nct6775_read_value(data,
1603 data->REG_TOLERANCE_H[i]) & 0x70) >> 1;
1604 }
1605 data->target_speed_tolerance[i] = t;
1606 }
1607
1608 data->temp_tolerance[1][i] =
1609 nct6775_read_value(data,
1610 data->REG_CRITICAL_TEMP_TOLERANCE[i]);
1611
1612 reg = nct6775_read_value(data, data->REG_TEMP_SEL[i]);
1613 data->pwm_temp_sel[i] = reg & 0x1f;
1614 /* If fan can stop, report floor as 0 */
1615 if (reg & 0x80)
1616 data->pwm[2][i] = 0;
1617
1618 if (!data->REG_WEIGHT_TEMP_SEL[i])
1619 continue;
1620
1621 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[i]);
1622 data->pwm_weight_temp_sel[i] = reg & 0x1f;
1623 /* If weight is disabled, report weight source as 0 */
1624 if (!(reg & 0x80))
1625 data->pwm_weight_temp_sel[i] = 0;
1626
1627 /* Weight temp data */
1628 for (j = 0; j < ARRAY_SIZE(data->weight_temp); j++) {
1629 data->weight_temp[j][i]
1630 = nct6775_read_value(data,
1631 data->REG_WEIGHT_TEMP[j][i]);
1632 }
1633 }
1634}
1635
1636static void nct6775_update_pwm_limits(struct device *dev)
1637{
1638 struct nct6775_data *data = dev_get_drvdata(dev);
1639 int i, j;
1640 u8 reg;
1641 u16 reg_t;
1642
1643 for (i = 0; i < data->pwm_num; i++) {
1644 if (!(data->has_pwm & BIT(i)))
1645 continue;
1646
1647 for (j = 0; j < ARRAY_SIZE(data->fan_time); j++) {
1648 data->fan_time[j][i] =
1649 nct6775_read_value(data, data->REG_FAN_TIME[j][i]);
1650 }
1651
1652 reg_t = nct6775_read_value(data, data->REG_TARGET[i]);
1653 /* Update only in matching mode or if never updated */
1654 if (!data->target_temp[i] ||
1655 data->pwm_enable[i] == thermal_cruise)
1656 data->target_temp[i] = reg_t & data->target_temp_mask;
1657 if (!data->target_speed[i] ||
1658 data->pwm_enable[i] == speed_cruise) {
1659 if (data->REG_TOLERANCE_H) {
1660 reg_t |= (nct6775_read_value(data,
1661 data->REG_TOLERANCE_H[i]) & 0x0f) << 8;
1662 }
1663 data->target_speed[i] = reg_t;
1664 }
1665
1666 for (j = 0; j < data->auto_pwm_num; j++) {
1667 data->auto_pwm[i][j] =
1668 nct6775_read_value(data,
1669 NCT6775_AUTO_PWM(data, i, j));
1670 data->auto_temp[i][j] =
1671 nct6775_read_value(data,
1672 NCT6775_AUTO_TEMP(data, i, j));
1673 }
1674
1675 /* critical auto_pwm temperature data */
1676 data->auto_temp[i][data->auto_pwm_num] =
1677 nct6775_read_value(data, data->REG_CRITICAL_TEMP[i]);
1678
1679 switch (data->kind) {
1680 case nct6775:
1681 reg = nct6775_read_value(data,
1682 NCT6775_REG_CRITICAL_ENAB[i]);
1683 data->auto_pwm[i][data->auto_pwm_num] =
1684 (reg & 0x02) ? 0xff : 0x00;
1685 break;
1686 case nct6776:
1687 data->auto_pwm[i][data->auto_pwm_num] = 0xff;
1688 break;
1689 case nct6106:
1690 case nct6779:
1691 case nct6791:
1692 case nct6792:
1693 case nct6793:
1694 case nct6795:
1695 case nct6796:
1696 case nct6797:
1697 case nct6798:
1698 reg = nct6775_read_value(data,
1699 data->REG_CRITICAL_PWM_ENABLE[i]);
1700 if (reg & data->CRITICAL_PWM_ENABLE_MASK)
1701 reg = nct6775_read_value(data,
1702 data->REG_CRITICAL_PWM[i]);
1703 else
1704 reg = 0xff;
1705 data->auto_pwm[i][data->auto_pwm_num] = reg;
1706 break;
1707 }
1708 }
1709}
1710
1711static struct nct6775_data *nct6775_update_device(struct device *dev)
1712{
1713 struct nct6775_data *data = dev_get_drvdata(dev);
1714 int i, j;
1715
1716 mutex_lock(&data->update_lock);
1717
1718 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1719 || !data->valid) {
1720 /* Fan clock dividers */
1721 nct6775_update_fan_div_common(data);
1722
1723 /* Measured voltages and limits */
1724 for (i = 0; i < data->in_num; i++) {
1725 if (!(data->have_in & BIT(i)))
1726 continue;
1727
1728 data->in[i][0] = nct6775_read_value(data,
1729 data->REG_VIN[i]);
1730 data->in[i][1] = nct6775_read_value(data,
1731 data->REG_IN_MINMAX[0][i]);
1732 data->in[i][2] = nct6775_read_value(data,
1733 data->REG_IN_MINMAX[1][i]);
1734 }
1735
1736 /* Measured fan speeds and limits */
1737 for (i = 0; i < ARRAY_SIZE(data->rpm); i++) {
1738 u16 reg;
1739
1740 if (!(data->has_fan & BIT(i)))
1741 continue;
1742
1743 reg = nct6775_read_value(data, data->REG_FAN[i]);
1744 data->rpm[i] = data->fan_from_reg(reg,
1745 data->fan_div[i]);
1746
1747 if (data->has_fan_min & BIT(i))
1748 data->fan_min[i] = nct6775_read_value(data,
1749 data->REG_FAN_MIN[i]);
1750
1751 if (data->REG_FAN_PULSES[i]) {
1752 data->fan_pulses[i] =
1753 (nct6775_read_value(data,
1754 data->REG_FAN_PULSES[i])
1755 >> data->FAN_PULSE_SHIFT[i]) & 0x03;
1756 }
1757
1758 nct6775_select_fan_div(dev, data, i, reg);
1759 }
1760
1761 nct6775_update_pwm(dev);
1762 nct6775_update_pwm_limits(dev);
1763
1764 /* Measured temperatures and limits */
1765 for (i = 0; i < NUM_TEMP; i++) {
1766 if (!(data->have_temp & BIT(i)))
1767 continue;
1768 for (j = 0; j < ARRAY_SIZE(data->reg_temp); j++) {
1769 if (data->reg_temp[j][i])
1770 data->temp[j][i]
1771 = nct6775_read_temp(data,
1772 data->reg_temp[j][i]);
1773 }
1774 if (i >= NUM_TEMP_FIXED ||
1775 !(data->have_temp_fixed & BIT(i)))
1776 continue;
1777 data->temp_offset[i]
1778 = nct6775_read_value(data, data->REG_TEMP_OFFSET[i]);
1779 }
1780
1781 data->alarms = 0;
1782 for (i = 0; i < NUM_REG_ALARM; i++) {
1783 u8 alarm;
1784
1785 if (!data->REG_ALARM[i])
1786 continue;
1787 alarm = nct6775_read_value(data, data->REG_ALARM[i]);
1788 data->alarms |= ((u64)alarm) << (i << 3);
1789 }
1790
1791 data->beeps = 0;
1792 for (i = 0; i < NUM_REG_BEEP; i++) {
1793 u8 beep;
1794
1795 if (!data->REG_BEEP[i])
1796 continue;
1797 beep = nct6775_read_value(data, data->REG_BEEP[i]);
1798 data->beeps |= ((u64)beep) << (i << 3);
1799 }
1800
1801 data->last_updated = jiffies;
1802 data->valid = true;
1803 }
1804
1805 mutex_unlock(&data->update_lock);
1806 return data;
1807}
1808
1809/*
1810 * Sysfs callback functions
1811 */
1812static ssize_t
1813show_in_reg(struct device *dev, struct device_attribute *attr, char *buf)
1814{
1815 struct nct6775_data *data = nct6775_update_device(dev);
1816 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1817 int index = sattr->index;
1818 int nr = sattr->nr;
1819
1820 return sprintf(buf, "%ld\n", in_from_reg(data->in[nr][index], nr));
1821}
1822
1823static ssize_t
1824store_in_reg(struct device *dev, struct device_attribute *attr, const char *buf,
1825 size_t count)
1826{
1827 struct nct6775_data *data = dev_get_drvdata(dev);
1828 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1829 int index = sattr->index;
1830 int nr = sattr->nr;
1831 unsigned long val;
1832 int err;
1833
1834 err = kstrtoul(buf, 10, &val);
1835 if (err < 0)
1836 return err;
1837 mutex_lock(&data->update_lock);
1838 data->in[nr][index] = in_to_reg(val, nr);
1839 nct6775_write_value(data, data->REG_IN_MINMAX[index - 1][nr],
1840 data->in[nr][index]);
1841 mutex_unlock(&data->update_lock);
1842 return count;
1843}
1844
1845static ssize_t
1846show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1847{
1848 struct nct6775_data *data = nct6775_update_device(dev);
1849 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1850 int nr = data->ALARM_BITS[sattr->index];
1851
1852 return sprintf(buf, "%u\n",
1853 (unsigned int)((data->alarms >> nr) & 0x01));
1854}
1855
1856static int find_temp_source(struct nct6775_data *data, int index, int count)
1857{
1858 int source = data->temp_src[index];
1859 int nr;
1860
1861 for (nr = 0; nr < count; nr++) {
1862 int src;
1863
1864 src = nct6775_read_value(data,
1865 data->REG_TEMP_SOURCE[nr]) & 0x1f;
1866 if (src == source)
1867 return nr;
1868 }
1869 return -ENODEV;
1870}
1871
1872static ssize_t
1873show_temp_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1874{
1875 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1876 struct nct6775_data *data = nct6775_update_device(dev);
1877 unsigned int alarm = 0;
1878 int nr;
1879
1880 /*
1881 * For temperatures, there is no fixed mapping from registers to alarm
1882 * bits. Alarm bits are determined by the temperature source mapping.
1883 */
1884 nr = find_temp_source(data, sattr->index, data->num_temp_alarms);
1885 if (nr >= 0) {
1886 int bit = data->ALARM_BITS[nr + TEMP_ALARM_BASE];
1887
1888 alarm = (data->alarms >> bit) & 0x01;
1889 }
1890 return sprintf(buf, "%u\n", alarm);
1891}
1892
1893static ssize_t
1894show_beep(struct device *dev, struct device_attribute *attr, char *buf)
1895{
1896 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1897 struct nct6775_data *data = nct6775_update_device(dev);
1898 int nr = data->BEEP_BITS[sattr->index];
1899
1900 return sprintf(buf, "%u\n",
1901 (unsigned int)((data->beeps >> nr) & 0x01));
1902}
1903
1904static ssize_t
1905store_beep(struct device *dev, struct device_attribute *attr, const char *buf,
1906 size_t count)
1907{
1908 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1909 struct nct6775_data *data = dev_get_drvdata(dev);
1910 int nr = data->BEEP_BITS[sattr->index];
1911 int regindex = nr >> 3;
1912 unsigned long val;
1913 int err;
1914
1915 err = kstrtoul(buf, 10, &val);
1916 if (err < 0)
1917 return err;
1918 if (val > 1)
1919 return -EINVAL;
1920
1921 mutex_lock(&data->update_lock);
1922 if (val)
1923 data->beeps |= (1ULL << nr);
1924 else
1925 data->beeps &= ~(1ULL << nr);
1926 nct6775_write_value(data, data->REG_BEEP[regindex],
1927 (data->beeps >> (regindex << 3)) & 0xff);
1928 mutex_unlock(&data->update_lock);
1929 return count;
1930}
1931
1932static ssize_t
1933show_temp_beep(struct device *dev, struct device_attribute *attr, char *buf)
1934{
1935 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1936 struct nct6775_data *data = nct6775_update_device(dev);
1937 unsigned int beep = 0;
1938 int nr;
1939
1940 /*
1941 * For temperatures, there is no fixed mapping from registers to beep
1942 * enable bits. Beep enable bits are determined by the temperature
1943 * source mapping.
1944 */
1945 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1946 if (nr >= 0) {
1947 int bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1948
1949 beep = (data->beeps >> bit) & 0x01;
1950 }
1951 return sprintf(buf, "%u\n", beep);
1952}
1953
1954static ssize_t
1955store_temp_beep(struct device *dev, struct device_attribute *attr,
1956 const char *buf, size_t count)
1957{
1958 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1959 struct nct6775_data *data = dev_get_drvdata(dev);
1960 int nr, bit, regindex;
1961 unsigned long val;
1962 int err;
1963
1964 err = kstrtoul(buf, 10, &val);
1965 if (err < 0)
1966 return err;
1967 if (val > 1)
1968 return -EINVAL;
1969
1970 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1971 if (nr < 0)
1972 return nr;
1973
1974 bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1975 regindex = bit >> 3;
1976
1977 mutex_lock(&data->update_lock);
1978 if (val)
1979 data->beeps |= (1ULL << bit);
1980 else
1981 data->beeps &= ~(1ULL << bit);
1982 nct6775_write_value(data, data->REG_BEEP[regindex],
1983 (data->beeps >> (regindex << 3)) & 0xff);
1984 mutex_unlock(&data->update_lock);
1985
1986 return count;
1987}
1988
1989static umode_t nct6775_in_is_visible(struct kobject *kobj,
1990 struct attribute *attr, int index)
1991{
1992 struct device *dev = container_of(kobj, struct device, kobj);
1993 struct nct6775_data *data = dev_get_drvdata(dev);
1994 int in = index / 5; /* voltage index */
1995
1996 if (!(data->have_in & BIT(in)))
1997 return 0;
1998
1999 return attr->mode;
2000}
2001
2002SENSOR_TEMPLATE_2(in_input, "in%d_input", S_IRUGO, show_in_reg, NULL, 0, 0);
2003SENSOR_TEMPLATE(in_alarm, "in%d_alarm", S_IRUGO, show_alarm, NULL, 0);
2004SENSOR_TEMPLATE(in_beep, "in%d_beep", S_IWUSR | S_IRUGO, show_beep, store_beep,
2005 0);
2006SENSOR_TEMPLATE_2(in_min, "in%d_min", S_IWUSR | S_IRUGO, show_in_reg,
2007 store_in_reg, 0, 1);
2008SENSOR_TEMPLATE_2(in_max, "in%d_max", S_IWUSR | S_IRUGO, show_in_reg,
2009 store_in_reg, 0, 2);
2010
2011/*
2012 * nct6775_in_is_visible uses the index into the following array
2013 * to determine if attributes should be created or not.
2014 * Any change in order or content must be matched.
2015 */
2016static struct sensor_device_template *nct6775_attributes_in_template[] = {
2017 &sensor_dev_template_in_input,
2018 &sensor_dev_template_in_alarm,
2019 &sensor_dev_template_in_beep,
2020 &sensor_dev_template_in_min,
2021 &sensor_dev_template_in_max,
2022 NULL
2023};
2024
2025static const struct sensor_template_group nct6775_in_template_group = {
2026 .templates = nct6775_attributes_in_template,
2027 .is_visible = nct6775_in_is_visible,
2028};
2029
2030static ssize_t
2031show_fan(struct device *dev, struct device_attribute *attr, char *buf)
2032{
2033 struct nct6775_data *data = nct6775_update_device(dev);
2034 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2035 int nr = sattr->index;
2036
2037 return sprintf(buf, "%d\n", data->rpm[nr]);
2038}
2039
2040static ssize_t
2041show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
2042{
2043 struct nct6775_data *data = nct6775_update_device(dev);
2044 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2045 int nr = sattr->index;
2046
2047 return sprintf(buf, "%d\n",
2048 data->fan_from_reg_min(data->fan_min[nr],
2049 data->fan_div[nr]));
2050}
2051
2052static ssize_t
2053show_fan_div(struct device *dev, struct device_attribute *attr, char *buf)
2054{
2055 struct nct6775_data *data = nct6775_update_device(dev);
2056 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2057 int nr = sattr->index;
2058
2059 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
2060}
2061
2062static ssize_t
2063store_fan_min(struct device *dev, struct device_attribute *attr,
2064 const char *buf, size_t count)
2065{
2066 struct nct6775_data *data = dev_get_drvdata(dev);
2067 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2068 int nr = sattr->index;
2069 unsigned long val;
2070 unsigned int reg;
2071 u8 new_div;
2072 int err;
2073
2074 err = kstrtoul(buf, 10, &val);
2075 if (err < 0)
2076 return err;
2077
2078 mutex_lock(&data->update_lock);
2079 if (!data->has_fan_div) {
2080 /* NCT6776F or NCT6779D; we know this is a 13 bit register */
2081 if (!val) {
2082 val = 0xff1f;
2083 } else {
2084 if (val > 1350000U)
2085 val = 135000U;
2086 val = 1350000U / val;
2087 val = (val & 0x1f) | ((val << 3) & 0xff00);
2088 }
2089 data->fan_min[nr] = val;
2090 goto write_min; /* Leave fan divider alone */
2091 }
2092 if (!val) {
2093 /* No min limit, alarm disabled */
2094 data->fan_min[nr] = 255;
2095 new_div = data->fan_div[nr]; /* No change */
2096 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
2097 goto write_div;
2098 }
2099 reg = 1350000U / val;
2100 if (reg >= 128 * 255) {
2101 /*
2102 * Speed below this value cannot possibly be represented,
2103 * even with the highest divider (128)
2104 */
2105 data->fan_min[nr] = 254;
2106 new_div = 7; /* 128 == BIT(7) */
2107 dev_warn(dev,
2108 "fan%u low limit %lu below minimum %u, set to minimum\n",
2109 nr + 1, val, data->fan_from_reg_min(254, 7));
2110 } else if (!reg) {
2111 /*
2112 * Speed above this value cannot possibly be represented,
2113 * even with the lowest divider (1)
2114 */
2115 data->fan_min[nr] = 1;
2116 new_div = 0; /* 1 == BIT(0) */
2117 dev_warn(dev,
2118 "fan%u low limit %lu above maximum %u, set to maximum\n",
2119 nr + 1, val, data->fan_from_reg_min(1, 0));
2120 } else {
2121 /*
2122 * Automatically pick the best divider, i.e. the one such
2123 * that the min limit will correspond to a register value
2124 * in the 96..192 range
2125 */
2126 new_div = 0;
2127 while (reg > 192 && new_div < 7) {
2128 reg >>= 1;
2129 new_div++;
2130 }
2131 data->fan_min[nr] = reg;
2132 }
2133
2134write_div:
2135 /*
2136 * Write both the fan clock divider (if it changed) and the new
2137 * fan min (unconditionally)
2138 */
2139 if (new_div != data->fan_div[nr]) {
2140 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
2141 nr + 1, div_from_reg(data->fan_div[nr]),
2142 div_from_reg(new_div));
2143 data->fan_div[nr] = new_div;
2144 nct6775_write_fan_div_common(data, nr);
2145 /* Give the chip time to sample a new speed value */
2146 data->last_updated = jiffies;
2147 }
2148
2149write_min:
2150 nct6775_write_value(data, data->REG_FAN_MIN[nr], data->fan_min[nr]);
2151 mutex_unlock(&data->update_lock);
2152
2153 return count;
2154}
2155
2156static ssize_t
2157show_fan_pulses(struct device *dev, struct device_attribute *attr, char *buf)
2158{
2159 struct nct6775_data *data = nct6775_update_device(dev);
2160 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2161 int p = data->fan_pulses[sattr->index];
2162
2163 return sprintf(buf, "%d\n", p ? : 4);
2164}
2165
2166static ssize_t
2167store_fan_pulses(struct device *dev, struct device_attribute *attr,
2168 const char *buf, size_t count)
2169{
2170 struct nct6775_data *data = dev_get_drvdata(dev);
2171 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2172 int nr = sattr->index;
2173 unsigned long val;
2174 int err;
2175 u8 reg;
2176
2177 err = kstrtoul(buf, 10, &val);
2178 if (err < 0)
2179 return err;
2180
2181 if (val > 4)
2182 return -EINVAL;
2183
2184 mutex_lock(&data->update_lock);
2185 data->fan_pulses[nr] = val & 3;
2186 reg = nct6775_read_value(data, data->REG_FAN_PULSES[nr]);
2187 reg &= ~(0x03 << data->FAN_PULSE_SHIFT[nr]);
2188 reg |= (val & 3) << data->FAN_PULSE_SHIFT[nr];
2189 nct6775_write_value(data, data->REG_FAN_PULSES[nr], reg);
2190 mutex_unlock(&data->update_lock);
2191
2192 return count;
2193}
2194
2195static umode_t nct6775_fan_is_visible(struct kobject *kobj,
2196 struct attribute *attr, int index)
2197{
2198 struct device *dev = container_of(kobj, struct device, kobj);
2199 struct nct6775_data *data = dev_get_drvdata(dev);
2200 int fan = index / 6; /* fan index */
2201 int nr = index % 6; /* attribute index */
2202
2203 if (!(data->has_fan & BIT(fan)))
2204 return 0;
2205
2206 if (nr == 1 && data->ALARM_BITS[FAN_ALARM_BASE + fan] == -1)
2207 return 0;
2208 if (nr == 2 && data->BEEP_BITS[FAN_ALARM_BASE + fan] == -1)
2209 return 0;
2210 if (nr == 3 && !data->REG_FAN_PULSES[fan])
2211 return 0;
2212 if (nr == 4 && !(data->has_fan_min & BIT(fan)))
2213 return 0;
2214 if (nr == 5 && data->kind != nct6775)
2215 return 0;
2216
2217 return attr->mode;
2218}
2219
2220SENSOR_TEMPLATE(fan_input, "fan%d_input", S_IRUGO, show_fan, NULL, 0);
2221SENSOR_TEMPLATE(fan_alarm, "fan%d_alarm", S_IRUGO, show_alarm, NULL,
2222 FAN_ALARM_BASE);
2223SENSOR_TEMPLATE(fan_beep, "fan%d_beep", S_IWUSR | S_IRUGO, show_beep,
2224 store_beep, FAN_ALARM_BASE);
2225SENSOR_TEMPLATE(fan_pulses, "fan%d_pulses", S_IWUSR | S_IRUGO, show_fan_pulses,
2226 store_fan_pulses, 0);
2227SENSOR_TEMPLATE(fan_min, "fan%d_min", S_IWUSR | S_IRUGO, show_fan_min,
2228 store_fan_min, 0);
2229SENSOR_TEMPLATE(fan_div, "fan%d_div", S_IRUGO, show_fan_div, NULL, 0);
2230
2231/*
2232 * nct6775_fan_is_visible uses the index into the following array
2233 * to determine if attributes should be created or not.
2234 * Any change in order or content must be matched.
2235 */
2236static struct sensor_device_template *nct6775_attributes_fan_template[] = {
2237 &sensor_dev_template_fan_input,
2238 &sensor_dev_template_fan_alarm, /* 1 */
2239 &sensor_dev_template_fan_beep, /* 2 */
2240 &sensor_dev_template_fan_pulses,
2241 &sensor_dev_template_fan_min, /* 4 */
2242 &sensor_dev_template_fan_div, /* 5 */
2243 NULL
2244};
2245
2246static const struct sensor_template_group nct6775_fan_template_group = {
2247 .templates = nct6775_attributes_fan_template,
2248 .is_visible = nct6775_fan_is_visible,
2249 .base = 1,
2250};
2251
2252static ssize_t
2253show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
2254{
2255 struct nct6775_data *data = nct6775_update_device(dev);
2256 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2257 int nr = sattr->index;
2258
2259 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
2260}
2261
2262static ssize_t
2263show_temp(struct device *dev, struct device_attribute *attr, char *buf)
2264{
2265 struct nct6775_data *data = nct6775_update_device(dev);
2266 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2267 int nr = sattr->nr;
2268 int index = sattr->index;
2269
2270 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->temp[index][nr]));
2271}
2272
2273static ssize_t
2274store_temp(struct device *dev, struct device_attribute *attr, const char *buf,
2275 size_t count)
2276{
2277 struct nct6775_data *data = dev_get_drvdata(dev);
2278 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2279 int nr = sattr->nr;
2280 int index = sattr->index;
2281 int err;
2282 long val;
2283
2284 err = kstrtol(buf, 10, &val);
2285 if (err < 0)
2286 return err;
2287
2288 mutex_lock(&data->update_lock);
2289 data->temp[index][nr] = LM75_TEMP_TO_REG(val);
2290 nct6775_write_temp(data, data->reg_temp[index][nr],
2291 data->temp[index][nr]);
2292 mutex_unlock(&data->update_lock);
2293 return count;
2294}
2295
2296static ssize_t
2297show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf)
2298{
2299 struct nct6775_data *data = nct6775_update_device(dev);
2300 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2301
2302 return sprintf(buf, "%d\n", data->temp_offset[sattr->index] * 1000);
2303}
2304
2305static ssize_t
2306store_temp_offset(struct device *dev, struct device_attribute *attr,
2307 const char *buf, size_t count)
2308{
2309 struct nct6775_data *data = dev_get_drvdata(dev);
2310 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2311 int nr = sattr->index;
2312 long val;
2313 int err;
2314
2315 err = kstrtol(buf, 10, &val);
2316 if (err < 0)
2317 return err;
2318
2319 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
2320
2321 mutex_lock(&data->update_lock);
2322 data->temp_offset[nr] = val;
2323 nct6775_write_value(data, data->REG_TEMP_OFFSET[nr], val);
2324 mutex_unlock(&data->update_lock);
2325
2326 return count;
2327}
2328
2329static ssize_t
2330show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
2331{
2332 struct nct6775_data *data = nct6775_update_device(dev);
2333 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2334 int nr = sattr->index;
2335
2336 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
2337}
2338
2339static ssize_t
2340store_temp_type(struct device *dev, struct device_attribute *attr,
2341 const char *buf, size_t count)
2342{
2343 struct nct6775_data *data = nct6775_update_device(dev);
2344 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2345 int nr = sattr->index;
2346 unsigned long val;
2347 int err;
2348 u8 vbat, diode, vbit, dbit;
2349
2350 err = kstrtoul(buf, 10, &val);
2351 if (err < 0)
2352 return err;
2353
2354 if (val != 1 && val != 3 && val != 4)
2355 return -EINVAL;
2356
2357 mutex_lock(&data->update_lock);
2358
2359 data->temp_type[nr] = val;
2360 vbit = 0x02 << nr;
2361 dbit = data->DIODE_MASK << nr;
2362 vbat = nct6775_read_value(data, data->REG_VBAT) & ~vbit;
2363 diode = nct6775_read_value(data, data->REG_DIODE) & ~dbit;
2364 switch (val) {
2365 case 1: /* CPU diode (diode, current mode) */
2366 vbat |= vbit;
2367 diode |= dbit;
2368 break;
2369 case 3: /* diode, voltage mode */
2370 vbat |= dbit;
2371 break;
2372 case 4: /* thermistor */
2373 break;
2374 }
2375 nct6775_write_value(data, data->REG_VBAT, vbat);
2376 nct6775_write_value(data, data->REG_DIODE, diode);
2377
2378 mutex_unlock(&data->update_lock);
2379 return count;
2380}
2381
2382static umode_t nct6775_temp_is_visible(struct kobject *kobj,
2383 struct attribute *attr, int index)
2384{
2385 struct device *dev = container_of(kobj, struct device, kobj);
2386 struct nct6775_data *data = dev_get_drvdata(dev);
2387 int temp = index / 10; /* temp index */
2388 int nr = index % 10; /* attribute index */
2389
2390 if (!(data->have_temp & BIT(temp)))
2391 return 0;
2392
2393 if (nr == 1 && !data->temp_label)
2394 return 0;
2395
2396 if (nr == 2 && find_temp_source(data, temp, data->num_temp_alarms) < 0)
2397 return 0; /* alarm */
2398
2399 if (nr == 3 && find_temp_source(data, temp, data->num_temp_beeps) < 0)
2400 return 0; /* beep */
2401
2402 if (nr == 4 && !data->reg_temp[1][temp]) /* max */
2403 return 0;
2404
2405 if (nr == 5 && !data->reg_temp[2][temp]) /* max_hyst */
2406 return 0;
2407
2408 if (nr == 6 && !data->reg_temp[3][temp]) /* crit */
2409 return 0;
2410
2411 if (nr == 7 && !data->reg_temp[4][temp]) /* lcrit */
2412 return 0;
2413
2414 /* offset and type only apply to fixed sensors */
2415 if (nr > 7 && !(data->have_temp_fixed & BIT(temp)))
2416 return 0;
2417
2418 return attr->mode;
2419}
2420
2421SENSOR_TEMPLATE_2(temp_input, "temp%d_input", S_IRUGO, show_temp, NULL, 0, 0);
2422SENSOR_TEMPLATE(temp_label, "temp%d_label", S_IRUGO, show_temp_label, NULL, 0);
2423SENSOR_TEMPLATE_2(temp_max, "temp%d_max", S_IRUGO | S_IWUSR, show_temp,
2424 store_temp, 0, 1);
2425SENSOR_TEMPLATE_2(temp_max_hyst, "temp%d_max_hyst", S_IRUGO | S_IWUSR,
2426 show_temp, store_temp, 0, 2);
2427SENSOR_TEMPLATE_2(temp_crit, "temp%d_crit", S_IRUGO | S_IWUSR, show_temp,
2428 store_temp, 0, 3);
2429SENSOR_TEMPLATE_2(temp_lcrit, "temp%d_lcrit", S_IRUGO | S_IWUSR, show_temp,
2430 store_temp, 0, 4);
2431SENSOR_TEMPLATE(temp_offset, "temp%d_offset", S_IRUGO | S_IWUSR,
2432 show_temp_offset, store_temp_offset, 0);
2433SENSOR_TEMPLATE(temp_type, "temp%d_type", S_IRUGO | S_IWUSR, show_temp_type,
2434 store_temp_type, 0);
2435SENSOR_TEMPLATE(temp_alarm, "temp%d_alarm", S_IRUGO, show_temp_alarm, NULL, 0);
2436SENSOR_TEMPLATE(temp_beep, "temp%d_beep", S_IRUGO | S_IWUSR, show_temp_beep,
2437 store_temp_beep, 0);
2438
2439/*
2440 * nct6775_temp_is_visible uses the index into the following array
2441 * to determine if attributes should be created or not.
2442 * Any change in order or content must be matched.
2443 */
2444static struct sensor_device_template *nct6775_attributes_temp_template[] = {
2445 &sensor_dev_template_temp_input,
2446 &sensor_dev_template_temp_label,
2447 &sensor_dev_template_temp_alarm, /* 2 */
2448 &sensor_dev_template_temp_beep, /* 3 */
2449 &sensor_dev_template_temp_max, /* 4 */
2450 &sensor_dev_template_temp_max_hyst, /* 5 */
2451 &sensor_dev_template_temp_crit, /* 6 */
2452 &sensor_dev_template_temp_lcrit, /* 7 */
2453 &sensor_dev_template_temp_offset, /* 8 */
2454 &sensor_dev_template_temp_type, /* 9 */
2455 NULL
2456};
2457
2458static const struct sensor_template_group nct6775_temp_template_group = {
2459 .templates = nct6775_attributes_temp_template,
2460 .is_visible = nct6775_temp_is_visible,
2461 .base = 1,
2462};
2463
2464static ssize_t
2465show_pwm_mode(struct device *dev, struct device_attribute *attr, char *buf)
2466{
2467 struct nct6775_data *data = nct6775_update_device(dev);
2468 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2469
2470 return sprintf(buf, "%d\n", data->pwm_mode[sattr->index]);
2471}
2472
2473static ssize_t
2474store_pwm_mode(struct device *dev, struct device_attribute *attr,
2475 const char *buf, size_t count)
2476{
2477 struct nct6775_data *data = dev_get_drvdata(dev);
2478 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2479 int nr = sattr->index;
2480 unsigned long val;
2481 int err;
2482 u8 reg;
2483
2484 err = kstrtoul(buf, 10, &val);
2485 if (err < 0)
2486 return err;
2487
2488 if (val > 1)
2489 return -EINVAL;
2490
2491 /* Setting DC mode (0) is not supported for all chips/channels */
2492 if (data->REG_PWM_MODE[nr] == 0) {
2493 if (!val)
2494 return -EINVAL;
2495 return count;
2496 }
2497
2498 mutex_lock(&data->update_lock);
2499 data->pwm_mode[nr] = val;
2500 reg = nct6775_read_value(data, data->REG_PWM_MODE[nr]);
2501 reg &= ~data->PWM_MODE_MASK[nr];
2502 if (!val)
2503 reg |= data->PWM_MODE_MASK[nr];
2504 nct6775_write_value(data, data->REG_PWM_MODE[nr], reg);
2505 mutex_unlock(&data->update_lock);
2506 return count;
2507}
2508
2509static ssize_t
2510show_pwm(struct device *dev, struct device_attribute *attr, char *buf)
2511{
2512 struct nct6775_data *data = nct6775_update_device(dev);
2513 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2514 int nr = sattr->nr;
2515 int index = sattr->index;
2516 int pwm;
2517
2518 /*
2519 * For automatic fan control modes, show current pwm readings.
2520 * Otherwise, show the configured value.
2521 */
2522 if (index == 0 && data->pwm_enable[nr] > manual)
2523 pwm = nct6775_read_value(data, data->REG_PWM_READ[nr]);
2524 else
2525 pwm = data->pwm[index][nr];
2526
2527 return sprintf(buf, "%d\n", pwm);
2528}
2529
2530static ssize_t
2531store_pwm(struct device *dev, struct device_attribute *attr, const char *buf,
2532 size_t count)
2533{
2534 struct nct6775_data *data = dev_get_drvdata(dev);
2535 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2536 int nr = sattr->nr;
2537 int index = sattr->index;
2538 unsigned long val;
2539 int minval[7] = { 0, 1, 1, data->pwm[2][nr], 0, 0, 0 };
2540 int maxval[7]
2541 = { 255, 255, data->pwm[3][nr] ? : 255, 255, 255, 255, 255 };
2542 int err;
2543 u8 reg;
2544
2545 err = kstrtoul(buf, 10, &val);
2546 if (err < 0)
2547 return err;
2548 val = clamp_val(val, minval[index], maxval[index]);
2549
2550 mutex_lock(&data->update_lock);
2551 data->pwm[index][nr] = val;
2552 nct6775_write_value(data, data->REG_PWM[index][nr], val);
2553 if (index == 2) { /* floor: disable if val == 0 */
2554 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2555 reg &= 0x7f;
2556 if (val)
2557 reg |= 0x80;
2558 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2559 }
2560 mutex_unlock(&data->update_lock);
2561 return count;
2562}
2563
2564/* Returns 0 if OK, -EINVAL otherwise */
2565static int check_trip_points(struct nct6775_data *data, int nr)
2566{
2567 int i;
2568
2569 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2570 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
2571 return -EINVAL;
2572 }
2573 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2574 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
2575 return -EINVAL;
2576 }
2577 /* validate critical temperature and pwm if enabled (pwm > 0) */
2578 if (data->auto_pwm[nr][data->auto_pwm_num]) {
2579 if (data->auto_temp[nr][data->auto_pwm_num - 1] >
2580 data->auto_temp[nr][data->auto_pwm_num] ||
2581 data->auto_pwm[nr][data->auto_pwm_num - 1] >
2582 data->auto_pwm[nr][data->auto_pwm_num])
2583 return -EINVAL;
2584 }
2585 return 0;
2586}
2587
2588static void pwm_update_registers(struct nct6775_data *data, int nr)
2589{
2590 u8 reg;
2591
2592 switch (data->pwm_enable[nr]) {
2593 case off:
2594 case manual:
2595 break;
2596 case speed_cruise:
2597 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2598 reg = (reg & ~data->tolerance_mask) |
2599 (data->target_speed_tolerance[nr] & data->tolerance_mask);
2600 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2601 nct6775_write_value(data, data->REG_TARGET[nr],
2602 data->target_speed[nr] & 0xff);
2603 if (data->REG_TOLERANCE_H) {
2604 reg = (data->target_speed[nr] >> 8) & 0x0f;
2605 reg |= (data->target_speed_tolerance[nr] & 0x38) << 1;
2606 nct6775_write_value(data,
2607 data->REG_TOLERANCE_H[nr],
2608 reg);
2609 }
2610 break;
2611 case thermal_cruise:
2612 nct6775_write_value(data, data->REG_TARGET[nr],
2613 data->target_temp[nr]);
2614 /* fall through */
2615 default:
2616 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2617 reg = (reg & ~data->tolerance_mask) |
2618 data->temp_tolerance[0][nr];
2619 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2620 break;
2621 }
2622}
2623
2624static ssize_t
2625show_pwm_enable(struct device *dev, struct device_attribute *attr, char *buf)
2626{
2627 struct nct6775_data *data = nct6775_update_device(dev);
2628 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2629
2630 return sprintf(buf, "%d\n", data->pwm_enable[sattr->index]);
2631}
2632
2633static ssize_t
2634store_pwm_enable(struct device *dev, struct device_attribute *attr,
2635 const char *buf, size_t count)
2636{
2637 struct nct6775_data *data = dev_get_drvdata(dev);
2638 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2639 int nr = sattr->index;
2640 unsigned long val;
2641 int err;
2642 u16 reg;
2643
2644 err = kstrtoul(buf, 10, &val);
2645 if (err < 0)
2646 return err;
2647
2648 if (val > sf4)
2649 return -EINVAL;
2650
2651 if (val == sf3 && data->kind != nct6775)
2652 return -EINVAL;
2653
2654 if (val == sf4 && check_trip_points(data, nr)) {
2655 dev_err(dev, "Inconsistent trip points, not switching to SmartFan IV mode\n");
2656 dev_err(dev, "Adjust trip points and try again\n");
2657 return -EINVAL;
2658 }
2659
2660 mutex_lock(&data->update_lock);
2661 data->pwm_enable[nr] = val;
2662 if (val == off) {
2663 /*
2664 * turn off pwm control: select manual mode, set pwm to maximum
2665 */
2666 data->pwm[0][nr] = 255;
2667 nct6775_write_value(data, data->REG_PWM[0][nr], 255);
2668 }
2669 pwm_update_registers(data, nr);
2670 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2671 reg &= 0x0f;
2672 reg |= pwm_enable_to_reg(val) << 4;
2673 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2674 mutex_unlock(&data->update_lock);
2675 return count;
2676}
2677
2678static ssize_t
2679show_pwm_temp_sel_common(struct nct6775_data *data, char *buf, int src)
2680{
2681 int i, sel = 0;
2682
2683 for (i = 0; i < NUM_TEMP; i++) {
2684 if (!(data->have_temp & BIT(i)))
2685 continue;
2686 if (src == data->temp_src[i]) {
2687 sel = i + 1;
2688 break;
2689 }
2690 }
2691
2692 return sprintf(buf, "%d\n", sel);
2693}
2694
2695static ssize_t
2696show_pwm_temp_sel(struct device *dev, struct device_attribute *attr, char *buf)
2697{
2698 struct nct6775_data *data = nct6775_update_device(dev);
2699 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2700 int index = sattr->index;
2701
2702 return show_pwm_temp_sel_common(data, buf, data->pwm_temp_sel[index]);
2703}
2704
2705static ssize_t
2706store_pwm_temp_sel(struct device *dev, struct device_attribute *attr,
2707 const char *buf, size_t count)
2708{
2709 struct nct6775_data *data = nct6775_update_device(dev);
2710 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2711 int nr = sattr->index;
2712 unsigned long val;
2713 int err, reg, src;
2714
2715 err = kstrtoul(buf, 10, &val);
2716 if (err < 0)
2717 return err;
2718 if (val == 0 || val > NUM_TEMP)
2719 return -EINVAL;
2720 if (!(data->have_temp & BIT(val - 1)) || !data->temp_src[val - 1])
2721 return -EINVAL;
2722
2723 mutex_lock(&data->update_lock);
2724 src = data->temp_src[val - 1];
2725 data->pwm_temp_sel[nr] = src;
2726 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2727 reg &= 0xe0;
2728 reg |= src;
2729 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2730 mutex_unlock(&data->update_lock);
2731
2732 return count;
2733}
2734
2735static ssize_t
2736show_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2737 char *buf)
2738{
2739 struct nct6775_data *data = nct6775_update_device(dev);
2740 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2741 int index = sattr->index;
2742
2743 return show_pwm_temp_sel_common(data, buf,
2744 data->pwm_weight_temp_sel[index]);
2745}
2746
2747static ssize_t
2748store_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2749 const char *buf, size_t count)
2750{
2751 struct nct6775_data *data = nct6775_update_device(dev);
2752 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2753 int nr = sattr->index;
2754 unsigned long val;
2755 int err, reg, src;
2756
2757 err = kstrtoul(buf, 10, &val);
2758 if (err < 0)
2759 return err;
2760 if (val > NUM_TEMP)
2761 return -EINVAL;
2762 val = array_index_nospec(val, NUM_TEMP + 1);
2763 if (val && (!(data->have_temp & BIT(val - 1)) ||
2764 !data->temp_src[val - 1]))
2765 return -EINVAL;
2766
2767 mutex_lock(&data->update_lock);
2768 if (val) {
2769 src = data->temp_src[val - 1];
2770 data->pwm_weight_temp_sel[nr] = src;
2771 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2772 reg &= 0xe0;
2773 reg |= (src | 0x80);
2774 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2775 } else {
2776 data->pwm_weight_temp_sel[nr] = 0;
2777 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2778 reg &= 0x7f;
2779 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2780 }
2781 mutex_unlock(&data->update_lock);
2782
2783 return count;
2784}
2785
2786static ssize_t
2787show_target_temp(struct device *dev, struct device_attribute *attr, char *buf)
2788{
2789 struct nct6775_data *data = nct6775_update_device(dev);
2790 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2791
2792 return sprintf(buf, "%d\n", data->target_temp[sattr->index] * 1000);
2793}
2794
2795static ssize_t
2796store_target_temp(struct device *dev, struct device_attribute *attr,
2797 const char *buf, size_t count)
2798{
2799 struct nct6775_data *data = dev_get_drvdata(dev);
2800 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2801 int nr = sattr->index;
2802 unsigned long val;
2803 int err;
2804
2805 err = kstrtoul(buf, 10, &val);
2806 if (err < 0)
2807 return err;
2808
2809 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0,
2810 data->target_temp_mask);
2811
2812 mutex_lock(&data->update_lock);
2813 data->target_temp[nr] = val;
2814 pwm_update_registers(data, nr);
2815 mutex_unlock(&data->update_lock);
2816 return count;
2817}
2818
2819static ssize_t
2820show_target_speed(struct device *dev, struct device_attribute *attr, char *buf)
2821{
2822 struct nct6775_data *data = nct6775_update_device(dev);
2823 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2824 int nr = sattr->index;
2825
2826 return sprintf(buf, "%d\n",
2827 fan_from_reg16(data->target_speed[nr],
2828 data->fan_div[nr]));
2829}
2830
2831static ssize_t
2832store_target_speed(struct device *dev, struct device_attribute *attr,
2833 const char *buf, size_t count)
2834{
2835 struct nct6775_data *data = dev_get_drvdata(dev);
2836 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2837 int nr = sattr->index;
2838 unsigned long val;
2839 int err;
2840 u16 speed;
2841
2842 err = kstrtoul(buf, 10, &val);
2843 if (err < 0)
2844 return err;
2845
2846 val = clamp_val(val, 0, 1350000U);
2847 speed = fan_to_reg(val, data->fan_div[nr]);
2848
2849 mutex_lock(&data->update_lock);
2850 data->target_speed[nr] = speed;
2851 pwm_update_registers(data, nr);
2852 mutex_unlock(&data->update_lock);
2853 return count;
2854}
2855
2856static ssize_t
2857show_temp_tolerance(struct device *dev, struct device_attribute *attr,
2858 char *buf)
2859{
2860 struct nct6775_data *data = nct6775_update_device(dev);
2861 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2862 int nr = sattr->nr;
2863 int index = sattr->index;
2864
2865 return sprintf(buf, "%d\n", data->temp_tolerance[index][nr] * 1000);
2866}
2867
2868static ssize_t
2869store_temp_tolerance(struct device *dev, struct device_attribute *attr,
2870 const char *buf, size_t count)
2871{
2872 struct nct6775_data *data = dev_get_drvdata(dev);
2873 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2874 int nr = sattr->nr;
2875 int index = sattr->index;
2876 unsigned long val;
2877 int err;
2878
2879 err = kstrtoul(buf, 10, &val);
2880 if (err < 0)
2881 return err;
2882
2883 /* Limit tolerance as needed */
2884 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, data->tolerance_mask);
2885
2886 mutex_lock(&data->update_lock);
2887 data->temp_tolerance[index][nr] = val;
2888 if (index)
2889 pwm_update_registers(data, nr);
2890 else
2891 nct6775_write_value(data,
2892 data->REG_CRITICAL_TEMP_TOLERANCE[nr],
2893 val);
2894 mutex_unlock(&data->update_lock);
2895 return count;
2896}
2897
2898/*
2899 * Fan speed tolerance is a tricky beast, since the associated register is
2900 * a tick counter, but the value is reported and configured as rpm.
2901 * Compute resulting low and high rpm values and report the difference.
2902 * A fan speed tolerance only makes sense if a fan target speed has been
2903 * configured, so only display values other than 0 if that is the case.
2904 */
2905static ssize_t
2906show_speed_tolerance(struct device *dev, struct device_attribute *attr,
2907 char *buf)
2908{
2909 struct nct6775_data *data = nct6775_update_device(dev);
2910 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2911 int nr = sattr->index;
2912 int target = data->target_speed[nr];
2913 int tolerance = 0;
2914
2915 if (target) {
2916 int low = target - data->target_speed_tolerance[nr];
2917 int high = target + data->target_speed_tolerance[nr];
2918
2919 if (low <= 0)
2920 low = 1;
2921 if (high > 0xffff)
2922 high = 0xffff;
2923 if (high < low)
2924 high = low;
2925
2926 tolerance = (fan_from_reg16(low, data->fan_div[nr])
2927 - fan_from_reg16(high, data->fan_div[nr])) / 2;
2928 }
2929
2930 return sprintf(buf, "%d\n", tolerance);
2931}
2932
2933static ssize_t
2934store_speed_tolerance(struct device *dev, struct device_attribute *attr,
2935 const char *buf, size_t count)
2936{
2937 struct nct6775_data *data = dev_get_drvdata(dev);
2938 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2939 int nr = sattr->index;
2940 unsigned long val;
2941 int err;
2942 int low, high;
2943
2944 err = kstrtoul(buf, 10, &val);
2945 if (err < 0)
2946 return err;
2947
2948 high = fan_from_reg16(data->target_speed[nr],
2949 data->fan_div[nr]) + val;
2950 low = fan_from_reg16(data->target_speed[nr],
2951 data->fan_div[nr]) - val;
2952 if (low <= 0)
2953 low = 1;
2954 if (high < low)
2955 high = low;
2956
2957 val = (fan_to_reg(low, data->fan_div[nr]) -
2958 fan_to_reg(high, data->fan_div[nr])) / 2;
2959
2960 /* Limit tolerance as needed */
2961 val = clamp_val(val, 0, data->speed_tolerance_limit);
2962
2963 mutex_lock(&data->update_lock);
2964 data->target_speed_tolerance[nr] = val;
2965 pwm_update_registers(data, nr);
2966 mutex_unlock(&data->update_lock);
2967 return count;
2968}
2969
2970SENSOR_TEMPLATE_2(pwm, "pwm%d", S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 0);
2971SENSOR_TEMPLATE(pwm_mode, "pwm%d_mode", S_IWUSR | S_IRUGO, show_pwm_mode,
2972 store_pwm_mode, 0);
2973SENSOR_TEMPLATE(pwm_enable, "pwm%d_enable", S_IWUSR | S_IRUGO, show_pwm_enable,
2974 store_pwm_enable, 0);
2975SENSOR_TEMPLATE(pwm_temp_sel, "pwm%d_temp_sel", S_IWUSR | S_IRUGO,
2976 show_pwm_temp_sel, store_pwm_temp_sel, 0);
2977SENSOR_TEMPLATE(pwm_target_temp, "pwm%d_target_temp", S_IWUSR | S_IRUGO,
2978 show_target_temp, store_target_temp, 0);
2979SENSOR_TEMPLATE(fan_target, "fan%d_target", S_IWUSR | S_IRUGO,
2980 show_target_speed, store_target_speed, 0);
2981SENSOR_TEMPLATE(fan_tolerance, "fan%d_tolerance", S_IWUSR | S_IRUGO,
2982 show_speed_tolerance, store_speed_tolerance, 0);
2983
2984/* Smart Fan registers */
2985
2986static ssize_t
2987show_weight_temp(struct device *dev, struct device_attribute *attr, char *buf)
2988{
2989 struct nct6775_data *data = nct6775_update_device(dev);
2990 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2991 int nr = sattr->nr;
2992 int index = sattr->index;
2993
2994 return sprintf(buf, "%d\n", data->weight_temp[index][nr] * 1000);
2995}
2996
2997static ssize_t
2998store_weight_temp(struct device *dev, struct device_attribute *attr,
2999 const char *buf, size_t count)
3000{
3001 struct nct6775_data *data = dev_get_drvdata(dev);
3002 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3003 int nr = sattr->nr;
3004 int index = sattr->index;
3005 unsigned long val;
3006 int err;
3007
3008 err = kstrtoul(buf, 10, &val);
3009 if (err < 0)
3010 return err;
3011
3012 val =