1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * This driver implements I2C master functionality using the LSI API2C |
4 | * controller. |
5 | * |
6 | * NOTE: The controller has a limitation in that it can only do transfers of |
7 | * maximum 255 bytes at a time. If a larger transfer is attempted, error code |
8 | * (-EINVAL) is returned. |
9 | */ |
10 | #include <linux/clk.h> |
11 | #include <linux/clkdev.h> |
12 | #include <linux/delay.h> |
13 | #include <linux/err.h> |
14 | #include <linux/i2c.h> |
15 | #include <linux/init.h> |
16 | #include <linux/interrupt.h> |
17 | #include <linux/module.h> |
18 | #include <linux/io.h> |
19 | #include <linux/kernel.h> |
20 | #include <linux/platform_device.h> |
21 | |
22 | #define SCL_WAIT_TIMEOUT_NS 25000000 |
23 | #define I2C_XFER_TIMEOUT (msecs_to_jiffies(250)) |
24 | #define I2C_STOP_TIMEOUT (msecs_to_jiffies(100)) |
25 | #define FIFO_SIZE 8 |
26 | #define SEQ_LEN 2 |
27 | |
28 | #define GLOBAL_CONTROL 0x00 |
29 | #define GLOBAL_MST_EN BIT(0) |
30 | #define GLOBAL_SLV_EN BIT(1) |
31 | #define GLOBAL_IBML_EN BIT(2) |
32 | #define INTERRUPT_STATUS 0x04 |
33 | #define INTERRUPT_ENABLE 0x08 |
34 | #define INT_SLV BIT(1) |
35 | #define INT_MST BIT(0) |
36 | #define WAIT_TIMER_CONTROL 0x0c |
37 | #define WT_EN BIT(15) |
38 | #define WT_VALUE(_x) ((_x) & 0x7fff) |
39 | #define IBML_TIMEOUT 0x10 |
40 | #define IBML_LOW_MEXT 0x14 |
41 | #define IBML_LOW_SEXT 0x18 |
42 | #define TIMER_CLOCK_DIV 0x1c |
43 | #define I2C_BUS_MONITOR 0x20 |
44 | #define BM_SDAC BIT(3) |
45 | #define BM_SCLC BIT(2) |
46 | #define BM_SDAS BIT(1) |
47 | #define BM_SCLS BIT(0) |
48 | #define SOFT_RESET 0x24 |
49 | #define MST_COMMAND 0x28 |
50 | #define CMD_BUSY (1<<3) |
51 | #define CMD_MANUAL (0x00 | CMD_BUSY) |
52 | #define CMD_AUTO (0x01 | CMD_BUSY) |
53 | #define CMD_SEQUENCE (0x02 | CMD_BUSY) |
54 | #define MST_RX_XFER 0x2c |
55 | #define MST_TX_XFER 0x30 |
56 | #define MST_ADDR_1 0x34 |
57 | #define MST_ADDR_2 0x38 |
58 | #define MST_DATA 0x3c |
59 | #define MST_TX_FIFO 0x40 |
60 | #define MST_RX_FIFO 0x44 |
61 | #define MST_INT_ENABLE 0x48 |
62 | #define MST_INT_STATUS 0x4c |
63 | #define MST_STATUS_RFL (1 << 13) /* RX FIFO serivce */ |
64 | #define MST_STATUS_TFL (1 << 12) /* TX FIFO service */ |
65 | #define MST_STATUS_SNS (1 << 11) /* Manual mode done */ |
66 | #define MST_STATUS_SS (1 << 10) /* Automatic mode done */ |
67 | #define MST_STATUS_SCC (1 << 9) /* Stop complete */ |
68 | #define MST_STATUS_IP (1 << 8) /* Invalid parameter */ |
69 | #define MST_STATUS_TSS (1 << 7) /* Timeout */ |
70 | #define MST_STATUS_AL (1 << 6) /* Arbitration lost */ |
71 | #define MST_STATUS_ND (1 << 5) /* NAK on data phase */ |
72 | #define MST_STATUS_NA (1 << 4) /* NAK on address phase */ |
73 | #define MST_STATUS_NAK (MST_STATUS_NA | \ |
74 | MST_STATUS_ND) |
75 | #define MST_STATUS_ERR (MST_STATUS_NAK | \ |
76 | MST_STATUS_AL | \ |
77 | MST_STATUS_IP) |
78 | #define MST_TX_BYTES_XFRD 0x50 |
79 | #define MST_RX_BYTES_XFRD 0x54 |
80 | #define SLV_ADDR_DEC_CTL 0x58 |
81 | #define SLV_ADDR_DEC_GCE BIT(0) /* ACK to General Call Address from own master (loopback) */ |
82 | #define SLV_ADDR_DEC_OGCE BIT(1) /* ACK to General Call Address from external masters */ |
83 | #define SLV_ADDR_DEC_SA1E BIT(2) /* ACK to addr_1 enabled */ |
84 | #define SLV_ADDR_DEC_SA1M BIT(3) /* 10-bit addressing for addr_1 enabled */ |
85 | #define SLV_ADDR_DEC_SA2E BIT(4) /* ACK to addr_2 enabled */ |
86 | #define SLV_ADDR_DEC_SA2M BIT(5) /* 10-bit addressing for addr_2 enabled */ |
87 | #define SLV_ADDR_1 0x5c |
88 | #define SLV_ADDR_2 0x60 |
89 | #define SLV_RX_CTL 0x64 |
90 | #define SLV_RX_ACSA1 BIT(0) /* Generate ACK for writes to addr_1 */ |
91 | #define SLV_RX_ACSA2 BIT(1) /* Generate ACK for writes to addr_2 */ |
92 | #define SLV_RX_ACGCA BIT(2) /* ACK data phase transfers to General Call Address */ |
93 | #define SLV_DATA 0x68 |
94 | #define SLV_RX_FIFO 0x6c |
95 | #define SLV_FIFO_DV1 BIT(0) /* Data Valid for addr_1 */ |
96 | #define SLV_FIFO_DV2 BIT(1) /* Data Valid for addr_2 */ |
97 | #define SLV_FIFO_AS BIT(2) /* (N)ACK Sent */ |
98 | #define SLV_FIFO_TNAK BIT(3) /* Timeout NACK */ |
99 | #define SLV_FIFO_STRC BIT(4) /* First byte after start condition received */ |
100 | #define SLV_FIFO_RSC BIT(5) /* Repeated Start Condition */ |
101 | #define SLV_FIFO_STPC BIT(6) /* Stop Condition */ |
102 | #define SLV_FIFO_DV (SLV_FIFO_DV1 | SLV_FIFO_DV2) |
103 | #define SLV_INT_ENABLE 0x70 |
104 | #define SLV_INT_STATUS 0x74 |
105 | #define SLV_STATUS_RFH BIT(0) /* FIFO service */ |
106 | #define SLV_STATUS_WTC BIT(1) /* Write transfer complete */ |
107 | #define SLV_STATUS_SRS1 BIT(2) /* Slave read from addr 1 */ |
108 | #define SLV_STATUS_SRRS1 BIT(3) /* Repeated start from addr 1 */ |
109 | #define SLV_STATUS_SRND1 BIT(4) /* Read request not following start condition */ |
110 | #define SLV_STATUS_SRC1 BIT(5) /* Read canceled */ |
111 | #define SLV_STATUS_SRAT1 BIT(6) /* Slave Read timed out */ |
112 | #define SLV_STATUS_SRDRE1 BIT(7) /* Data written after timed out */ |
113 | #define SLV_READ_DUMMY 0x78 |
114 | #define SCL_HIGH_PERIOD 0x80 |
115 | #define SCL_LOW_PERIOD 0x84 |
116 | #define SPIKE_FLTR_LEN 0x88 |
117 | #define SDA_SETUP_TIME 0x8c |
118 | #define SDA_HOLD_TIME 0x90 |
119 | |
120 | /** |
121 | * struct axxia_i2c_dev - I2C device context |
122 | * @base: pointer to register struct |
123 | * @msg: pointer to current message |
124 | * @msg_r: pointer to current read message (sequence transfer) |
125 | * @msg_xfrd: number of bytes transferred in tx_fifo |
126 | * @msg_xfrd_r: number of bytes transferred in rx_fifo |
127 | * @msg_err: error code for completed message |
128 | * @msg_complete: xfer completion object |
129 | * @dev: device reference |
130 | * @adapter: core i2c abstraction |
131 | * @i2c_clk: clock reference for i2c input clock |
132 | * @bus_clk_rate: current i2c bus clock rate |
133 | * @last: a flag indicating is this is last message in transfer |
134 | * @slave: associated &i2c_client |
135 | * @irq: platform device IRQ number |
136 | */ |
137 | struct axxia_i2c_dev { |
138 | void __iomem *base; |
139 | struct i2c_msg *msg; |
140 | struct i2c_msg *msg_r; |
141 | size_t msg_xfrd; |
142 | size_t msg_xfrd_r; |
143 | int msg_err; |
144 | struct completion msg_complete; |
145 | struct device *dev; |
146 | struct i2c_adapter adapter; |
147 | struct clk *i2c_clk; |
148 | u32 bus_clk_rate; |
149 | bool last; |
150 | struct i2c_client *slave; |
151 | int irq; |
152 | }; |
153 | |
154 | static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask) |
155 | { |
156 | u32 int_en; |
157 | |
158 | int_en = readl(addr: idev->base + MST_INT_ENABLE); |
159 | writel(val: int_en & ~mask, addr: idev->base + MST_INT_ENABLE); |
160 | } |
161 | |
162 | static void i2c_int_enable(struct axxia_i2c_dev *idev, u32 mask) |
163 | { |
164 | u32 int_en; |
165 | |
166 | int_en = readl(addr: idev->base + MST_INT_ENABLE); |
167 | writel(val: int_en | mask, addr: idev->base + MST_INT_ENABLE); |
168 | } |
169 | |
170 | /* |
171 | * ns_to_clk - Convert time (ns) to clock cycles for the given clock frequency. |
172 | */ |
173 | static u32 ns_to_clk(u64 ns, u32 clk_mhz) |
174 | { |
175 | return div_u64(dividend: ns * clk_mhz, divisor: 1000); |
176 | } |
177 | |
178 | static int axxia_i2c_init(struct axxia_i2c_dev *idev) |
179 | { |
180 | u32 divisor = clk_get_rate(clk: idev->i2c_clk) / idev->bus_clk_rate; |
181 | u32 clk_mhz = clk_get_rate(clk: idev->i2c_clk) / 1000000; |
182 | u32 t_setup; |
183 | u32 t_high, t_low; |
184 | u32 tmo_clk; |
185 | u32 prescale; |
186 | unsigned long timeout; |
187 | |
188 | dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n" , |
189 | idev->bus_clk_rate, clk_mhz, divisor); |
190 | |
191 | /* Reset controller */ |
192 | writel(val: 0x01, addr: idev->base + SOFT_RESET); |
193 | timeout = jiffies + msecs_to_jiffies(m: 100); |
194 | while (readl(addr: idev->base + SOFT_RESET) & 1) { |
195 | if (time_after(jiffies, timeout)) { |
196 | dev_warn(idev->dev, "Soft reset failed\n" ); |
197 | break; |
198 | } |
199 | } |
200 | |
201 | /* Enable Master Mode */ |
202 | writel(val: 0x1, addr: idev->base + GLOBAL_CONTROL); |
203 | |
204 | if (idev->bus_clk_rate <= I2C_MAX_STANDARD_MODE_FREQ) { |
205 | /* Standard mode SCL 50/50, tSU:DAT = 250 ns */ |
206 | t_high = divisor * 1 / 2; |
207 | t_low = divisor * 1 / 2; |
208 | t_setup = ns_to_clk(ns: 250, clk_mhz); |
209 | } else { |
210 | /* Fast mode SCL 33/66, tSU:DAT = 100 ns */ |
211 | t_high = divisor * 1 / 3; |
212 | t_low = divisor * 2 / 3; |
213 | t_setup = ns_to_clk(ns: 100, clk_mhz); |
214 | } |
215 | |
216 | /* SCL High Time */ |
217 | writel(val: t_high, addr: idev->base + SCL_HIGH_PERIOD); |
218 | /* SCL Low Time */ |
219 | writel(val: t_low, addr: idev->base + SCL_LOW_PERIOD); |
220 | /* SDA Setup Time */ |
221 | writel(val: t_setup, addr: idev->base + SDA_SETUP_TIME); |
222 | /* SDA Hold Time, 300ns */ |
223 | writel(val: ns_to_clk(ns: 300, clk_mhz), addr: idev->base + SDA_HOLD_TIME); |
224 | /* Filter <50ns spikes */ |
225 | writel(val: ns_to_clk(ns: 50, clk_mhz), addr: idev->base + SPIKE_FLTR_LEN); |
226 | |
227 | /* Configure Time-Out Registers */ |
228 | tmo_clk = ns_to_clk(SCL_WAIT_TIMEOUT_NS, clk_mhz); |
229 | |
230 | /* Find prescaler value that makes tmo_clk fit in 15-bits counter. */ |
231 | for (prescale = 0; prescale < 15; ++prescale) { |
232 | if (tmo_clk <= 0x7fff) |
233 | break; |
234 | tmo_clk >>= 1; |
235 | } |
236 | if (tmo_clk > 0x7fff) |
237 | tmo_clk = 0x7fff; |
238 | |
239 | /* Prescale divider (log2) */ |
240 | writel(val: prescale, addr: idev->base + TIMER_CLOCK_DIV); |
241 | /* Timeout in divided clocks */ |
242 | writel(WT_EN | WT_VALUE(tmo_clk), addr: idev->base + WAIT_TIMER_CONTROL); |
243 | |
244 | /* Mask all master interrupt bits */ |
245 | i2c_int_disable(idev, mask: ~0); |
246 | |
247 | /* Interrupt enable */ |
248 | writel(val: 0x01, addr: idev->base + INTERRUPT_ENABLE); |
249 | |
250 | return 0; |
251 | } |
252 | |
253 | static int i2c_m_rd(const struct i2c_msg *msg) |
254 | { |
255 | return (msg->flags & I2C_M_RD) != 0; |
256 | } |
257 | |
258 | static int i2c_m_ten(const struct i2c_msg *msg) |
259 | { |
260 | return (msg->flags & I2C_M_TEN) != 0; |
261 | } |
262 | |
263 | static int i2c_m_recv_len(const struct i2c_msg *msg) |
264 | { |
265 | return (msg->flags & I2C_M_RECV_LEN) != 0; |
266 | } |
267 | |
268 | /* |
269 | * axxia_i2c_empty_rx_fifo - Fetch data from RX FIFO and update SMBus block |
270 | * transfer length if this is the first byte of such a transfer. |
271 | */ |
272 | static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev) |
273 | { |
274 | struct i2c_msg *msg = idev->msg_r; |
275 | size_t rx_fifo_avail = readl(addr: idev->base + MST_RX_FIFO); |
276 | int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd_r); |
277 | |
278 | while (bytes_to_transfer-- > 0) { |
279 | int c = readl(addr: idev->base + MST_DATA); |
280 | |
281 | if (idev->msg_xfrd_r == 0 && i2c_m_recv_len(msg)) { |
282 | /* |
283 | * Check length byte for SMBus block read |
284 | */ |
285 | if (c <= 0 || c > I2C_SMBUS_BLOCK_MAX) { |
286 | idev->msg_err = -EPROTO; |
287 | i2c_int_disable(idev, mask: ~MST_STATUS_TSS); |
288 | complete(&idev->msg_complete); |
289 | break; |
290 | } |
291 | msg->len = 1 + c; |
292 | writel(val: msg->len, addr: idev->base + MST_RX_XFER); |
293 | } |
294 | msg->buf[idev->msg_xfrd_r++] = c; |
295 | } |
296 | |
297 | return 0; |
298 | } |
299 | |
300 | /* |
301 | * axxia_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer. |
302 | * @return: Number of bytes left to transfer. |
303 | */ |
304 | static int axxia_i2c_fill_tx_fifo(struct axxia_i2c_dev *idev) |
305 | { |
306 | struct i2c_msg *msg = idev->msg; |
307 | size_t tx_fifo_avail = FIFO_SIZE - readl(addr: idev->base + MST_TX_FIFO); |
308 | int bytes_to_transfer = min(tx_fifo_avail, msg->len - idev->msg_xfrd); |
309 | int ret = msg->len - idev->msg_xfrd - bytes_to_transfer; |
310 | |
311 | while (bytes_to_transfer-- > 0) |
312 | writel(val: msg->buf[idev->msg_xfrd++], addr: idev->base + MST_DATA); |
313 | |
314 | return ret; |
315 | } |
316 | |
317 | static void axxia_i2c_slv_fifo_event(struct axxia_i2c_dev *idev) |
318 | { |
319 | u32 fifo_status = readl(addr: idev->base + SLV_RX_FIFO); |
320 | u8 val; |
321 | |
322 | dev_dbg(idev->dev, "slave irq fifo_status=0x%x\n" , fifo_status); |
323 | |
324 | if (fifo_status & SLV_FIFO_DV1) { |
325 | if (fifo_status & SLV_FIFO_STRC) |
326 | i2c_slave_event(client: idev->slave, |
327 | event: I2C_SLAVE_WRITE_REQUESTED, val: &val); |
328 | |
329 | val = readl(addr: idev->base + SLV_DATA); |
330 | i2c_slave_event(client: idev->slave, event: I2C_SLAVE_WRITE_RECEIVED, val: &val); |
331 | } |
332 | if (fifo_status & SLV_FIFO_STPC) { |
333 | readl(addr: idev->base + SLV_DATA); /* dummy read */ |
334 | i2c_slave_event(client: idev->slave, event: I2C_SLAVE_STOP, val: &val); |
335 | } |
336 | if (fifo_status & SLV_FIFO_RSC) |
337 | readl(addr: idev->base + SLV_DATA); /* dummy read */ |
338 | } |
339 | |
340 | static irqreturn_t axxia_i2c_slv_isr(struct axxia_i2c_dev *idev) |
341 | { |
342 | u32 status = readl(addr: idev->base + SLV_INT_STATUS); |
343 | u8 val; |
344 | |
345 | dev_dbg(idev->dev, "slave irq status=0x%x\n" , status); |
346 | |
347 | if (status & SLV_STATUS_RFH) |
348 | axxia_i2c_slv_fifo_event(idev); |
349 | if (status & SLV_STATUS_SRS1) { |
350 | i2c_slave_event(client: idev->slave, event: I2C_SLAVE_READ_REQUESTED, val: &val); |
351 | writel(val, addr: idev->base + SLV_DATA); |
352 | } |
353 | if (status & SLV_STATUS_SRND1) { |
354 | i2c_slave_event(client: idev->slave, event: I2C_SLAVE_READ_PROCESSED, val: &val); |
355 | writel(val, addr: idev->base + SLV_DATA); |
356 | } |
357 | if (status & SLV_STATUS_SRC1) |
358 | i2c_slave_event(client: idev->slave, event: I2C_SLAVE_STOP, val: &val); |
359 | |
360 | writel(INT_SLV, addr: idev->base + INTERRUPT_STATUS); |
361 | return IRQ_HANDLED; |
362 | } |
363 | |
364 | static irqreturn_t axxia_i2c_isr(int irq, void *_dev) |
365 | { |
366 | struct axxia_i2c_dev *idev = _dev; |
367 | irqreturn_t ret = IRQ_NONE; |
368 | u32 status; |
369 | |
370 | status = readl(addr: idev->base + INTERRUPT_STATUS); |
371 | |
372 | if (status & INT_SLV) |
373 | ret = axxia_i2c_slv_isr(idev); |
374 | if (!(status & INT_MST)) |
375 | return ret; |
376 | |
377 | /* Read interrupt status bits */ |
378 | status = readl(addr: idev->base + MST_INT_STATUS); |
379 | |
380 | if (!idev->msg) { |
381 | dev_warn(idev->dev, "unexpected interrupt\n" ); |
382 | goto out; |
383 | } |
384 | |
385 | /* RX FIFO needs service? */ |
386 | if (i2c_m_rd(msg: idev->msg_r) && (status & MST_STATUS_RFL)) |
387 | axxia_i2c_empty_rx_fifo(idev); |
388 | |
389 | /* TX FIFO needs service? */ |
390 | if (!i2c_m_rd(msg: idev->msg) && (status & MST_STATUS_TFL)) { |
391 | if (axxia_i2c_fill_tx_fifo(idev) == 0) |
392 | i2c_int_disable(idev, MST_STATUS_TFL); |
393 | } |
394 | |
395 | if (unlikely(status & MST_STATUS_ERR)) { |
396 | /* Transfer error */ |
397 | i2c_int_disable(idev, mask: ~0); |
398 | if (status & MST_STATUS_AL) |
399 | idev->msg_err = -EAGAIN; |
400 | else if (status & MST_STATUS_NAK) |
401 | idev->msg_err = -ENXIO; |
402 | else |
403 | idev->msg_err = -EIO; |
404 | dev_dbg(idev->dev, "error %#x, addr=%#x rx=%u/%u tx=%u/%u\n" , |
405 | status, |
406 | idev->msg->addr, |
407 | readl(idev->base + MST_RX_BYTES_XFRD), |
408 | readl(idev->base + MST_RX_XFER), |
409 | readl(idev->base + MST_TX_BYTES_XFRD), |
410 | readl(idev->base + MST_TX_XFER)); |
411 | complete(&idev->msg_complete); |
412 | } else if (status & MST_STATUS_SCC) { |
413 | /* Stop completed */ |
414 | i2c_int_disable(idev, mask: ~MST_STATUS_TSS); |
415 | complete(&idev->msg_complete); |
416 | } else if (status & (MST_STATUS_SNS | MST_STATUS_SS)) { |
417 | /* Transfer done */ |
418 | int mask = idev->last ? ~0 : ~MST_STATUS_TSS; |
419 | |
420 | i2c_int_disable(idev, mask); |
421 | if (i2c_m_rd(msg: idev->msg_r) && idev->msg_xfrd_r < idev->msg_r->len) |
422 | axxia_i2c_empty_rx_fifo(idev); |
423 | complete(&idev->msg_complete); |
424 | } else if (status & MST_STATUS_TSS) { |
425 | /* Transfer timeout */ |
426 | idev->msg_err = -ETIMEDOUT; |
427 | i2c_int_disable(idev, mask: ~MST_STATUS_TSS); |
428 | complete(&idev->msg_complete); |
429 | } |
430 | |
431 | out: |
432 | /* Clear interrupt */ |
433 | writel(INT_MST, addr: idev->base + INTERRUPT_STATUS); |
434 | |
435 | return IRQ_HANDLED; |
436 | } |
437 | |
438 | static void axxia_i2c_set_addr(struct axxia_i2c_dev *idev, struct i2c_msg *msg) |
439 | { |
440 | u32 addr_1, addr_2; |
441 | |
442 | if (i2c_m_ten(msg)) { |
443 | /* 10-bit address |
444 | * addr_1: 5'b11110 | addr[9:8] | (R/nW) |
445 | * addr_2: addr[7:0] |
446 | */ |
447 | addr_1 = 0xF0 | ((msg->addr >> 7) & 0x06); |
448 | if (i2c_m_rd(msg)) |
449 | addr_1 |= 1; /* Set the R/nW bit of the address */ |
450 | addr_2 = msg->addr & 0xFF; |
451 | } else { |
452 | /* 7-bit address |
453 | * addr_1: addr[6:0] | (R/nW) |
454 | * addr_2: dont care |
455 | */ |
456 | addr_1 = i2c_8bit_addr_from_msg(msg); |
457 | addr_2 = 0; |
458 | } |
459 | |
460 | writel(val: addr_1, addr: idev->base + MST_ADDR_1); |
461 | writel(val: addr_2, addr: idev->base + MST_ADDR_2); |
462 | } |
463 | |
464 | /* The NAK interrupt will be sent _before_ issuing STOP command |
465 | * so the controller might still be busy processing it. No |
466 | * interrupt will be sent at the end so we have to poll for it |
467 | */ |
468 | static int axxia_i2c_handle_seq_nak(struct axxia_i2c_dev *idev) |
469 | { |
470 | unsigned long timeout = jiffies + I2C_XFER_TIMEOUT; |
471 | |
472 | do { |
473 | if ((readl(addr: idev->base + MST_COMMAND) & CMD_BUSY) == 0) |
474 | return 0; |
475 | usleep_range(min: 1, max: 100); |
476 | } while (time_before(jiffies, timeout)); |
477 | |
478 | return -ETIMEDOUT; |
479 | } |
480 | |
481 | static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[]) |
482 | { |
483 | u32 int_mask = MST_STATUS_ERR | MST_STATUS_SS | MST_STATUS_RFL; |
484 | u32 rlen = i2c_m_recv_len(msg: &msgs[1]) ? I2C_SMBUS_BLOCK_MAX : msgs[1].len; |
485 | unsigned long time_left; |
486 | |
487 | axxia_i2c_set_addr(idev, msg: &msgs[0]); |
488 | |
489 | writel(val: msgs[0].len, addr: idev->base + MST_TX_XFER); |
490 | writel(val: rlen, addr: idev->base + MST_RX_XFER); |
491 | |
492 | idev->msg = &msgs[0]; |
493 | idev->msg_r = &msgs[1]; |
494 | idev->msg_xfrd = 0; |
495 | idev->msg_xfrd_r = 0; |
496 | idev->last = true; |
497 | axxia_i2c_fill_tx_fifo(idev); |
498 | |
499 | writel(CMD_SEQUENCE, addr: idev->base + MST_COMMAND); |
500 | |
501 | reinit_completion(x: &idev->msg_complete); |
502 | i2c_int_enable(idev, mask: int_mask); |
503 | |
504 | time_left = wait_for_completion_timeout(x: &idev->msg_complete, |
505 | I2C_XFER_TIMEOUT); |
506 | |
507 | if (idev->msg_err == -ENXIO) { |
508 | if (axxia_i2c_handle_seq_nak(idev)) |
509 | axxia_i2c_init(idev); |
510 | } else if (readl(addr: idev->base + MST_COMMAND) & CMD_BUSY) { |
511 | dev_warn(idev->dev, "busy after xfer\n" ); |
512 | } |
513 | |
514 | if (time_left == 0) { |
515 | idev->msg_err = -ETIMEDOUT; |
516 | i2c_recover_bus(adap: &idev->adapter); |
517 | axxia_i2c_init(idev); |
518 | } |
519 | |
520 | if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO) |
521 | axxia_i2c_init(idev); |
522 | |
523 | return idev->msg_err; |
524 | } |
525 | |
526 | static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg, |
527 | bool last) |
528 | { |
529 | u32 int_mask = MST_STATUS_ERR; |
530 | u32 rx_xfer, tx_xfer; |
531 | unsigned long time_left; |
532 | unsigned int wt_value; |
533 | |
534 | idev->msg = msg; |
535 | idev->msg_r = msg; |
536 | idev->msg_xfrd = 0; |
537 | idev->msg_xfrd_r = 0; |
538 | idev->last = last; |
539 | reinit_completion(x: &idev->msg_complete); |
540 | |
541 | axxia_i2c_set_addr(idev, msg); |
542 | |
543 | if (i2c_m_rd(msg)) { |
544 | /* I2C read transfer */ |
545 | rx_xfer = i2c_m_recv_len(msg) ? I2C_SMBUS_BLOCK_MAX : msg->len; |
546 | tx_xfer = 0; |
547 | } else { |
548 | /* I2C write transfer */ |
549 | rx_xfer = 0; |
550 | tx_xfer = msg->len; |
551 | } |
552 | |
553 | writel(val: rx_xfer, addr: idev->base + MST_RX_XFER); |
554 | writel(val: tx_xfer, addr: idev->base + MST_TX_XFER); |
555 | |
556 | if (i2c_m_rd(msg)) |
557 | int_mask |= MST_STATUS_RFL; |
558 | else if (axxia_i2c_fill_tx_fifo(idev) != 0) |
559 | int_mask |= MST_STATUS_TFL; |
560 | |
561 | wt_value = WT_VALUE(readl(idev->base + WAIT_TIMER_CONTROL)); |
562 | /* Disable wait timer temporarly */ |
563 | writel(val: wt_value, addr: idev->base + WAIT_TIMER_CONTROL); |
564 | /* Check if timeout error happened */ |
565 | if (idev->msg_err) |
566 | goto out; |
567 | |
568 | if (!last) { |
569 | writel(CMD_MANUAL, addr: idev->base + MST_COMMAND); |
570 | int_mask |= MST_STATUS_SNS; |
571 | } else { |
572 | writel(CMD_AUTO, addr: idev->base + MST_COMMAND); |
573 | int_mask |= MST_STATUS_SS; |
574 | } |
575 | |
576 | writel(WT_EN | wt_value, addr: idev->base + WAIT_TIMER_CONTROL); |
577 | |
578 | i2c_int_enable(idev, mask: int_mask); |
579 | |
580 | time_left = wait_for_completion_timeout(x: &idev->msg_complete, |
581 | I2C_XFER_TIMEOUT); |
582 | |
583 | i2c_int_disable(idev, mask: int_mask); |
584 | |
585 | if (readl(addr: idev->base + MST_COMMAND) & CMD_BUSY) |
586 | dev_warn(idev->dev, "busy after xfer\n" ); |
587 | |
588 | if (time_left == 0) { |
589 | idev->msg_err = -ETIMEDOUT; |
590 | i2c_recover_bus(adap: &idev->adapter); |
591 | axxia_i2c_init(idev); |
592 | } |
593 | |
594 | out: |
595 | if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO && |
596 | idev->msg_err != -ETIMEDOUT) |
597 | axxia_i2c_init(idev); |
598 | |
599 | return idev->msg_err; |
600 | } |
601 | |
602 | /* This function checks if the msgs[] array contains messages compatible with |
603 | * Sequence mode of operation. This mode assumes there will be exactly one |
604 | * write of non-zero length followed by exactly one read of non-zero length, |
605 | * both targeted at the same client device. |
606 | */ |
607 | static bool axxia_i2c_sequence_ok(struct i2c_msg msgs[], int num) |
608 | { |
609 | return num == SEQ_LEN && !i2c_m_rd(msg: &msgs[0]) && i2c_m_rd(msg: &msgs[1]) && |
610 | msgs[0].len > 0 && msgs[0].len <= FIFO_SIZE && |
611 | msgs[1].len > 0 && msgs[0].addr == msgs[1].addr; |
612 | } |
613 | |
614 | static int |
615 | axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) |
616 | { |
617 | struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); |
618 | int i; |
619 | int ret = 0; |
620 | |
621 | idev->msg_err = 0; |
622 | |
623 | if (axxia_i2c_sequence_ok(msgs, num)) { |
624 | ret = axxia_i2c_xfer_seq(idev, msgs); |
625 | return ret ? : SEQ_LEN; |
626 | } |
627 | |
628 | i2c_int_enable(idev, MST_STATUS_TSS); |
629 | |
630 | for (i = 0; ret == 0 && i < num; ++i) |
631 | ret = axxia_i2c_xfer_msg(idev, msg: &msgs[i], last: i == (num - 1)); |
632 | |
633 | return ret ? : i; |
634 | } |
635 | |
636 | static int axxia_i2c_get_scl(struct i2c_adapter *adap) |
637 | { |
638 | struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); |
639 | |
640 | return !!(readl(addr: idev->base + I2C_BUS_MONITOR) & BM_SCLS); |
641 | } |
642 | |
643 | static void axxia_i2c_set_scl(struct i2c_adapter *adap, int val) |
644 | { |
645 | struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); |
646 | u32 tmp; |
647 | |
648 | /* Preserve SDA Control */ |
649 | tmp = readl(addr: idev->base + I2C_BUS_MONITOR) & BM_SDAC; |
650 | if (!val) |
651 | tmp |= BM_SCLC; |
652 | writel(val: tmp, addr: idev->base + I2C_BUS_MONITOR); |
653 | } |
654 | |
655 | static int axxia_i2c_get_sda(struct i2c_adapter *adap) |
656 | { |
657 | struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); |
658 | |
659 | return !!(readl(addr: idev->base + I2C_BUS_MONITOR) & BM_SDAS); |
660 | } |
661 | |
662 | static struct i2c_bus_recovery_info axxia_i2c_recovery_info = { |
663 | .recover_bus = i2c_generic_scl_recovery, |
664 | .get_scl = axxia_i2c_get_scl, |
665 | .set_scl = axxia_i2c_set_scl, |
666 | .get_sda = axxia_i2c_get_sda, |
667 | }; |
668 | |
669 | static u32 axxia_i2c_func(struct i2c_adapter *adap) |
670 | { |
671 | u32 caps = (I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | |
672 | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA); |
673 | return caps; |
674 | } |
675 | |
676 | static int axxia_i2c_reg_slave(struct i2c_client *slave) |
677 | { |
678 | struct axxia_i2c_dev *idev = i2c_get_adapdata(adap: slave->adapter); |
679 | u32 slv_int_mask = SLV_STATUS_RFH; |
680 | u32 dec_ctl; |
681 | |
682 | if (idev->slave) |
683 | return -EBUSY; |
684 | |
685 | idev->slave = slave; |
686 | |
687 | /* Enable slave mode as well */ |
688 | writel(GLOBAL_MST_EN | GLOBAL_SLV_EN, addr: idev->base + GLOBAL_CONTROL); |
689 | writel(INT_MST | INT_SLV, addr: idev->base + INTERRUPT_ENABLE); |
690 | |
691 | /* Set slave address */ |
692 | dec_ctl = SLV_ADDR_DEC_SA1E; |
693 | if (slave->flags & I2C_CLIENT_TEN) |
694 | dec_ctl |= SLV_ADDR_DEC_SA1M; |
695 | |
696 | writel(SLV_RX_ACSA1, addr: idev->base + SLV_RX_CTL); |
697 | writel(val: dec_ctl, addr: idev->base + SLV_ADDR_DEC_CTL); |
698 | writel(val: slave->addr, addr: idev->base + SLV_ADDR_1); |
699 | |
700 | /* Enable interrupts */ |
701 | slv_int_mask |= SLV_STATUS_SRS1 | SLV_STATUS_SRRS1 | SLV_STATUS_SRND1; |
702 | slv_int_mask |= SLV_STATUS_SRC1; |
703 | writel(val: slv_int_mask, addr: idev->base + SLV_INT_ENABLE); |
704 | |
705 | return 0; |
706 | } |
707 | |
708 | static int axxia_i2c_unreg_slave(struct i2c_client *slave) |
709 | { |
710 | struct axxia_i2c_dev *idev = i2c_get_adapdata(adap: slave->adapter); |
711 | |
712 | /* Disable slave mode */ |
713 | writel(GLOBAL_MST_EN, addr: idev->base + GLOBAL_CONTROL); |
714 | writel(INT_MST, addr: idev->base + INTERRUPT_ENABLE); |
715 | |
716 | synchronize_irq(irq: idev->irq); |
717 | |
718 | idev->slave = NULL; |
719 | |
720 | return 0; |
721 | } |
722 | |
723 | static const struct i2c_algorithm axxia_i2c_algo = { |
724 | .master_xfer = axxia_i2c_xfer, |
725 | .functionality = axxia_i2c_func, |
726 | .reg_slave = axxia_i2c_reg_slave, |
727 | .unreg_slave = axxia_i2c_unreg_slave, |
728 | }; |
729 | |
730 | static const struct i2c_adapter_quirks axxia_i2c_quirks = { |
731 | .max_read_len = 255, |
732 | .max_write_len = 255, |
733 | }; |
734 | |
735 | static int axxia_i2c_probe(struct platform_device *pdev) |
736 | { |
737 | struct device_node *np = pdev->dev.of_node; |
738 | struct axxia_i2c_dev *idev = NULL; |
739 | void __iomem *base; |
740 | int ret = 0; |
741 | |
742 | idev = devm_kzalloc(dev: &pdev->dev, size: sizeof(*idev), GFP_KERNEL); |
743 | if (!idev) |
744 | return -ENOMEM; |
745 | |
746 | base = devm_platform_ioremap_resource(pdev, index: 0); |
747 | if (IS_ERR(ptr: base)) |
748 | return PTR_ERR(ptr: base); |
749 | |
750 | idev->irq = platform_get_irq(pdev, 0); |
751 | if (idev->irq < 0) |
752 | return idev->irq; |
753 | |
754 | idev->i2c_clk = devm_clk_get(dev: &pdev->dev, id: "i2c" ); |
755 | if (IS_ERR(ptr: idev->i2c_clk)) { |
756 | dev_err(&pdev->dev, "missing clock\n" ); |
757 | return PTR_ERR(ptr: idev->i2c_clk); |
758 | } |
759 | |
760 | idev->base = base; |
761 | idev->dev = &pdev->dev; |
762 | init_completion(x: &idev->msg_complete); |
763 | |
764 | of_property_read_u32(np, propname: "clock-frequency" , out_value: &idev->bus_clk_rate); |
765 | if (idev->bus_clk_rate == 0) |
766 | idev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; /* default clock rate */ |
767 | |
768 | ret = clk_prepare_enable(clk: idev->i2c_clk); |
769 | if (ret) { |
770 | dev_err(&pdev->dev, "failed to enable clock\n" ); |
771 | return ret; |
772 | } |
773 | |
774 | ret = axxia_i2c_init(idev); |
775 | if (ret) { |
776 | dev_err(&pdev->dev, "failed to initialize\n" ); |
777 | goto error_disable_clk; |
778 | } |
779 | |
780 | ret = devm_request_irq(dev: &pdev->dev, irq: idev->irq, handler: axxia_i2c_isr, irqflags: 0, |
781 | devname: pdev->name, dev_id: idev); |
782 | if (ret) { |
783 | dev_err(&pdev->dev, "failed to claim IRQ%d\n" , idev->irq); |
784 | goto error_disable_clk; |
785 | } |
786 | |
787 | i2c_set_adapdata(adap: &idev->adapter, data: idev); |
788 | strscpy(p: idev->adapter.name, q: pdev->name, size: sizeof(idev->adapter.name)); |
789 | idev->adapter.owner = THIS_MODULE; |
790 | idev->adapter.algo = &axxia_i2c_algo; |
791 | idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info; |
792 | idev->adapter.quirks = &axxia_i2c_quirks; |
793 | idev->adapter.dev.parent = &pdev->dev; |
794 | idev->adapter.dev.of_node = pdev->dev.of_node; |
795 | |
796 | platform_set_drvdata(pdev, data: idev); |
797 | |
798 | ret = i2c_add_adapter(adap: &idev->adapter); |
799 | if (ret) |
800 | goto error_disable_clk; |
801 | |
802 | return 0; |
803 | |
804 | error_disable_clk: |
805 | clk_disable_unprepare(clk: idev->i2c_clk); |
806 | return ret; |
807 | } |
808 | |
809 | static void axxia_i2c_remove(struct platform_device *pdev) |
810 | { |
811 | struct axxia_i2c_dev *idev = platform_get_drvdata(pdev); |
812 | |
813 | clk_disable_unprepare(clk: idev->i2c_clk); |
814 | i2c_del_adapter(adap: &idev->adapter); |
815 | } |
816 | |
817 | /* Match table for of_platform binding */ |
818 | static const struct of_device_id axxia_i2c_of_match[] = { |
819 | { .compatible = "lsi,api2c" , }, |
820 | {}, |
821 | }; |
822 | |
823 | MODULE_DEVICE_TABLE(of, axxia_i2c_of_match); |
824 | |
825 | static struct platform_driver axxia_i2c_driver = { |
826 | .probe = axxia_i2c_probe, |
827 | .remove_new = axxia_i2c_remove, |
828 | .driver = { |
829 | .name = "axxia-i2c" , |
830 | .of_match_table = axxia_i2c_of_match, |
831 | }, |
832 | }; |
833 | |
834 | module_platform_driver(axxia_i2c_driver); |
835 | |
836 | MODULE_DESCRIPTION("Axxia I2C Bus driver" ); |
837 | MODULE_AUTHOR("Anders Berg <anders.berg@lsi.com>" ); |
838 | MODULE_LICENSE("GPL v2" ); |
839 | |