1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Synopsys DesignWare I2C adapter driver. |
4 | * |
5 | * Based on the TI DAVINCI I2C adapter driver. |
6 | * |
7 | * Copyright (C) 2006 Texas Instruments. |
8 | * Copyright (C) 2007 MontaVista Software Inc. |
9 | * Copyright (C) 2009 Provigent Ltd. |
10 | */ |
11 | #include <linux/acpi.h> |
12 | #include <linux/clk.h> |
13 | #include <linux/delay.h> |
14 | #include <linux/device.h> |
15 | #include <linux/err.h> |
16 | #include <linux/errno.h> |
17 | #include <linux/export.h> |
18 | #include <linux/i2c.h> |
19 | #include <linux/interrupt.h> |
20 | #include <linux/io.h> |
21 | #include <linux/kernel.h> |
22 | #include <linux/module.h> |
23 | #include <linux/pm_runtime.h> |
24 | #include <linux/regmap.h> |
25 | #include <linux/swab.h> |
26 | #include <linux/types.h> |
27 | #include <linux/units.h> |
28 | |
29 | #include "i2c-designware-core.h" |
30 | |
31 | static char *abort_sources[] = { |
32 | [ABRT_7B_ADDR_NOACK] = |
33 | "slave address not acknowledged (7bit mode)" , |
34 | [ABRT_10ADDR1_NOACK] = |
35 | "first address byte not acknowledged (10bit mode)" , |
36 | [ABRT_10ADDR2_NOACK] = |
37 | "second address byte not acknowledged (10bit mode)" , |
38 | [ABRT_TXDATA_NOACK] = |
39 | "data not acknowledged" , |
40 | [ABRT_GCALL_NOACK] = |
41 | "no acknowledgement for a general call" , |
42 | [ABRT_GCALL_READ] = |
43 | "read after general call" , |
44 | [ABRT_SBYTE_ACKDET] = |
45 | "start byte acknowledged" , |
46 | [ABRT_SBYTE_NORSTRT] = |
47 | "trying to send start byte when restart is disabled" , |
48 | [ABRT_10B_RD_NORSTRT] = |
49 | "trying to read when restart is disabled (10bit mode)" , |
50 | [ABRT_MASTER_DIS] = |
51 | "trying to use disabled adapter" , |
52 | [ARB_LOST] = |
53 | "lost arbitration" , |
54 | [ABRT_SLAVE_FLUSH_TXFIFO] = |
55 | "read command so flush old data in the TX FIFO" , |
56 | [ABRT_SLAVE_ARBLOST] = |
57 | "slave lost the bus while transmitting data to a remote master" , |
58 | [ABRT_SLAVE_RD_INTX] = |
59 | "incorrect slave-transmitter mode configuration" , |
60 | }; |
61 | |
62 | static int dw_reg_read(void *context, unsigned int reg, unsigned int *val) |
63 | { |
64 | struct dw_i2c_dev *dev = context; |
65 | |
66 | *val = readl_relaxed(dev->base + reg); |
67 | |
68 | return 0; |
69 | } |
70 | |
71 | static int dw_reg_write(void *context, unsigned int reg, unsigned int val) |
72 | { |
73 | struct dw_i2c_dev *dev = context; |
74 | |
75 | writel_relaxed(val, dev->base + reg); |
76 | |
77 | return 0; |
78 | } |
79 | |
80 | static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val) |
81 | { |
82 | struct dw_i2c_dev *dev = context; |
83 | |
84 | *val = swab32(readl_relaxed(dev->base + reg)); |
85 | |
86 | return 0; |
87 | } |
88 | |
89 | static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val) |
90 | { |
91 | struct dw_i2c_dev *dev = context; |
92 | |
93 | writel_relaxed(swab32(val), dev->base + reg); |
94 | |
95 | return 0; |
96 | } |
97 | |
98 | static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val) |
99 | { |
100 | struct dw_i2c_dev *dev = context; |
101 | |
102 | *val = readw_relaxed(dev->base + reg) | |
103 | (readw_relaxed(dev->base + reg + 2) << 16); |
104 | |
105 | return 0; |
106 | } |
107 | |
108 | static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val) |
109 | { |
110 | struct dw_i2c_dev *dev = context; |
111 | |
112 | writew_relaxed(val, dev->base + reg); |
113 | writew_relaxed(val >> 16, dev->base + reg + 2); |
114 | |
115 | return 0; |
116 | } |
117 | |
118 | /** |
119 | * i2c_dw_init_regmap() - Initialize registers map |
120 | * @dev: device private data |
121 | * |
122 | * Autodetects needed register access mode and creates the regmap with |
123 | * corresponding read/write callbacks. This must be called before doing any |
124 | * other register access. |
125 | */ |
126 | int i2c_dw_init_regmap(struct dw_i2c_dev *dev) |
127 | { |
128 | struct regmap_config map_cfg = { |
129 | .reg_bits = 32, |
130 | .val_bits = 32, |
131 | .reg_stride = 4, |
132 | .disable_locking = true, |
133 | .reg_read = dw_reg_read, |
134 | .reg_write = dw_reg_write, |
135 | .max_register = DW_IC_COMP_TYPE, |
136 | }; |
137 | u32 reg; |
138 | int ret; |
139 | |
140 | /* |
141 | * Skip detecting the registers map configuration if the regmap has |
142 | * already been provided by a higher code. |
143 | */ |
144 | if (dev->map) |
145 | return 0; |
146 | |
147 | ret = i2c_dw_acquire_lock(dev); |
148 | if (ret) |
149 | return ret; |
150 | |
151 | reg = readl(addr: dev->base + DW_IC_COMP_TYPE); |
152 | i2c_dw_release_lock(dev); |
153 | |
154 | if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) |
155 | map_cfg.max_register = AMD_UCSI_INTR_REG; |
156 | |
157 | if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) { |
158 | map_cfg.reg_read = dw_reg_read_swab; |
159 | map_cfg.reg_write = dw_reg_write_swab; |
160 | } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { |
161 | map_cfg.reg_read = dw_reg_read_word; |
162 | map_cfg.reg_write = dw_reg_write_word; |
163 | } else if (reg != DW_IC_COMP_TYPE_VALUE) { |
164 | dev_err(dev->dev, |
165 | "Unknown Synopsys component type: 0x%08x\n" , reg); |
166 | return -ENODEV; |
167 | } |
168 | |
169 | /* |
170 | * Note we'll check the return value of the regmap IO accessors only |
171 | * at the probe stage. The rest of the code won't do this because |
172 | * basically we have MMIO-based regmap so non of the read/write methods |
173 | * can fail. |
174 | */ |
175 | dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg); |
176 | if (IS_ERR(ptr: dev->map)) { |
177 | dev_err(dev->dev, "Failed to init the registers map\n" ); |
178 | return PTR_ERR(ptr: dev->map); |
179 | } |
180 | |
181 | return 0; |
182 | } |
183 | |
184 | static const u32 supported_speeds[] = { |
185 | I2C_MAX_HIGH_SPEED_MODE_FREQ, |
186 | I2C_MAX_FAST_MODE_PLUS_FREQ, |
187 | I2C_MAX_FAST_MODE_FREQ, |
188 | I2C_MAX_STANDARD_MODE_FREQ, |
189 | }; |
190 | |
191 | int i2c_dw_validate_speed(struct dw_i2c_dev *dev) |
192 | { |
193 | struct i2c_timings *t = &dev->timings; |
194 | unsigned int i; |
195 | |
196 | /* |
197 | * Only standard mode at 100kHz, fast mode at 400kHz, |
198 | * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported. |
199 | */ |
200 | for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) { |
201 | if (t->bus_freq_hz == supported_speeds[i]) |
202 | return 0; |
203 | } |
204 | |
205 | dev_err(dev->dev, |
206 | "%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n" , |
207 | t->bus_freq_hz); |
208 | |
209 | return -EINVAL; |
210 | } |
211 | EXPORT_SYMBOL_GPL(i2c_dw_validate_speed); |
212 | |
213 | #ifdef CONFIG_ACPI |
214 | |
215 | #include <linux/dmi.h> |
216 | |
217 | /* |
218 | * The HCNT/LCNT information coming from ACPI should be the most accurate |
219 | * for given platform. However, some systems get it wrong. On such systems |
220 | * we get better results by calculating those based on the input clock. |
221 | */ |
222 | static const struct dmi_system_id i2c_dw_no_acpi_params[] = { |
223 | { |
224 | .ident = "Dell Inspiron 7348" , |
225 | .matches = { |
226 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc." ), |
227 | DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348" ), |
228 | }, |
229 | }, |
230 | {} |
231 | }; |
232 | |
233 | static void i2c_dw_acpi_params(struct device *device, char method[], |
234 | u16 *hcnt, u16 *lcnt, u32 *sda_hold) |
235 | { |
236 | struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER }; |
237 | acpi_handle handle = ACPI_HANDLE(device); |
238 | union acpi_object *obj; |
239 | |
240 | if (dmi_check_system(list: i2c_dw_no_acpi_params)) |
241 | return; |
242 | |
243 | if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf))) |
244 | return; |
245 | |
246 | obj = (union acpi_object *)buf.pointer; |
247 | if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) { |
248 | const union acpi_object *objs = obj->package.elements; |
249 | |
250 | *hcnt = (u16)objs[0].integer.value; |
251 | *lcnt = (u16)objs[1].integer.value; |
252 | *sda_hold = (u32)objs[2].integer.value; |
253 | } |
254 | |
255 | kfree(objp: buf.pointer); |
256 | } |
257 | |
258 | int i2c_dw_acpi_configure(struct device *device) |
259 | { |
260 | struct dw_i2c_dev *dev = dev_get_drvdata(dev: device); |
261 | struct i2c_timings *t = &dev->timings; |
262 | u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0; |
263 | |
264 | /* |
265 | * Try to get SDA hold time and *CNT values from an ACPI method for |
266 | * selected speed modes. |
267 | */ |
268 | i2c_dw_acpi_params(device, method: "SSCN" , hcnt: &dev->ss_hcnt, lcnt: &dev->ss_lcnt, sda_hold: &ss_ht); |
269 | i2c_dw_acpi_params(device, method: "FMCN" , hcnt: &dev->fs_hcnt, lcnt: &dev->fs_lcnt, sda_hold: &fs_ht); |
270 | i2c_dw_acpi_params(device, method: "FPCN" , hcnt: &dev->fp_hcnt, lcnt: &dev->fp_lcnt, sda_hold: &fp_ht); |
271 | i2c_dw_acpi_params(device, method: "HSCN" , hcnt: &dev->hs_hcnt, lcnt: &dev->hs_lcnt, sda_hold: &hs_ht); |
272 | |
273 | switch (t->bus_freq_hz) { |
274 | case I2C_MAX_STANDARD_MODE_FREQ: |
275 | dev->sda_hold_time = ss_ht; |
276 | break; |
277 | case I2C_MAX_FAST_MODE_PLUS_FREQ: |
278 | dev->sda_hold_time = fp_ht; |
279 | break; |
280 | case I2C_MAX_HIGH_SPEED_MODE_FREQ: |
281 | dev->sda_hold_time = hs_ht; |
282 | break; |
283 | case I2C_MAX_FAST_MODE_FREQ: |
284 | default: |
285 | dev->sda_hold_time = fs_ht; |
286 | break; |
287 | } |
288 | |
289 | return 0; |
290 | } |
291 | EXPORT_SYMBOL_GPL(i2c_dw_acpi_configure); |
292 | |
293 | static u32 i2c_dw_acpi_round_bus_speed(struct device *device) |
294 | { |
295 | u32 acpi_speed; |
296 | int i; |
297 | |
298 | acpi_speed = i2c_acpi_find_bus_speed(dev: device); |
299 | /* |
300 | * Some DSTDs use a non standard speed, round down to the lowest |
301 | * standard speed. |
302 | */ |
303 | for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) { |
304 | if (acpi_speed >= supported_speeds[i]) |
305 | return supported_speeds[i]; |
306 | } |
307 | |
308 | return 0; |
309 | } |
310 | |
311 | #else /* CONFIG_ACPI */ |
312 | |
313 | static inline u32 i2c_dw_acpi_round_bus_speed(struct device *device) { return 0; } |
314 | |
315 | #endif /* CONFIG_ACPI */ |
316 | |
317 | void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev) |
318 | { |
319 | u32 acpi_speed = i2c_dw_acpi_round_bus_speed(device: dev->dev); |
320 | struct i2c_timings *t = &dev->timings; |
321 | |
322 | /* |
323 | * Find bus speed from the "clock-frequency" device property, ACPI |
324 | * or by using fast mode if neither is set. |
325 | */ |
326 | if (acpi_speed && t->bus_freq_hz) |
327 | t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed); |
328 | else if (acpi_speed || t->bus_freq_hz) |
329 | t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed); |
330 | else |
331 | t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; |
332 | } |
333 | EXPORT_SYMBOL_GPL(i2c_dw_adjust_bus_speed); |
334 | |
335 | u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) |
336 | { |
337 | /* |
338 | * DesignWare I2C core doesn't seem to have solid strategy to meet |
339 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec |
340 | * will result in violation of the tHD;STA spec. |
341 | */ |
342 | if (cond) |
343 | /* |
344 | * Conditional expression: |
345 | * |
346 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH |
347 | * |
348 | * This is based on the DW manuals, and represents an ideal |
349 | * configuration. The resulting I2C bus speed will be |
350 | * faster than any of the others. |
351 | * |
352 | * If your hardware is free from tHD;STA issue, try this one. |
353 | */ |
354 | return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * tSYMBOL, MICRO) - |
355 | 8 + offset; |
356 | else |
357 | /* |
358 | * Conditional expression: |
359 | * |
360 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) |
361 | * |
362 | * This is just experimental rule; the tHD;STA period turned |
363 | * out to be proportinal to (_HCNT + 3). With this setting, |
364 | * we could meet both tHIGH and tHD;STA timing specs. |
365 | * |
366 | * If unsure, you'd better to take this alternative. |
367 | * |
368 | * The reason why we need to take into account "tf" here, |
369 | * is the same as described in i2c_dw_scl_lcnt(). |
370 | */ |
371 | return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tSYMBOL + tf), MICRO) - |
372 | 3 + offset; |
373 | } |
374 | |
375 | u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) |
376 | { |
377 | /* |
378 | * Conditional expression: |
379 | * |
380 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) |
381 | * |
382 | * DW I2C core starts counting the SCL CNTs for the LOW period |
383 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. |
384 | * In order to meet the tLOW timing spec, we need to take into |
385 | * account the fall time of SCL signal (tf). Default tf value |
386 | * should be 0.3 us, for safety. |
387 | */ |
388 | return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tLOW + tf), MICRO) - |
389 | 1 + offset; |
390 | } |
391 | |
392 | int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev) |
393 | { |
394 | unsigned int reg; |
395 | int ret; |
396 | |
397 | ret = i2c_dw_acquire_lock(dev); |
398 | if (ret) |
399 | return ret; |
400 | |
401 | /* Configure SDA Hold Time if required */ |
402 | ret = regmap_read(map: dev->map, DW_IC_COMP_VERSION, val: ®); |
403 | if (ret) |
404 | goto err_release_lock; |
405 | |
406 | if (reg >= DW_IC_SDA_HOLD_MIN_VERS) { |
407 | if (!dev->sda_hold_time) { |
408 | /* Keep previous hold time setting if no one set it */ |
409 | ret = regmap_read(map: dev->map, DW_IC_SDA_HOLD, |
410 | val: &dev->sda_hold_time); |
411 | if (ret) |
412 | goto err_release_lock; |
413 | } |
414 | |
415 | /* |
416 | * Workaround for avoiding TX arbitration lost in case I2C |
417 | * slave pulls SDA down "too quickly" after falling edge of |
418 | * SCL by enabling non-zero SDA RX hold. Specification says it |
419 | * extends incoming SDA low to high transition while SCL is |
420 | * high but it appears to help also above issue. |
421 | */ |
422 | if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK)) |
423 | dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT; |
424 | |
425 | dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n" , |
426 | dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK, |
427 | dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT); |
428 | } else if (dev->set_sda_hold_time) { |
429 | dev->set_sda_hold_time(dev); |
430 | } else if (dev->sda_hold_time) { |
431 | dev_warn(dev->dev, |
432 | "Hardware too old to adjust SDA hold time.\n" ); |
433 | dev->sda_hold_time = 0; |
434 | } |
435 | |
436 | err_release_lock: |
437 | i2c_dw_release_lock(dev); |
438 | |
439 | return ret; |
440 | } |
441 | |
442 | void __i2c_dw_disable(struct dw_i2c_dev *dev) |
443 | { |
444 | unsigned int raw_intr_stats; |
445 | unsigned int enable; |
446 | int timeout = 100; |
447 | bool abort_needed; |
448 | unsigned int status; |
449 | int ret; |
450 | |
451 | regmap_read(map: dev->map, DW_IC_RAW_INTR_STAT, val: &raw_intr_stats); |
452 | regmap_read(map: dev->map, DW_IC_ENABLE, val: &enable); |
453 | |
454 | abort_needed = raw_intr_stats & DW_IC_INTR_MST_ON_HOLD; |
455 | if (abort_needed) { |
456 | regmap_write(map: dev->map, DW_IC_ENABLE, val: enable | DW_IC_ENABLE_ABORT); |
457 | ret = regmap_read_poll_timeout(dev->map, DW_IC_ENABLE, enable, |
458 | !(enable & DW_IC_ENABLE_ABORT), 10, |
459 | 100); |
460 | if (ret) |
461 | dev_err(dev->dev, "timeout while trying to abort current transfer\n" ); |
462 | } |
463 | |
464 | do { |
465 | __i2c_dw_disable_nowait(dev); |
466 | /* |
467 | * The enable status register may be unimplemented, but |
468 | * in that case this test reads zero and exits the loop. |
469 | */ |
470 | regmap_read(map: dev->map, DW_IC_ENABLE_STATUS, val: &status); |
471 | if ((status & 1) == 0) |
472 | return; |
473 | |
474 | /* |
475 | * Wait 10 times the signaling period of the highest I2C |
476 | * transfer supported by the driver (for 400KHz this is |
477 | * 25us) as described in the DesignWare I2C databook. |
478 | */ |
479 | usleep_range(min: 25, max: 250); |
480 | } while (timeout--); |
481 | |
482 | dev_warn(dev->dev, "timeout in disabling adapter\n" ); |
483 | } |
484 | |
485 | u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev) |
486 | { |
487 | /* |
488 | * Clock is not necessary if we got LCNT/HCNT values directly from |
489 | * the platform code. |
490 | */ |
491 | if (WARN_ON_ONCE(!dev->get_clk_rate_khz)) |
492 | return 0; |
493 | return dev->get_clk_rate_khz(dev); |
494 | } |
495 | |
496 | int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare) |
497 | { |
498 | int ret; |
499 | |
500 | if (prepare) { |
501 | /* Optional interface clock */ |
502 | ret = clk_prepare_enable(clk: dev->pclk); |
503 | if (ret) |
504 | return ret; |
505 | |
506 | ret = clk_prepare_enable(clk: dev->clk); |
507 | if (ret) |
508 | clk_disable_unprepare(clk: dev->pclk); |
509 | |
510 | return ret; |
511 | } |
512 | |
513 | clk_disable_unprepare(clk: dev->clk); |
514 | clk_disable_unprepare(clk: dev->pclk); |
515 | |
516 | return 0; |
517 | } |
518 | EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk); |
519 | |
520 | int i2c_dw_acquire_lock(struct dw_i2c_dev *dev) |
521 | { |
522 | int ret; |
523 | |
524 | if (!dev->acquire_lock) |
525 | return 0; |
526 | |
527 | ret = dev->acquire_lock(); |
528 | if (!ret) |
529 | return 0; |
530 | |
531 | dev_err(dev->dev, "couldn't acquire bus ownership\n" ); |
532 | |
533 | return ret; |
534 | } |
535 | |
536 | void i2c_dw_release_lock(struct dw_i2c_dev *dev) |
537 | { |
538 | if (dev->release_lock) |
539 | dev->release_lock(); |
540 | } |
541 | |
542 | /* |
543 | * Waiting for bus not busy |
544 | */ |
545 | int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) |
546 | { |
547 | unsigned int status; |
548 | int ret; |
549 | |
550 | ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status, |
551 | !(status & DW_IC_STATUS_ACTIVITY), |
552 | 1100, 20000); |
553 | if (ret) { |
554 | dev_warn(dev->dev, "timeout waiting for bus ready\n" ); |
555 | |
556 | i2c_recover_bus(adap: &dev->adapter); |
557 | |
558 | regmap_read(map: dev->map, DW_IC_STATUS, val: &status); |
559 | if (!(status & DW_IC_STATUS_ACTIVITY)) |
560 | ret = 0; |
561 | } |
562 | |
563 | return ret; |
564 | } |
565 | |
566 | int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) |
567 | { |
568 | unsigned long abort_source = dev->abort_source; |
569 | int i; |
570 | |
571 | if (abort_source & DW_IC_TX_ABRT_NOACK) { |
572 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
573 | dev_dbg(dev->dev, |
574 | "%s: %s\n" , __func__, abort_sources[i]); |
575 | return -EREMOTEIO; |
576 | } |
577 | |
578 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
579 | dev_err(dev->dev, "%s: %s\n" , __func__, abort_sources[i]); |
580 | |
581 | if (abort_source & DW_IC_TX_ARB_LOST) |
582 | return -EAGAIN; |
583 | else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) |
584 | return -EINVAL; /* wrong msgs[] data */ |
585 | else |
586 | return -EIO; |
587 | } |
588 | |
589 | int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev) |
590 | { |
591 | u32 tx_fifo_depth, rx_fifo_depth; |
592 | unsigned int param; |
593 | int ret; |
594 | |
595 | /* DW_IC_COMP_PARAM_1 not implement for IP issue */ |
596 | if ((dev->flags & MODEL_MASK) == MODEL_WANGXUN_SP) { |
597 | dev->tx_fifo_depth = TXGBE_TX_FIFO_DEPTH; |
598 | dev->rx_fifo_depth = TXGBE_RX_FIFO_DEPTH; |
599 | |
600 | return 0; |
601 | } |
602 | |
603 | /* |
604 | * Try to detect the FIFO depth if not set by interface driver, |
605 | * the depth could be from 2 to 256 from HW spec. |
606 | */ |
607 | ret = i2c_dw_acquire_lock(dev); |
608 | if (ret) |
609 | return ret; |
610 | |
611 | ret = regmap_read(map: dev->map, DW_IC_COMP_PARAM_1, val: ¶m); |
612 | i2c_dw_release_lock(dev); |
613 | if (ret) |
614 | return ret; |
615 | |
616 | tx_fifo_depth = ((param >> 16) & 0xff) + 1; |
617 | rx_fifo_depth = ((param >> 8) & 0xff) + 1; |
618 | if (!dev->tx_fifo_depth) { |
619 | dev->tx_fifo_depth = tx_fifo_depth; |
620 | dev->rx_fifo_depth = rx_fifo_depth; |
621 | } else if (tx_fifo_depth >= 2) { |
622 | dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth, |
623 | tx_fifo_depth); |
624 | dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth, |
625 | rx_fifo_depth); |
626 | } |
627 | |
628 | return 0; |
629 | } |
630 | |
631 | u32 i2c_dw_func(struct i2c_adapter *adap) |
632 | { |
633 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); |
634 | |
635 | return dev->functionality; |
636 | } |
637 | |
638 | void i2c_dw_disable(struct dw_i2c_dev *dev) |
639 | { |
640 | unsigned int dummy; |
641 | int ret; |
642 | |
643 | ret = i2c_dw_acquire_lock(dev); |
644 | if (ret) |
645 | return; |
646 | |
647 | /* Disable controller */ |
648 | __i2c_dw_disable(dev); |
649 | |
650 | /* Disable all interrupts */ |
651 | regmap_write(map: dev->map, DW_IC_INTR_MASK, val: 0); |
652 | regmap_read(map: dev->map, DW_IC_CLR_INTR, val: &dummy); |
653 | |
654 | i2c_dw_release_lock(dev); |
655 | } |
656 | |
657 | MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core" ); |
658 | MODULE_LICENSE("GPL" ); |
659 | |