1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Renesas Solutions Highlander FPGA I2C/SMBus support. |
4 | * |
5 | * Supported devices: R0P7780LC0011RL, R0P7785LC0011RL |
6 | * |
7 | * Copyright (C) 2008 Paul Mundt |
8 | * Copyright (C) 2008 Renesas Solutions Corp. |
9 | * Copyright (C) 2008 Atom Create Engineering Co., Ltd. |
10 | */ |
11 | #include <linux/module.h> |
12 | #include <linux/interrupt.h> |
13 | #include <linux/i2c.h> |
14 | #include <linux/platform_device.h> |
15 | #include <linux/completion.h> |
16 | #include <linux/io.h> |
17 | #include <linux/delay.h> |
18 | #include <linux/slab.h> |
19 | |
20 | #define SMCR 0x00 |
21 | #define SMCR_START (1 << 0) |
22 | #define SMCR_IRIC (1 << 1) |
23 | #define SMCR_BBSY (1 << 2) |
24 | #define SMCR_ACKE (1 << 3) |
25 | #define SMCR_RST (1 << 4) |
26 | #define SMCR_IEIC (1 << 6) |
27 | |
28 | #define SMSMADR 0x02 |
29 | |
30 | #define SMMR 0x04 |
31 | #define SMMR_MODE0 (1 << 0) |
32 | #define SMMR_MODE1 (1 << 1) |
33 | #define SMMR_CAP (1 << 3) |
34 | #define SMMR_TMMD (1 << 4) |
35 | #define SMMR_SP (1 << 7) |
36 | |
37 | #define SMSADR 0x06 |
38 | #define SMTRDR 0x46 |
39 | |
40 | struct highlander_i2c_dev { |
41 | struct device *dev; |
42 | void __iomem *base; |
43 | struct i2c_adapter adapter; |
44 | struct completion cmd_complete; |
45 | unsigned long last_read_time; |
46 | int irq; |
47 | u8 *buf; |
48 | size_t buf_len; |
49 | }; |
50 | |
51 | static bool iic_force_poll, iic_force_normal; |
52 | static int iic_timeout = 1000, iic_read_delay; |
53 | |
54 | static inline void highlander_i2c_irq_enable(struct highlander_i2c_dev *dev) |
55 | { |
56 | iowrite16(ioread16(dev->base + SMCR) | SMCR_IEIC, dev->base + SMCR); |
57 | } |
58 | |
59 | static inline void highlander_i2c_irq_disable(struct highlander_i2c_dev *dev) |
60 | { |
61 | iowrite16(ioread16(dev->base + SMCR) & ~SMCR_IEIC, dev->base + SMCR); |
62 | } |
63 | |
64 | static inline void highlander_i2c_start(struct highlander_i2c_dev *dev) |
65 | { |
66 | iowrite16(ioread16(dev->base + SMCR) | SMCR_START, dev->base + SMCR); |
67 | } |
68 | |
69 | static inline void highlander_i2c_done(struct highlander_i2c_dev *dev) |
70 | { |
71 | iowrite16(ioread16(dev->base + SMCR) | SMCR_IRIC, dev->base + SMCR); |
72 | } |
73 | |
74 | static void highlander_i2c_setup(struct highlander_i2c_dev *dev) |
75 | { |
76 | u16 smmr; |
77 | |
78 | smmr = ioread16(dev->base + SMMR); |
79 | smmr |= SMMR_TMMD; |
80 | |
81 | if (iic_force_normal) |
82 | smmr &= ~SMMR_SP; |
83 | else |
84 | smmr |= SMMR_SP; |
85 | |
86 | iowrite16(smmr, dev->base + SMMR); |
87 | } |
88 | |
89 | static void smbus_write_data(u8 *src, u16 *dst, int len) |
90 | { |
91 | for (; len > 1; len -= 2) { |
92 | *dst++ = be16_to_cpup(p: (__be16 *)src); |
93 | src += 2; |
94 | } |
95 | |
96 | if (len) |
97 | *dst = *src << 8; |
98 | } |
99 | |
100 | static void smbus_read_data(u16 *src, u8 *dst, int len) |
101 | { |
102 | for (; len > 1; len -= 2) { |
103 | *(__be16 *)dst = cpu_to_be16p(p: src++); |
104 | dst += 2; |
105 | } |
106 | |
107 | if (len) |
108 | *dst = *src >> 8; |
109 | } |
110 | |
111 | static void highlander_i2c_command(struct highlander_i2c_dev *dev, |
112 | u8 command, int len) |
113 | { |
114 | unsigned int i; |
115 | u16 cmd = (command << 8) | command; |
116 | |
117 | for (i = 0; i < len; i += 2) { |
118 | if (len - i == 1) |
119 | cmd = command << 8; |
120 | iowrite16(cmd, dev->base + SMSADR + i); |
121 | dev_dbg(dev->dev, "command data[%x] 0x%04x\n" , i/2, cmd); |
122 | } |
123 | } |
124 | |
125 | static int highlander_i2c_wait_for_bbsy(struct highlander_i2c_dev *dev) |
126 | { |
127 | unsigned long timeout; |
128 | |
129 | timeout = jiffies + msecs_to_jiffies(m: iic_timeout); |
130 | while (ioread16(dev->base + SMCR) & SMCR_BBSY) { |
131 | if (time_after(jiffies, timeout)) { |
132 | dev_warn(dev->dev, "timeout waiting for bus ready\n" ); |
133 | return -ETIMEDOUT; |
134 | } |
135 | |
136 | msleep(msecs: 1); |
137 | } |
138 | |
139 | return 0; |
140 | } |
141 | |
142 | static int highlander_i2c_reset(struct highlander_i2c_dev *dev) |
143 | { |
144 | iowrite16(ioread16(dev->base + SMCR) | SMCR_RST, dev->base + SMCR); |
145 | return highlander_i2c_wait_for_bbsy(dev); |
146 | } |
147 | |
148 | static int highlander_i2c_wait_for_ack(struct highlander_i2c_dev *dev) |
149 | { |
150 | u16 tmp = ioread16(dev->base + SMCR); |
151 | |
152 | if ((tmp & (SMCR_IRIC | SMCR_ACKE)) == SMCR_ACKE) { |
153 | dev_warn(dev->dev, "ack abnormality\n" ); |
154 | return highlander_i2c_reset(dev); |
155 | } |
156 | |
157 | return 0; |
158 | } |
159 | |
160 | static irqreturn_t highlander_i2c_irq(int irq, void *dev_id) |
161 | { |
162 | struct highlander_i2c_dev *dev = dev_id; |
163 | |
164 | highlander_i2c_done(dev); |
165 | complete(&dev->cmd_complete); |
166 | |
167 | return IRQ_HANDLED; |
168 | } |
169 | |
170 | static void highlander_i2c_poll(struct highlander_i2c_dev *dev) |
171 | { |
172 | unsigned long timeout; |
173 | u16 smcr; |
174 | |
175 | timeout = jiffies + msecs_to_jiffies(m: iic_timeout); |
176 | for (;;) { |
177 | smcr = ioread16(dev->base + SMCR); |
178 | |
179 | /* |
180 | * Don't bother checking ACKE here, this and the reset |
181 | * are handled in highlander_i2c_wait_xfer_done() when |
182 | * waiting for the ACK. |
183 | */ |
184 | |
185 | if (smcr & SMCR_IRIC) |
186 | return; |
187 | if (time_after(jiffies, timeout)) |
188 | break; |
189 | |
190 | cpu_relax(); |
191 | cond_resched(); |
192 | } |
193 | |
194 | dev_err(dev->dev, "polling timed out\n" ); |
195 | } |
196 | |
197 | static inline int highlander_i2c_wait_xfer_done(struct highlander_i2c_dev *dev) |
198 | { |
199 | if (dev->irq) |
200 | wait_for_completion_timeout(x: &dev->cmd_complete, |
201 | timeout: msecs_to_jiffies(m: iic_timeout)); |
202 | else |
203 | /* busy looping, the IRQ of champions */ |
204 | highlander_i2c_poll(dev); |
205 | |
206 | return highlander_i2c_wait_for_ack(dev); |
207 | } |
208 | |
209 | static int highlander_i2c_read(struct highlander_i2c_dev *dev) |
210 | { |
211 | int i, cnt; |
212 | u16 data[16]; |
213 | |
214 | if (highlander_i2c_wait_for_bbsy(dev)) |
215 | return -EAGAIN; |
216 | |
217 | highlander_i2c_start(dev); |
218 | |
219 | if (highlander_i2c_wait_xfer_done(dev)) { |
220 | dev_err(dev->dev, "Arbitration loss\n" ); |
221 | return -EAGAIN; |
222 | } |
223 | |
224 | /* |
225 | * The R0P7780LC0011RL FPGA needs a significant delay between |
226 | * data read cycles, otherwise the transceiver gets confused and |
227 | * garbage is returned when the read is subsequently aborted. |
228 | * |
229 | * It is not sufficient to wait for BBSY. |
230 | * |
231 | * While this generally only applies to the older SH7780-based |
232 | * Highlanders, the same issue can be observed on SH7785 ones, |
233 | * albeit less frequently. SH7780-based Highlanders may need |
234 | * this to be as high as 1000 ms. |
235 | */ |
236 | if (iic_read_delay && time_before(jiffies, dev->last_read_time + |
237 | msecs_to_jiffies(iic_read_delay))) |
238 | msleep(msecs: jiffies_to_msecs(j: (dev->last_read_time + |
239 | msecs_to_jiffies(m: iic_read_delay)) - jiffies)); |
240 | |
241 | cnt = (dev->buf_len + 1) >> 1; |
242 | for (i = 0; i < cnt; i++) { |
243 | data[i] = ioread16(dev->base + SMTRDR + (i * sizeof(u16))); |
244 | dev_dbg(dev->dev, "read data[%x] 0x%04x\n" , i, data[i]); |
245 | } |
246 | |
247 | smbus_read_data(src: data, dst: dev->buf, len: dev->buf_len); |
248 | |
249 | dev->last_read_time = jiffies; |
250 | |
251 | return 0; |
252 | } |
253 | |
254 | static int highlander_i2c_write(struct highlander_i2c_dev *dev) |
255 | { |
256 | int i, cnt; |
257 | u16 data[16]; |
258 | |
259 | smbus_write_data(src: dev->buf, dst: data, len: dev->buf_len); |
260 | |
261 | cnt = (dev->buf_len + 1) >> 1; |
262 | for (i = 0; i < cnt; i++) { |
263 | iowrite16(data[i], dev->base + SMTRDR + (i * sizeof(u16))); |
264 | dev_dbg(dev->dev, "write data[%x] 0x%04x\n" , i, data[i]); |
265 | } |
266 | |
267 | if (highlander_i2c_wait_for_bbsy(dev)) |
268 | return -EAGAIN; |
269 | |
270 | highlander_i2c_start(dev); |
271 | |
272 | return highlander_i2c_wait_xfer_done(dev); |
273 | } |
274 | |
275 | static int highlander_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, |
276 | unsigned short flags, char read_write, |
277 | u8 command, int size, |
278 | union i2c_smbus_data *data) |
279 | { |
280 | struct highlander_i2c_dev *dev = i2c_get_adapdata(adap); |
281 | u16 tmp; |
282 | |
283 | init_completion(x: &dev->cmd_complete); |
284 | |
285 | dev_dbg(dev->dev, "addr %04x, command %02x, read_write %d, size %d\n" , |
286 | addr, command, read_write, size); |
287 | |
288 | /* |
289 | * Set up the buffer and transfer size |
290 | */ |
291 | switch (size) { |
292 | case I2C_SMBUS_BYTE_DATA: |
293 | dev->buf = &data->byte; |
294 | dev->buf_len = 1; |
295 | break; |
296 | case I2C_SMBUS_I2C_BLOCK_DATA: |
297 | dev->buf = &data->block[1]; |
298 | dev->buf_len = data->block[0]; |
299 | break; |
300 | default: |
301 | dev_err(dev->dev, "unsupported command %d\n" , size); |
302 | return -EINVAL; |
303 | } |
304 | |
305 | /* |
306 | * Encode the mode setting |
307 | */ |
308 | tmp = ioread16(dev->base + SMMR); |
309 | tmp &= ~(SMMR_MODE0 | SMMR_MODE1); |
310 | |
311 | switch (dev->buf_len) { |
312 | case 1: |
313 | /* default */ |
314 | break; |
315 | case 8: |
316 | tmp |= SMMR_MODE0; |
317 | break; |
318 | case 16: |
319 | tmp |= SMMR_MODE1; |
320 | break; |
321 | case 32: |
322 | tmp |= (SMMR_MODE0 | SMMR_MODE1); |
323 | break; |
324 | default: |
325 | dev_err(dev->dev, "unsupported xfer size %zu\n" , dev->buf_len); |
326 | return -EINVAL; |
327 | } |
328 | |
329 | iowrite16(tmp, dev->base + SMMR); |
330 | |
331 | /* Ensure we're in a sane state */ |
332 | highlander_i2c_done(dev); |
333 | |
334 | /* Set slave address */ |
335 | iowrite16((addr << 1) | read_write, dev->base + SMSMADR); |
336 | |
337 | highlander_i2c_command(dev, command, len: dev->buf_len); |
338 | |
339 | if (read_write == I2C_SMBUS_READ) |
340 | return highlander_i2c_read(dev); |
341 | else |
342 | return highlander_i2c_write(dev); |
343 | } |
344 | |
345 | static u32 highlander_i2c_func(struct i2c_adapter *adapter) |
346 | { |
347 | return I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK; |
348 | } |
349 | |
350 | static const struct i2c_algorithm highlander_i2c_algo = { |
351 | .smbus_xfer = highlander_i2c_smbus_xfer, |
352 | .functionality = highlander_i2c_func, |
353 | }; |
354 | |
355 | static int highlander_i2c_probe(struct platform_device *pdev) |
356 | { |
357 | struct highlander_i2c_dev *dev; |
358 | struct i2c_adapter *adap; |
359 | struct resource *res; |
360 | int ret; |
361 | |
362 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
363 | if (unlikely(!res)) { |
364 | dev_err(&pdev->dev, "no mem resource\n" ); |
365 | return -ENODEV; |
366 | } |
367 | |
368 | dev = kzalloc(size: sizeof(struct highlander_i2c_dev), GFP_KERNEL); |
369 | if (unlikely(!dev)) |
370 | return -ENOMEM; |
371 | |
372 | dev->base = ioremap(offset: res->start, size: resource_size(res)); |
373 | if (unlikely(!dev->base)) { |
374 | ret = -ENXIO; |
375 | goto err; |
376 | } |
377 | |
378 | dev->dev = &pdev->dev; |
379 | platform_set_drvdata(pdev, data: dev); |
380 | |
381 | dev->irq = platform_get_irq(pdev, 0); |
382 | if (dev->irq < 0 || iic_force_poll) |
383 | dev->irq = 0; |
384 | |
385 | if (dev->irq) { |
386 | ret = request_irq(irq: dev->irq, handler: highlander_i2c_irq, flags: 0, |
387 | name: pdev->name, dev); |
388 | if (unlikely(ret)) |
389 | goto err_unmap; |
390 | |
391 | highlander_i2c_irq_enable(dev); |
392 | } else { |
393 | dev_notice(&pdev->dev, "no IRQ, using polling mode\n" ); |
394 | highlander_i2c_irq_disable(dev); |
395 | } |
396 | |
397 | dev->last_read_time = jiffies; /* initial read jiffies */ |
398 | |
399 | highlander_i2c_setup(dev); |
400 | |
401 | adap = &dev->adapter; |
402 | i2c_set_adapdata(adap, data: dev); |
403 | adap->owner = THIS_MODULE; |
404 | adap->class = I2C_CLASS_HWMON; |
405 | strscpy(p: adap->name, q: "HL FPGA I2C adapter" , size: sizeof(adap->name)); |
406 | adap->algo = &highlander_i2c_algo; |
407 | adap->dev.parent = &pdev->dev; |
408 | adap->nr = pdev->id; |
409 | |
410 | /* |
411 | * Reset the adapter |
412 | */ |
413 | ret = highlander_i2c_reset(dev); |
414 | if (unlikely(ret)) { |
415 | dev_err(&pdev->dev, "controller didn't come up\n" ); |
416 | goto err_free_irq; |
417 | } |
418 | |
419 | ret = i2c_add_numbered_adapter(adap); |
420 | if (unlikely(ret)) { |
421 | dev_err(&pdev->dev, "failure adding adapter\n" ); |
422 | goto err_free_irq; |
423 | } |
424 | |
425 | return 0; |
426 | |
427 | err_free_irq: |
428 | if (dev->irq) |
429 | free_irq(dev->irq, dev); |
430 | err_unmap: |
431 | iounmap(addr: dev->base); |
432 | err: |
433 | kfree(objp: dev); |
434 | |
435 | return ret; |
436 | } |
437 | |
438 | static void highlander_i2c_remove(struct platform_device *pdev) |
439 | { |
440 | struct highlander_i2c_dev *dev = platform_get_drvdata(pdev); |
441 | |
442 | i2c_del_adapter(adap: &dev->adapter); |
443 | |
444 | if (dev->irq) |
445 | free_irq(dev->irq, dev); |
446 | |
447 | iounmap(addr: dev->base); |
448 | kfree(objp: dev); |
449 | } |
450 | |
451 | static struct platform_driver highlander_i2c_driver = { |
452 | .driver = { |
453 | .name = "i2c-highlander" , |
454 | }, |
455 | |
456 | .probe = highlander_i2c_probe, |
457 | .remove_new = highlander_i2c_remove, |
458 | }; |
459 | |
460 | module_platform_driver(highlander_i2c_driver); |
461 | |
462 | MODULE_AUTHOR("Paul Mundt" ); |
463 | MODULE_DESCRIPTION("Renesas Highlander FPGA I2C/SMBus adapter" ); |
464 | MODULE_LICENSE("GPL v2" ); |
465 | |
466 | module_param(iic_force_poll, bool, 0); |
467 | module_param(iic_force_normal, bool, 0); |
468 | module_param(iic_timeout, int, 0); |
469 | module_param(iic_read_delay, int, 0); |
470 | |
471 | MODULE_PARM_DESC(iic_force_poll, "Force polling mode" ); |
472 | MODULE_PARM_DESC(iic_force_normal, |
473 | "Force normal mode (100 kHz), default is fast mode (400 kHz)" ); |
474 | MODULE_PARM_DESC(iic_timeout, "Set timeout value in msecs (default 1000 ms)" ); |
475 | MODULE_PARM_DESC(iic_read_delay, |
476 | "Delay between data read cycles (default 0 ms)" ); |
477 | |