1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * I2C adapter for the IMG Serial Control Bus (SCB) IP block. |
4 | * |
5 | * Copyright (C) 2009, 2010, 2012, 2014 Imagination Technologies Ltd. |
6 | * |
7 | * There are three ways that this I2C controller can be driven: |
8 | * |
9 | * - Raw control of the SDA and SCK signals. |
10 | * |
11 | * This corresponds to MODE_RAW, which takes control of the signals |
12 | * directly for a certain number of clock cycles (the INT_TIMING |
13 | * interrupt can be used for timing). |
14 | * |
15 | * - Atomic commands. A low level I2C symbol (such as generate |
16 | * start/stop/ack/nack bit, generate byte, receive byte, and receive |
17 | * ACK) is given to the hardware, with detection of completion by bits |
18 | * in the LINESTAT register. |
19 | * |
20 | * This mode of operation is used by MODE_ATOMIC, which uses an I2C |
21 | * state machine in the interrupt handler to compose/react to I2C |
22 | * transactions using atomic mode commands, and also by MODE_SEQUENCE, |
23 | * which emits a simple fixed sequence of atomic mode commands. |
24 | * |
25 | * Due to software control, the use of atomic commands usually results |
26 | * in suboptimal use of the bus, with gaps between the I2C symbols while |
27 | * the driver decides what to do next. |
28 | * |
29 | * - Automatic mode. A bus address, and whether to read/write is |
30 | * specified, and the hardware takes care of the I2C state machine, |
31 | * using a FIFO to send/receive bytes of data to an I2C slave. The |
32 | * driver just has to keep the FIFO drained or filled in response to the |
33 | * appropriate FIFO interrupts. |
34 | * |
35 | * This corresponds to MODE_AUTOMATIC, which manages the FIFOs and deals |
36 | * with control of repeated start bits between I2C messages. |
37 | * |
38 | * Use of automatic mode and the FIFO can make much more efficient use |
39 | * of the bus compared to individual atomic commands, with potentially |
40 | * no wasted time between I2C symbols or I2C messages. |
41 | * |
42 | * In most cases MODE_AUTOMATIC is used, however if any of the messages in |
43 | * a transaction are zero byte writes (e.g. used by i2cdetect for probing |
44 | * the bus), MODE_ATOMIC must be used since automatic mode is normally |
45 | * started by the writing of data into the FIFO. |
46 | * |
47 | * The other modes are used in specific circumstances where MODE_ATOMIC and |
48 | * MODE_AUTOMATIC aren't appropriate. MODE_RAW is used to implement a bus |
49 | * recovery routine. MODE_SEQUENCE is used to reset the bus and make sure |
50 | * it is in a sane state. |
51 | * |
52 | * Notice that the driver implements a timer-based timeout mechanism. |
53 | * The reason for this mechanism is to reduce the number of interrupts |
54 | * received in automatic mode. |
55 | * |
56 | * The driver would get a slave event and transaction done interrupts for |
57 | * each atomic mode command that gets completed. However, these events are |
58 | * not needed in automatic mode, becase those atomic mode commands are |
59 | * managed automatically by the hardware. |
60 | * |
61 | * In practice, normal I2C transactions will be complete well before you |
62 | * get the timer interrupt, as the timer is re-scheduled during FIFO |
63 | * maintenance and disabled after the transaction is complete. |
64 | * |
65 | * In this way normal automatic mode operation isn't impacted by |
66 | * unnecessary interrupts, but the exceptional abort condition can still be |
67 | * detected (with a slight delay). |
68 | */ |
69 | |
70 | #include <linux/bitops.h> |
71 | #include <linux/clk.h> |
72 | #include <linux/completion.h> |
73 | #include <linux/err.h> |
74 | #include <linux/i2c.h> |
75 | #include <linux/init.h> |
76 | #include <linux/interrupt.h> |
77 | #include <linux/io.h> |
78 | #include <linux/kernel.h> |
79 | #include <linux/module.h> |
80 | #include <linux/of_platform.h> |
81 | #include <linux/platform_device.h> |
82 | #include <linux/pm_runtime.h> |
83 | #include <linux/slab.h> |
84 | #include <linux/timer.h> |
85 | |
86 | /* Register offsets */ |
87 | |
88 | #define SCB_STATUS_REG 0x00 |
89 | #define SCB_OVERRIDE_REG 0x04 |
90 | #define SCB_READ_ADDR_REG 0x08 |
91 | #define SCB_READ_COUNT_REG 0x0c |
92 | #define SCB_WRITE_ADDR_REG 0x10 |
93 | #define SCB_READ_DATA_REG 0x14 |
94 | #define SCB_WRITE_DATA_REG 0x18 |
95 | #define SCB_FIFO_STATUS_REG 0x1c |
96 | #define SCB_CONTROL_SOFT_RESET 0x1f |
97 | #define SCB_CLK_SET_REG 0x3c |
98 | #define SCB_INT_STATUS_REG 0x40 |
99 | #define SCB_INT_CLEAR_REG 0x44 |
100 | #define SCB_INT_MASK_REG 0x48 |
101 | #define SCB_CONTROL_REG 0x4c |
102 | #define SCB_TIME_TPL_REG 0x50 |
103 | #define SCB_TIME_TPH_REG 0x54 |
104 | #define SCB_TIME_TP2S_REG 0x58 |
105 | #define SCB_TIME_TBI_REG 0x60 |
106 | #define SCB_TIME_TSL_REG 0x64 |
107 | #define SCB_TIME_TDL_REG 0x68 |
108 | #define SCB_TIME_TSDL_REG 0x6c |
109 | #define SCB_TIME_TSDH_REG 0x70 |
110 | #define SCB_READ_XADDR_REG 0x74 |
111 | #define SCB_WRITE_XADDR_REG 0x78 |
112 | #define SCB_WRITE_COUNT_REG 0x7c |
113 | #define SCB_CORE_REV_REG 0x80 |
114 | #define SCB_TIME_TCKH_REG 0x84 |
115 | #define SCB_TIME_TCKL_REG 0x88 |
116 | #define SCB_FIFO_FLUSH_REG 0x8c |
117 | #define SCB_READ_FIFO_REG 0x94 |
118 | #define SCB_CLEAR_REG 0x98 |
119 | |
120 | /* SCB_CONTROL_REG bits */ |
121 | |
122 | #define SCB_CONTROL_CLK_ENABLE 0x1e0 |
123 | #define SCB_CONTROL_TRANSACTION_HALT 0x200 |
124 | |
125 | #define FIFO_READ_FULL BIT(0) |
126 | #define FIFO_READ_EMPTY BIT(1) |
127 | #define FIFO_WRITE_FULL BIT(2) |
128 | #define FIFO_WRITE_EMPTY BIT(3) |
129 | |
130 | /* SCB_CLK_SET_REG bits */ |
131 | #define SCB_FILT_DISABLE BIT(31) |
132 | #define SCB_FILT_BYPASS BIT(30) |
133 | #define SCB_FILT_INC_MASK 0x7f |
134 | #define SCB_FILT_INC_SHIFT 16 |
135 | #define SCB_INC_MASK 0x7f |
136 | #define SCB_INC_SHIFT 8 |
137 | |
138 | /* SCB_INT_*_REG bits */ |
139 | |
140 | #define INT_BUS_INACTIVE BIT(0) |
141 | #define INT_UNEXPECTED_START BIT(1) |
142 | #define INT_SCLK_LOW_TIMEOUT BIT(2) |
143 | #define INT_SDAT_LOW_TIMEOUT BIT(3) |
144 | #define INT_WRITE_ACK_ERR BIT(4) |
145 | #define INT_ADDR_ACK_ERR BIT(5) |
146 | #define INT_FIFO_FULL BIT(9) |
147 | #define INT_FIFO_FILLING BIT(10) |
148 | #define INT_FIFO_EMPTY BIT(11) |
149 | #define INT_FIFO_EMPTYING BIT(12) |
150 | #define INT_TRANSACTION_DONE BIT(15) |
151 | #define INT_SLAVE_EVENT BIT(16) |
152 | #define INT_MASTER_HALTED BIT(17) |
153 | #define INT_TIMING BIT(18) |
154 | #define INT_STOP_DETECTED BIT(19) |
155 | |
156 | #define INT_FIFO_FULL_FILLING (INT_FIFO_FULL | INT_FIFO_FILLING) |
157 | |
158 | /* Level interrupts need clearing after handling instead of before */ |
159 | #define INT_LEVEL 0x01e00 |
160 | |
161 | /* Don't allow any interrupts while the clock may be off */ |
162 | #define INT_ENABLE_MASK_INACTIVE 0x00000 |
163 | |
164 | /* Interrupt masks for the different driver modes */ |
165 | |
166 | #define INT_ENABLE_MASK_RAW INT_TIMING |
167 | |
168 | #define INT_ENABLE_MASK_ATOMIC (INT_TRANSACTION_DONE | \ |
169 | INT_SLAVE_EVENT | \ |
170 | INT_ADDR_ACK_ERR | \ |
171 | INT_WRITE_ACK_ERR) |
172 | |
173 | #define INT_ENABLE_MASK_AUTOMATIC (INT_SCLK_LOW_TIMEOUT | \ |
174 | INT_ADDR_ACK_ERR | \ |
175 | INT_WRITE_ACK_ERR | \ |
176 | INT_FIFO_FULL | \ |
177 | INT_FIFO_FILLING | \ |
178 | INT_FIFO_EMPTY | \ |
179 | INT_MASTER_HALTED | \ |
180 | INT_STOP_DETECTED) |
181 | |
182 | #define INT_ENABLE_MASK_WAITSTOP (INT_SLAVE_EVENT | \ |
183 | INT_ADDR_ACK_ERR | \ |
184 | INT_WRITE_ACK_ERR) |
185 | |
186 | /* SCB_STATUS_REG fields */ |
187 | |
188 | #define LINESTAT_SCLK_LINE_STATUS BIT(0) |
189 | #define LINESTAT_SCLK_EN BIT(1) |
190 | #define LINESTAT_SDAT_LINE_STATUS BIT(2) |
191 | #define LINESTAT_SDAT_EN BIT(3) |
192 | #define LINESTAT_DET_START_STATUS BIT(4) |
193 | #define LINESTAT_DET_STOP_STATUS BIT(5) |
194 | #define LINESTAT_DET_ACK_STATUS BIT(6) |
195 | #define LINESTAT_DET_NACK_STATUS BIT(7) |
196 | #define LINESTAT_BUS_IDLE BIT(8) |
197 | #define LINESTAT_T_DONE_STATUS BIT(9) |
198 | #define LINESTAT_SCLK_OUT_STATUS BIT(10) |
199 | #define LINESTAT_SDAT_OUT_STATUS BIT(11) |
200 | #define LINESTAT_GEN_LINE_MASK_STATUS BIT(12) |
201 | #define LINESTAT_START_BIT_DET BIT(13) |
202 | #define LINESTAT_STOP_BIT_DET BIT(14) |
203 | #define LINESTAT_ACK_DET BIT(15) |
204 | #define LINESTAT_NACK_DET BIT(16) |
205 | #define LINESTAT_INPUT_HELD_V BIT(17) |
206 | #define LINESTAT_ABORT_DET BIT(18) |
207 | #define LINESTAT_ACK_OR_NACK_DET (LINESTAT_ACK_DET | LINESTAT_NACK_DET) |
208 | #define LINESTAT_INPUT_DATA 0xff000000 |
209 | #define LINESTAT_INPUT_DATA_SHIFT 24 |
210 | |
211 | #define LINESTAT_CLEAR_SHIFT 13 |
212 | #define LINESTAT_LATCHED (0x3f << LINESTAT_CLEAR_SHIFT) |
213 | |
214 | /* SCB_OVERRIDE_REG fields */ |
215 | |
216 | #define OVERRIDE_SCLK_OVR BIT(0) |
217 | #define OVERRIDE_SCLKEN_OVR BIT(1) |
218 | #define OVERRIDE_SDAT_OVR BIT(2) |
219 | #define OVERRIDE_SDATEN_OVR BIT(3) |
220 | #define OVERRIDE_MASTER BIT(9) |
221 | #define OVERRIDE_LINE_OVR_EN BIT(10) |
222 | #define OVERRIDE_DIRECT BIT(11) |
223 | #define OVERRIDE_CMD_SHIFT 4 |
224 | #define OVERRIDE_CMD_MASK 0x1f |
225 | #define OVERRIDE_DATA_SHIFT 24 |
226 | |
227 | #define OVERRIDE_SCLK_DOWN (OVERRIDE_LINE_OVR_EN | \ |
228 | OVERRIDE_SCLKEN_OVR) |
229 | #define OVERRIDE_SCLK_UP (OVERRIDE_LINE_OVR_EN | \ |
230 | OVERRIDE_SCLKEN_OVR | \ |
231 | OVERRIDE_SCLK_OVR) |
232 | #define OVERRIDE_SDAT_DOWN (OVERRIDE_LINE_OVR_EN | \ |
233 | OVERRIDE_SDATEN_OVR) |
234 | #define OVERRIDE_SDAT_UP (OVERRIDE_LINE_OVR_EN | \ |
235 | OVERRIDE_SDATEN_OVR | \ |
236 | OVERRIDE_SDAT_OVR) |
237 | |
238 | /* OVERRIDE_CMD values */ |
239 | |
240 | #define CMD_PAUSE 0x00 |
241 | #define CMD_GEN_DATA 0x01 |
242 | #define CMD_GEN_START 0x02 |
243 | #define CMD_GEN_STOP 0x03 |
244 | #define CMD_GEN_ACK 0x04 |
245 | #define CMD_GEN_NACK 0x05 |
246 | #define CMD_RET_DATA 0x08 |
247 | #define CMD_RET_ACK 0x09 |
248 | |
249 | /* Fixed timing values */ |
250 | |
251 | #define TIMEOUT_TBI 0x0 |
252 | #define TIMEOUT_TSL 0xffff |
253 | #define TIMEOUT_TDL 0x0 |
254 | |
255 | /* Transaction timeout */ |
256 | |
257 | #define IMG_I2C_TIMEOUT (msecs_to_jiffies(1000)) |
258 | |
259 | /* |
260 | * Worst incs are 1 (inaccurate) and 16*256 (irregular). |
261 | * So a sensible inc is the logarithmic mean: 64 (2^6), which is |
262 | * in the middle of the valid range (0-127). |
263 | */ |
264 | #define SCB_OPT_INC 64 |
265 | |
266 | /* Setup the clock enable filtering for 25 ns */ |
267 | #define SCB_FILT_GLITCH 25 |
268 | |
269 | /* |
270 | * Bits to return from interrupt handler functions for different modes. |
271 | * This delays completion until we've finished with the registers, so that the |
272 | * function waiting for completion can safely disable the clock to save power. |
273 | */ |
274 | #define ISR_COMPLETE_M BIT(31) |
275 | #define ISR_FATAL_M BIT(30) |
276 | #define ISR_WAITSTOP BIT(29) |
277 | #define ISR_STATUS_M 0x0000ffff /* contains +ve errno */ |
278 | #define ISR_COMPLETE(err) (ISR_COMPLETE_M | (ISR_STATUS_M & (err))) |
279 | #define ISR_FATAL(err) (ISR_COMPLETE(err) | ISR_FATAL_M) |
280 | |
281 | #define IMG_I2C_PM_TIMEOUT 1000 /* ms */ |
282 | |
283 | enum img_i2c_mode { |
284 | MODE_INACTIVE, |
285 | MODE_RAW, |
286 | MODE_ATOMIC, |
287 | MODE_AUTOMATIC, |
288 | MODE_SEQUENCE, |
289 | MODE_FATAL, |
290 | MODE_WAITSTOP, |
291 | MODE_SUSPEND, |
292 | }; |
293 | |
294 | /* Timing parameters for i2c modes (in ns) */ |
295 | struct img_i2c_timings { |
296 | const char *name; |
297 | unsigned int max_bitrate; |
298 | unsigned int tckh, tckl, tsdh, tsdl; |
299 | unsigned int tp2s, tpl, tph; |
300 | }; |
301 | |
302 | /* The timings array must be ordered from slower to faster */ |
303 | static struct img_i2c_timings timings[] = { |
304 | /* Standard mode */ |
305 | { |
306 | .name = "standard" , |
307 | .max_bitrate = I2C_MAX_STANDARD_MODE_FREQ, |
308 | .tckh = 4000, |
309 | .tckl = 4700, |
310 | .tsdh = 4700, |
311 | .tsdl = 8700, |
312 | .tp2s = 4700, |
313 | .tpl = 4700, |
314 | .tph = 4000, |
315 | }, |
316 | /* Fast mode */ |
317 | { |
318 | .name = "fast" , |
319 | .max_bitrate = I2C_MAX_FAST_MODE_FREQ, |
320 | .tckh = 600, |
321 | .tckl = 1300, |
322 | .tsdh = 600, |
323 | .tsdl = 1200, |
324 | .tp2s = 1300, |
325 | .tpl = 600, |
326 | .tph = 600, |
327 | }, |
328 | }; |
329 | |
330 | /* Reset dance */ |
331 | static u8 img_i2c_reset_seq[] = { CMD_GEN_START, |
332 | CMD_GEN_DATA, 0xff, |
333 | CMD_RET_ACK, |
334 | CMD_GEN_START, |
335 | CMD_GEN_STOP, |
336 | 0 }; |
337 | /* Just issue a stop (after an abort condition) */ |
338 | static u8 img_i2c_stop_seq[] = { CMD_GEN_STOP, |
339 | 0 }; |
340 | |
341 | /* We're interested in different interrupts depending on the mode */ |
342 | static unsigned int img_i2c_int_enable_by_mode[] = { |
343 | [MODE_INACTIVE] = INT_ENABLE_MASK_INACTIVE, |
344 | [MODE_RAW] = INT_ENABLE_MASK_RAW, |
345 | [MODE_ATOMIC] = INT_ENABLE_MASK_ATOMIC, |
346 | [MODE_AUTOMATIC] = INT_ENABLE_MASK_AUTOMATIC, |
347 | [MODE_SEQUENCE] = INT_ENABLE_MASK_ATOMIC, |
348 | [MODE_FATAL] = 0, |
349 | [MODE_WAITSTOP] = INT_ENABLE_MASK_WAITSTOP, |
350 | [MODE_SUSPEND] = 0, |
351 | }; |
352 | |
353 | /* Atomic command names */ |
354 | static const char * const img_i2c_atomic_cmd_names[] = { |
355 | [CMD_PAUSE] = "PAUSE" , |
356 | [CMD_GEN_DATA] = "GEN_DATA" , |
357 | [CMD_GEN_START] = "GEN_START" , |
358 | [CMD_GEN_STOP] = "GEN_STOP" , |
359 | [CMD_GEN_ACK] = "GEN_ACK" , |
360 | [CMD_GEN_NACK] = "GEN_NACK" , |
361 | [CMD_RET_DATA] = "RET_DATA" , |
362 | [CMD_RET_ACK] = "RET_ACK" , |
363 | }; |
364 | |
365 | struct img_i2c { |
366 | struct i2c_adapter adap; |
367 | |
368 | void __iomem *base; |
369 | |
370 | /* |
371 | * The scb core clock is used to get the input frequency, and to disable |
372 | * it after every set of transactions to save some power. |
373 | */ |
374 | struct clk *scb_clk, *sys_clk; |
375 | unsigned int bitrate; |
376 | bool need_wr_rd_fence; |
377 | |
378 | /* state */ |
379 | struct completion msg_complete; |
380 | spinlock_t lock; /* lock before doing anything with the state */ |
381 | struct i2c_msg msg; |
382 | |
383 | /* After the last transaction, wait for a stop bit */ |
384 | bool last_msg; |
385 | int msg_status; |
386 | |
387 | enum img_i2c_mode mode; |
388 | u32 int_enable; /* depends on mode */ |
389 | u32 line_status; /* line status over command */ |
390 | |
391 | /* |
392 | * To avoid slave event interrupts in automatic mode, use a timer to |
393 | * poll the abort condition if we don't get an interrupt for too long. |
394 | */ |
395 | struct timer_list check_timer; |
396 | bool t_halt; |
397 | |
398 | /* atomic mode state */ |
399 | bool at_t_done; |
400 | bool at_slave_event; |
401 | int at_cur_cmd; |
402 | u8 at_cur_data; |
403 | |
404 | /* Sequence: either reset or stop. See img_i2c_sequence. */ |
405 | u8 *seq; |
406 | |
407 | /* raw mode */ |
408 | unsigned int raw_timeout; |
409 | }; |
410 | |
411 | static int img_i2c_runtime_suspend(struct device *dev); |
412 | static int img_i2c_runtime_resume(struct device *dev); |
413 | |
414 | static void img_i2c_writel(struct img_i2c *i2c, u32 offset, u32 value) |
415 | { |
416 | writel(val: value, addr: i2c->base + offset); |
417 | } |
418 | |
419 | static u32 img_i2c_readl(struct img_i2c *i2c, u32 offset) |
420 | { |
421 | return readl(addr: i2c->base + offset); |
422 | } |
423 | |
424 | /* |
425 | * The code to read from the master read fifo, and write to the master |
426 | * write fifo, checks a bit in an SCB register before every byte to |
427 | * ensure that the fifo is not full (write fifo) or empty (read fifo). |
428 | * Due to clock domain crossing inside the SCB block the updated value |
429 | * of this bit is only visible after 2 cycles. |
430 | * |
431 | * The scb_wr_rd_fence() function does 2 dummy writes (to the read-only |
432 | * revision register), and it's called after reading from or writing to the |
433 | * fifos to ensure that subsequent reads of the fifo status bits do not read |
434 | * stale values. |
435 | */ |
436 | static void img_i2c_wr_rd_fence(struct img_i2c *i2c) |
437 | { |
438 | if (i2c->need_wr_rd_fence) { |
439 | img_i2c_writel(i2c, SCB_CORE_REV_REG, value: 0); |
440 | img_i2c_writel(i2c, SCB_CORE_REV_REG, value: 0); |
441 | } |
442 | } |
443 | |
444 | static void img_i2c_switch_mode(struct img_i2c *i2c, enum img_i2c_mode mode) |
445 | { |
446 | i2c->mode = mode; |
447 | i2c->int_enable = img_i2c_int_enable_by_mode[mode]; |
448 | i2c->line_status = 0; |
449 | } |
450 | |
451 | static void img_i2c_raw_op(struct img_i2c *i2c) |
452 | { |
453 | i2c->raw_timeout = 0; |
454 | img_i2c_writel(i2c, SCB_OVERRIDE_REG, |
455 | OVERRIDE_SCLKEN_OVR | |
456 | OVERRIDE_SDATEN_OVR | |
457 | OVERRIDE_MASTER | |
458 | OVERRIDE_LINE_OVR_EN | |
459 | OVERRIDE_DIRECT | |
460 | ((i2c->at_cur_cmd & OVERRIDE_CMD_MASK) << OVERRIDE_CMD_SHIFT) | |
461 | (i2c->at_cur_data << OVERRIDE_DATA_SHIFT)); |
462 | } |
463 | |
464 | static const char *img_i2c_atomic_op_name(unsigned int cmd) |
465 | { |
466 | if (unlikely(cmd >= ARRAY_SIZE(img_i2c_atomic_cmd_names))) |
467 | return "UNKNOWN" ; |
468 | return img_i2c_atomic_cmd_names[cmd]; |
469 | } |
470 | |
471 | /* Send a single atomic mode command to the hardware */ |
472 | static void img_i2c_atomic_op(struct img_i2c *i2c, int cmd, u8 data) |
473 | { |
474 | i2c->at_cur_cmd = cmd; |
475 | i2c->at_cur_data = data; |
476 | |
477 | /* work around lack of data setup time when generating data */ |
478 | if (cmd == CMD_GEN_DATA && i2c->mode == MODE_ATOMIC) { |
479 | u32 line_status = img_i2c_readl(i2c, SCB_STATUS_REG); |
480 | |
481 | if (line_status & LINESTAT_SDAT_LINE_STATUS && !(data & 0x80)) { |
482 | /* hold the data line down for a moment */ |
483 | img_i2c_switch_mode(i2c, mode: MODE_RAW); |
484 | img_i2c_raw_op(i2c); |
485 | return; |
486 | } |
487 | } |
488 | |
489 | dev_dbg(i2c->adap.dev.parent, |
490 | "atomic cmd=%s (%d) data=%#x\n" , |
491 | img_i2c_atomic_op_name(cmd), cmd, data); |
492 | i2c->at_t_done = (cmd == CMD_RET_DATA || cmd == CMD_RET_ACK); |
493 | i2c->at_slave_event = false; |
494 | i2c->line_status = 0; |
495 | |
496 | img_i2c_writel(i2c, SCB_OVERRIDE_REG, |
497 | value: ((cmd & OVERRIDE_CMD_MASK) << OVERRIDE_CMD_SHIFT) | |
498 | OVERRIDE_MASTER | |
499 | OVERRIDE_DIRECT | |
500 | (data << OVERRIDE_DATA_SHIFT)); |
501 | } |
502 | |
503 | /* Start a transaction in atomic mode */ |
504 | static void img_i2c_atomic_start(struct img_i2c *i2c) |
505 | { |
506 | img_i2c_switch_mode(i2c, mode: MODE_ATOMIC); |
507 | img_i2c_writel(i2c, SCB_INT_MASK_REG, value: i2c->int_enable); |
508 | img_i2c_atomic_op(i2c, CMD_GEN_START, data: 0x00); |
509 | } |
510 | |
511 | static void img_i2c_soft_reset(struct img_i2c *i2c) |
512 | { |
513 | i2c->t_halt = false; |
514 | img_i2c_writel(i2c, SCB_CONTROL_REG, value: 0); |
515 | img_i2c_writel(i2c, SCB_CONTROL_REG, |
516 | SCB_CONTROL_CLK_ENABLE | SCB_CONTROL_SOFT_RESET); |
517 | } |
518 | |
519 | /* |
520 | * Enable or release transaction halt for control of repeated starts. |
521 | * In version 3.3 of the IP when transaction halt is set, an interrupt |
522 | * will be generated after each byte of a transfer instead of after |
523 | * every transfer but before the stop bit. |
524 | * Due to this behaviour we have to be careful that every time we |
525 | * release the transaction halt we have to re-enable it straight away |
526 | * so that we only process a single byte, not doing so will result in |
527 | * all remaining bytes been processed and a stop bit being issued, |
528 | * which will prevent us having a repeated start. |
529 | */ |
530 | static void img_i2c_transaction_halt(struct img_i2c *i2c, bool t_halt) |
531 | { |
532 | u32 val; |
533 | |
534 | if (i2c->t_halt == t_halt) |
535 | return; |
536 | i2c->t_halt = t_halt; |
537 | val = img_i2c_readl(i2c, SCB_CONTROL_REG); |
538 | if (t_halt) |
539 | val |= SCB_CONTROL_TRANSACTION_HALT; |
540 | else |
541 | val &= ~SCB_CONTROL_TRANSACTION_HALT; |
542 | img_i2c_writel(i2c, SCB_CONTROL_REG, value: val); |
543 | } |
544 | |
545 | /* Drain data from the FIFO into the buffer (automatic mode) */ |
546 | static void img_i2c_read_fifo(struct img_i2c *i2c) |
547 | { |
548 | while (i2c->msg.len) { |
549 | u32 fifo_status; |
550 | u8 data; |
551 | |
552 | img_i2c_wr_rd_fence(i2c); |
553 | fifo_status = img_i2c_readl(i2c, SCB_FIFO_STATUS_REG); |
554 | if (fifo_status & FIFO_READ_EMPTY) |
555 | break; |
556 | |
557 | data = img_i2c_readl(i2c, SCB_READ_DATA_REG); |
558 | *i2c->msg.buf = data; |
559 | |
560 | img_i2c_writel(i2c, SCB_READ_FIFO_REG, value: 0xff); |
561 | i2c->msg.len--; |
562 | i2c->msg.buf++; |
563 | } |
564 | } |
565 | |
566 | /* Fill the FIFO with data from the buffer (automatic mode) */ |
567 | static void img_i2c_write_fifo(struct img_i2c *i2c) |
568 | { |
569 | while (i2c->msg.len) { |
570 | u32 fifo_status; |
571 | |
572 | img_i2c_wr_rd_fence(i2c); |
573 | fifo_status = img_i2c_readl(i2c, SCB_FIFO_STATUS_REG); |
574 | if (fifo_status & FIFO_WRITE_FULL) |
575 | break; |
576 | |
577 | img_i2c_writel(i2c, SCB_WRITE_DATA_REG, value: *i2c->msg.buf); |
578 | i2c->msg.len--; |
579 | i2c->msg.buf++; |
580 | } |
581 | |
582 | /* Disable fifo emptying interrupt if nothing more to write */ |
583 | if (!i2c->msg.len) |
584 | i2c->int_enable &= ~INT_FIFO_EMPTYING; |
585 | } |
586 | |
587 | /* Start a read transaction in automatic mode */ |
588 | static void img_i2c_read(struct img_i2c *i2c) |
589 | { |
590 | img_i2c_switch_mode(i2c, mode: MODE_AUTOMATIC); |
591 | if (!i2c->last_msg) |
592 | i2c->int_enable |= INT_SLAVE_EVENT; |
593 | |
594 | img_i2c_writel(i2c, SCB_INT_MASK_REG, value: i2c->int_enable); |
595 | img_i2c_writel(i2c, SCB_READ_ADDR_REG, value: i2c->msg.addr); |
596 | img_i2c_writel(i2c, SCB_READ_COUNT_REG, value: i2c->msg.len); |
597 | |
598 | mod_timer(timer: &i2c->check_timer, expires: jiffies + msecs_to_jiffies(m: 1)); |
599 | } |
600 | |
601 | /* Start a write transaction in automatic mode */ |
602 | static void img_i2c_write(struct img_i2c *i2c) |
603 | { |
604 | img_i2c_switch_mode(i2c, mode: MODE_AUTOMATIC); |
605 | if (!i2c->last_msg) |
606 | i2c->int_enable |= INT_SLAVE_EVENT; |
607 | |
608 | img_i2c_writel(i2c, SCB_WRITE_ADDR_REG, value: i2c->msg.addr); |
609 | img_i2c_writel(i2c, SCB_WRITE_COUNT_REG, value: i2c->msg.len); |
610 | |
611 | mod_timer(timer: &i2c->check_timer, expires: jiffies + msecs_to_jiffies(m: 1)); |
612 | img_i2c_write_fifo(i2c); |
613 | |
614 | /* img_i2c_write_fifo() may modify int_enable */ |
615 | img_i2c_writel(i2c, SCB_INT_MASK_REG, value: i2c->int_enable); |
616 | } |
617 | |
618 | /* |
619 | * Indicate that the transaction is complete. This is called from the |
620 | * ISR to wake up the waiting thread, after which the ISR must not |
621 | * access any more SCB registers. |
622 | */ |
623 | static void img_i2c_complete_transaction(struct img_i2c *i2c, int status) |
624 | { |
625 | img_i2c_switch_mode(i2c, mode: MODE_INACTIVE); |
626 | if (status) { |
627 | i2c->msg_status = status; |
628 | img_i2c_transaction_halt(i2c, t_halt: false); |
629 | } |
630 | complete(&i2c->msg_complete); |
631 | } |
632 | |
633 | static unsigned int img_i2c_raw_atomic_delay_handler(struct img_i2c *i2c, |
634 | u32 int_status, u32 line_status) |
635 | { |
636 | /* Stay in raw mode for this, so we don't just loop infinitely */ |
637 | img_i2c_atomic_op(i2c, cmd: i2c->at_cur_cmd, data: i2c->at_cur_data); |
638 | img_i2c_switch_mode(i2c, mode: MODE_ATOMIC); |
639 | return 0; |
640 | } |
641 | |
642 | static unsigned int img_i2c_raw(struct img_i2c *i2c, u32 int_status, |
643 | u32 line_status) |
644 | { |
645 | if (int_status & INT_TIMING) { |
646 | if (i2c->raw_timeout == 0) |
647 | return img_i2c_raw_atomic_delay_handler(i2c, |
648 | int_status, line_status); |
649 | --i2c->raw_timeout; |
650 | } |
651 | return 0; |
652 | } |
653 | |
654 | static unsigned int img_i2c_sequence(struct img_i2c *i2c, u32 int_status) |
655 | { |
656 | static const unsigned int continue_bits[] = { |
657 | [CMD_GEN_START] = LINESTAT_START_BIT_DET, |
658 | [CMD_GEN_DATA] = LINESTAT_INPUT_HELD_V, |
659 | [CMD_RET_ACK] = LINESTAT_ACK_DET | LINESTAT_NACK_DET, |
660 | [CMD_RET_DATA] = LINESTAT_INPUT_HELD_V, |
661 | [CMD_GEN_STOP] = LINESTAT_STOP_BIT_DET, |
662 | }; |
663 | int next_cmd = -1; |
664 | u8 next_data = 0x00; |
665 | |
666 | if (int_status & INT_SLAVE_EVENT) |
667 | i2c->at_slave_event = true; |
668 | if (int_status & INT_TRANSACTION_DONE) |
669 | i2c->at_t_done = true; |
670 | |
671 | if (!i2c->at_slave_event || !i2c->at_t_done) |
672 | return 0; |
673 | |
674 | /* wait if no continue bits are set */ |
675 | if (i2c->at_cur_cmd >= 0 && |
676 | i2c->at_cur_cmd < ARRAY_SIZE(continue_bits)) { |
677 | unsigned int cont_bits = continue_bits[i2c->at_cur_cmd]; |
678 | |
679 | if (cont_bits) { |
680 | cont_bits |= LINESTAT_ABORT_DET; |
681 | if (!(i2c->line_status & cont_bits)) |
682 | return 0; |
683 | } |
684 | } |
685 | |
686 | /* follow the sequence of commands in i2c->seq */ |
687 | next_cmd = *i2c->seq; |
688 | /* stop on a nil */ |
689 | if (!next_cmd) { |
690 | img_i2c_writel(i2c, SCB_OVERRIDE_REG, value: 0); |
691 | return ISR_COMPLETE(0); |
692 | } |
693 | /* when generating data, the next byte is the data */ |
694 | if (next_cmd == CMD_GEN_DATA) { |
695 | ++i2c->seq; |
696 | next_data = *i2c->seq; |
697 | } |
698 | ++i2c->seq; |
699 | img_i2c_atomic_op(i2c, cmd: next_cmd, data: next_data); |
700 | |
701 | return 0; |
702 | } |
703 | |
704 | static void img_i2c_reset_start(struct img_i2c *i2c) |
705 | { |
706 | /* Initiate the magic dance */ |
707 | img_i2c_switch_mode(i2c, mode: MODE_SEQUENCE); |
708 | img_i2c_writel(i2c, SCB_INT_MASK_REG, value: i2c->int_enable); |
709 | i2c->seq = img_i2c_reset_seq; |
710 | i2c->at_slave_event = true; |
711 | i2c->at_t_done = true; |
712 | i2c->at_cur_cmd = -1; |
713 | |
714 | /* img_i2c_reset_seq isn't empty so the following won't fail */ |
715 | img_i2c_sequence(i2c, int_status: 0); |
716 | } |
717 | |
718 | static void img_i2c_stop_start(struct img_i2c *i2c) |
719 | { |
720 | /* Initiate a stop bit sequence */ |
721 | img_i2c_switch_mode(i2c, mode: MODE_SEQUENCE); |
722 | img_i2c_writel(i2c, SCB_INT_MASK_REG, value: i2c->int_enable); |
723 | i2c->seq = img_i2c_stop_seq; |
724 | i2c->at_slave_event = true; |
725 | i2c->at_t_done = true; |
726 | i2c->at_cur_cmd = -1; |
727 | |
728 | /* img_i2c_stop_seq isn't empty so the following won't fail */ |
729 | img_i2c_sequence(i2c, int_status: 0); |
730 | } |
731 | |
732 | static unsigned int img_i2c_atomic(struct img_i2c *i2c, |
733 | u32 int_status, |
734 | u32 line_status) |
735 | { |
736 | int next_cmd = -1; |
737 | u8 next_data = 0x00; |
738 | |
739 | if (int_status & INT_SLAVE_EVENT) |
740 | i2c->at_slave_event = true; |
741 | if (int_status & INT_TRANSACTION_DONE) |
742 | i2c->at_t_done = true; |
743 | |
744 | if (!i2c->at_slave_event || !i2c->at_t_done) |
745 | goto next_atomic_cmd; |
746 | if (i2c->line_status & LINESTAT_ABORT_DET) { |
747 | dev_dbg(i2c->adap.dev.parent, "abort condition detected\n" ); |
748 | next_cmd = CMD_GEN_STOP; |
749 | i2c->msg_status = -EIO; |
750 | goto next_atomic_cmd; |
751 | } |
752 | |
753 | /* i2c->at_cur_cmd may have completed */ |
754 | switch (i2c->at_cur_cmd) { |
755 | case CMD_GEN_START: |
756 | next_cmd = CMD_GEN_DATA; |
757 | next_data = i2c_8bit_addr_from_msg(msg: &i2c->msg); |
758 | break; |
759 | case CMD_GEN_DATA: |
760 | if (i2c->line_status & LINESTAT_INPUT_HELD_V) |
761 | next_cmd = CMD_RET_ACK; |
762 | break; |
763 | case CMD_RET_ACK: |
764 | if (i2c->line_status & LINESTAT_ACK_DET || |
765 | (i2c->line_status & LINESTAT_NACK_DET && |
766 | i2c->msg.flags & I2C_M_IGNORE_NAK)) { |
767 | if (i2c->msg.len == 0) { |
768 | next_cmd = CMD_GEN_STOP; |
769 | } else if (i2c->msg.flags & I2C_M_RD) { |
770 | next_cmd = CMD_RET_DATA; |
771 | } else { |
772 | next_cmd = CMD_GEN_DATA; |
773 | next_data = *i2c->msg.buf; |
774 | --i2c->msg.len; |
775 | ++i2c->msg.buf; |
776 | } |
777 | } else if (i2c->line_status & LINESTAT_NACK_DET) { |
778 | i2c->msg_status = -EIO; |
779 | next_cmd = CMD_GEN_STOP; |
780 | } |
781 | break; |
782 | case CMD_RET_DATA: |
783 | if (i2c->line_status & LINESTAT_INPUT_HELD_V) { |
784 | *i2c->msg.buf = (i2c->line_status & |
785 | LINESTAT_INPUT_DATA) |
786 | >> LINESTAT_INPUT_DATA_SHIFT; |
787 | --i2c->msg.len; |
788 | ++i2c->msg.buf; |
789 | if (i2c->msg.len) |
790 | next_cmd = CMD_GEN_ACK; |
791 | else |
792 | next_cmd = CMD_GEN_NACK; |
793 | } |
794 | break; |
795 | case CMD_GEN_ACK: |
796 | if (i2c->line_status & LINESTAT_ACK_DET) { |
797 | next_cmd = CMD_RET_DATA; |
798 | } else { |
799 | i2c->msg_status = -EIO; |
800 | next_cmd = CMD_GEN_STOP; |
801 | } |
802 | break; |
803 | case CMD_GEN_NACK: |
804 | next_cmd = CMD_GEN_STOP; |
805 | break; |
806 | case CMD_GEN_STOP: |
807 | img_i2c_writel(i2c, SCB_OVERRIDE_REG, value: 0); |
808 | return ISR_COMPLETE(0); |
809 | default: |
810 | dev_err(i2c->adap.dev.parent, "bad atomic command %d\n" , |
811 | i2c->at_cur_cmd); |
812 | i2c->msg_status = -EIO; |
813 | next_cmd = CMD_GEN_STOP; |
814 | break; |
815 | } |
816 | |
817 | next_atomic_cmd: |
818 | if (next_cmd != -1) { |
819 | /* don't actually stop unless we're the last transaction */ |
820 | if (next_cmd == CMD_GEN_STOP && !i2c->msg_status && |
821 | !i2c->last_msg) |
822 | return ISR_COMPLETE(0); |
823 | img_i2c_atomic_op(i2c, cmd: next_cmd, data: next_data); |
824 | } |
825 | return 0; |
826 | } |
827 | |
828 | /* |
829 | * Timer function to check if something has gone wrong in automatic mode (so we |
830 | * don't have to handle so many interrupts just to catch an exception). |
831 | */ |
832 | static void img_i2c_check_timer(struct timer_list *t) |
833 | { |
834 | struct img_i2c *i2c = from_timer(i2c, t, check_timer); |
835 | unsigned long flags; |
836 | unsigned int line_status; |
837 | |
838 | spin_lock_irqsave(&i2c->lock, flags); |
839 | line_status = img_i2c_readl(i2c, SCB_STATUS_REG); |
840 | |
841 | /* check for an abort condition */ |
842 | if (line_status & LINESTAT_ABORT_DET) { |
843 | dev_dbg(i2c->adap.dev.parent, |
844 | "abort condition detected by check timer\n" ); |
845 | /* enable slave event interrupt mask to trigger irq */ |
846 | img_i2c_writel(i2c, SCB_INT_MASK_REG, |
847 | value: i2c->int_enable | INT_SLAVE_EVENT); |
848 | } |
849 | |
850 | spin_unlock_irqrestore(lock: &i2c->lock, flags); |
851 | } |
852 | |
853 | static unsigned int img_i2c_auto(struct img_i2c *i2c, |
854 | unsigned int int_status, |
855 | unsigned int line_status) |
856 | { |
857 | if (int_status & (INT_WRITE_ACK_ERR | INT_ADDR_ACK_ERR)) |
858 | return ISR_COMPLETE(EIO); |
859 | |
860 | if (line_status & LINESTAT_ABORT_DET) { |
861 | dev_dbg(i2c->adap.dev.parent, "abort condition detected\n" ); |
862 | /* empty the read fifo */ |
863 | if ((i2c->msg.flags & I2C_M_RD) && |
864 | (int_status & INT_FIFO_FULL_FILLING)) |
865 | img_i2c_read_fifo(i2c); |
866 | /* use atomic mode and try to force a stop bit */ |
867 | i2c->msg_status = -EIO; |
868 | img_i2c_stop_start(i2c); |
869 | return 0; |
870 | } |
871 | |
872 | /* Enable transaction halt on start bit */ |
873 | if (!i2c->last_msg && line_status & LINESTAT_START_BIT_DET) { |
874 | img_i2c_transaction_halt(i2c, t_halt: !i2c->last_msg); |
875 | /* we're no longer interested in the slave event */ |
876 | i2c->int_enable &= ~INT_SLAVE_EVENT; |
877 | } |
878 | |
879 | mod_timer(timer: &i2c->check_timer, expires: jiffies + msecs_to_jiffies(m: 1)); |
880 | |
881 | if (int_status & INT_STOP_DETECTED) { |
882 | /* Drain remaining data in FIFO and complete transaction */ |
883 | if (i2c->msg.flags & I2C_M_RD) |
884 | img_i2c_read_fifo(i2c); |
885 | return ISR_COMPLETE(0); |
886 | } |
887 | |
888 | if (i2c->msg.flags & I2C_M_RD) { |
889 | if (int_status & (INT_FIFO_FULL_FILLING | INT_MASTER_HALTED)) { |
890 | img_i2c_read_fifo(i2c); |
891 | if (i2c->msg.len == 0) |
892 | return ISR_WAITSTOP; |
893 | } |
894 | } else { |
895 | if (int_status & (INT_FIFO_EMPTY | INT_MASTER_HALTED)) { |
896 | if ((int_status & INT_FIFO_EMPTY) && |
897 | i2c->msg.len == 0) |
898 | return ISR_WAITSTOP; |
899 | img_i2c_write_fifo(i2c); |
900 | } |
901 | } |
902 | if (int_status & INT_MASTER_HALTED) { |
903 | /* |
904 | * Release and then enable transaction halt, to |
905 | * allow only a single byte to proceed. |
906 | */ |
907 | img_i2c_transaction_halt(i2c, t_halt: false); |
908 | img_i2c_transaction_halt(i2c, t_halt: !i2c->last_msg); |
909 | } |
910 | |
911 | return 0; |
912 | } |
913 | |
914 | static irqreturn_t img_i2c_isr(int irq, void *dev_id) |
915 | { |
916 | struct img_i2c *i2c = dev_id; |
917 | u32 int_status, line_status; |
918 | /* We handle transaction completion AFTER accessing registers */ |
919 | unsigned int hret; |
920 | |
921 | /* Read interrupt status register. */ |
922 | int_status = img_i2c_readl(i2c, SCB_INT_STATUS_REG); |
923 | /* Clear detected interrupts. */ |
924 | img_i2c_writel(i2c, SCB_INT_CLEAR_REG, value: int_status); |
925 | |
926 | /* |
927 | * Read line status and clear it until it actually is clear. We have |
928 | * to be careful not to lose any line status bits that get latched. |
929 | */ |
930 | line_status = img_i2c_readl(i2c, SCB_STATUS_REG); |
931 | if (line_status & LINESTAT_LATCHED) { |
932 | img_i2c_writel(i2c, SCB_CLEAR_REG, |
933 | value: (line_status & LINESTAT_LATCHED) |
934 | >> LINESTAT_CLEAR_SHIFT); |
935 | img_i2c_wr_rd_fence(i2c); |
936 | } |
937 | |
938 | spin_lock(lock: &i2c->lock); |
939 | |
940 | /* Keep track of line status bits received */ |
941 | i2c->line_status &= ~LINESTAT_INPUT_DATA; |
942 | i2c->line_status |= line_status; |
943 | |
944 | /* |
945 | * Certain interrupts indicate that sclk low timeout is not |
946 | * a problem. If any of these are set, just continue. |
947 | */ |
948 | if ((int_status & INT_SCLK_LOW_TIMEOUT) && |
949 | !(int_status & (INT_SLAVE_EVENT | |
950 | INT_FIFO_EMPTY | |
951 | INT_FIFO_FULL))) { |
952 | dev_crit(i2c->adap.dev.parent, |
953 | "fatal: clock low timeout occurred %s addr 0x%02x\n" , |
954 | (i2c->msg.flags & I2C_M_RD) ? "reading" : "writing" , |
955 | i2c->msg.addr); |
956 | hret = ISR_FATAL(EIO); |
957 | goto out; |
958 | } |
959 | |
960 | if (i2c->mode == MODE_ATOMIC) |
961 | hret = img_i2c_atomic(i2c, int_status, line_status); |
962 | else if (i2c->mode == MODE_AUTOMATIC) |
963 | hret = img_i2c_auto(i2c, int_status, line_status); |
964 | else if (i2c->mode == MODE_SEQUENCE) |
965 | hret = img_i2c_sequence(i2c, int_status); |
966 | else if (i2c->mode == MODE_WAITSTOP && (int_status & INT_SLAVE_EVENT) && |
967 | (line_status & LINESTAT_STOP_BIT_DET)) |
968 | hret = ISR_COMPLETE(0); |
969 | else if (i2c->mode == MODE_RAW) |
970 | hret = img_i2c_raw(i2c, int_status, line_status); |
971 | else |
972 | hret = 0; |
973 | |
974 | /* Clear detected level interrupts. */ |
975 | img_i2c_writel(i2c, SCB_INT_CLEAR_REG, value: int_status & INT_LEVEL); |
976 | |
977 | out: |
978 | if (hret & ISR_WAITSTOP) { |
979 | /* |
980 | * Only wait for stop on last message. |
981 | * Also we may already have detected the stop bit. |
982 | */ |
983 | if (!i2c->last_msg || i2c->line_status & LINESTAT_STOP_BIT_DET) |
984 | hret = ISR_COMPLETE(0); |
985 | else |
986 | img_i2c_switch_mode(i2c, mode: MODE_WAITSTOP); |
987 | } |
988 | |
989 | /* now we've finished using regs, handle transaction completion */ |
990 | if (hret & ISR_COMPLETE_M) { |
991 | int status = -(hret & ISR_STATUS_M); |
992 | |
993 | img_i2c_complete_transaction(i2c, status); |
994 | if (hret & ISR_FATAL_M) |
995 | img_i2c_switch_mode(i2c, mode: MODE_FATAL); |
996 | } |
997 | |
998 | /* Enable interrupts (int_enable may be altered by changing mode) */ |
999 | img_i2c_writel(i2c, SCB_INT_MASK_REG, value: i2c->int_enable); |
1000 | |
1001 | spin_unlock(lock: &i2c->lock); |
1002 | |
1003 | return IRQ_HANDLED; |
1004 | } |
1005 | |
1006 | /* Force a bus reset sequence and wait for it to complete */ |
1007 | static int img_i2c_reset_bus(struct img_i2c *i2c) |
1008 | { |
1009 | unsigned long flags; |
1010 | unsigned long time_left; |
1011 | |
1012 | spin_lock_irqsave(&i2c->lock, flags); |
1013 | reinit_completion(x: &i2c->msg_complete); |
1014 | img_i2c_reset_start(i2c); |
1015 | spin_unlock_irqrestore(lock: &i2c->lock, flags); |
1016 | |
1017 | time_left = wait_for_completion_timeout(x: &i2c->msg_complete, |
1018 | IMG_I2C_TIMEOUT); |
1019 | if (time_left == 0) |
1020 | return -ETIMEDOUT; |
1021 | return 0; |
1022 | } |
1023 | |
1024 | static int img_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, |
1025 | int num) |
1026 | { |
1027 | struct img_i2c *i2c = i2c_get_adapdata(adap); |
1028 | bool atomic = false; |
1029 | int i, ret; |
1030 | unsigned long time_left; |
1031 | |
1032 | if (i2c->mode == MODE_SUSPEND) { |
1033 | WARN(1, "refusing to service transaction in suspended state\n" ); |
1034 | return -EIO; |
1035 | } |
1036 | |
1037 | if (i2c->mode == MODE_FATAL) |
1038 | return -EIO; |
1039 | |
1040 | for (i = 0; i < num; i++) { |
1041 | /* |
1042 | * 0 byte reads are not possible because the slave could try |
1043 | * and pull the data line low, preventing a stop bit. |
1044 | */ |
1045 | if (!msgs[i].len && msgs[i].flags & I2C_M_RD) |
1046 | return -EIO; |
1047 | /* |
1048 | * 0 byte writes are possible and used for probing, but we |
1049 | * cannot do them in automatic mode, so use atomic mode |
1050 | * instead. |
1051 | * |
1052 | * Also, the I2C_M_IGNORE_NAK mode can only be implemented |
1053 | * in atomic mode. |
1054 | */ |
1055 | if (!msgs[i].len || |
1056 | (msgs[i].flags & I2C_M_IGNORE_NAK)) |
1057 | atomic = true; |
1058 | } |
1059 | |
1060 | ret = pm_runtime_resume_and_get(dev: adap->dev.parent); |
1061 | if (ret < 0) |
1062 | return ret; |
1063 | |
1064 | for (i = 0; i < num; i++) { |
1065 | struct i2c_msg *msg = &msgs[i]; |
1066 | unsigned long flags; |
1067 | |
1068 | spin_lock_irqsave(&i2c->lock, flags); |
1069 | |
1070 | /* |
1071 | * Make a copy of the message struct. We mustn't modify the |
1072 | * original or we'll confuse drivers and i2c-dev. |
1073 | */ |
1074 | i2c->msg = *msg; |
1075 | i2c->msg_status = 0; |
1076 | |
1077 | /* |
1078 | * After the last message we must have waited for a stop bit. |
1079 | * Not waiting can cause problems when the clock is disabled |
1080 | * before the stop bit is sent, and the linux I2C interface |
1081 | * requires separate transfers not to joined with repeated |
1082 | * start. |
1083 | */ |
1084 | i2c->last_msg = (i == num - 1); |
1085 | reinit_completion(x: &i2c->msg_complete); |
1086 | |
1087 | /* |
1088 | * Clear line status and all interrupts before starting a |
1089 | * transfer, as we may have unserviced interrupts from |
1090 | * previous transfers that might be handled in the context |
1091 | * of the new transfer. |
1092 | */ |
1093 | img_i2c_writel(i2c, SCB_INT_CLEAR_REG, value: ~0); |
1094 | img_i2c_writel(i2c, SCB_CLEAR_REG, value: ~0); |
1095 | |
1096 | if (atomic) { |
1097 | img_i2c_atomic_start(i2c); |
1098 | } else { |
1099 | /* |
1100 | * Enable transaction halt if not the last message in |
1101 | * the queue so that we can control repeated starts. |
1102 | */ |
1103 | img_i2c_transaction_halt(i2c, t_halt: !i2c->last_msg); |
1104 | |
1105 | if (msg->flags & I2C_M_RD) |
1106 | img_i2c_read(i2c); |
1107 | else |
1108 | img_i2c_write(i2c); |
1109 | |
1110 | /* |
1111 | * Release and then enable transaction halt, to |
1112 | * allow only a single byte to proceed. |
1113 | * This doesn't have an effect on the initial transfer |
1114 | * but will allow the following transfers to start |
1115 | * processing if the previous transfer was marked as |
1116 | * complete while the i2c block was halted. |
1117 | */ |
1118 | img_i2c_transaction_halt(i2c, t_halt: false); |
1119 | img_i2c_transaction_halt(i2c, t_halt: !i2c->last_msg); |
1120 | } |
1121 | spin_unlock_irqrestore(lock: &i2c->lock, flags); |
1122 | |
1123 | time_left = wait_for_completion_timeout(x: &i2c->msg_complete, |
1124 | IMG_I2C_TIMEOUT); |
1125 | del_timer_sync(timer: &i2c->check_timer); |
1126 | |
1127 | if (time_left == 0) { |
1128 | dev_err(adap->dev.parent, "i2c transfer timed out\n" ); |
1129 | i2c->msg_status = -ETIMEDOUT; |
1130 | break; |
1131 | } |
1132 | |
1133 | if (i2c->msg_status) |
1134 | break; |
1135 | } |
1136 | |
1137 | pm_runtime_mark_last_busy(dev: adap->dev.parent); |
1138 | pm_runtime_put_autosuspend(dev: adap->dev.parent); |
1139 | |
1140 | return i2c->msg_status ? i2c->msg_status : num; |
1141 | } |
1142 | |
1143 | static u32 img_i2c_func(struct i2c_adapter *adap) |
1144 | { |
1145 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
1146 | } |
1147 | |
1148 | static const struct i2c_algorithm img_i2c_algo = { |
1149 | .master_xfer = img_i2c_xfer, |
1150 | .functionality = img_i2c_func, |
1151 | }; |
1152 | |
1153 | static int img_i2c_init(struct img_i2c *i2c) |
1154 | { |
1155 | unsigned int clk_khz, bitrate_khz, clk_period, tckh, tckl, tsdh; |
1156 | unsigned int i, data, prescale, inc, int_bitrate, filt; |
1157 | struct img_i2c_timings timing; |
1158 | u32 rev; |
1159 | int ret; |
1160 | |
1161 | ret = pm_runtime_resume_and_get(dev: i2c->adap.dev.parent); |
1162 | if (ret < 0) |
1163 | return ret; |
1164 | |
1165 | rev = img_i2c_readl(i2c, SCB_CORE_REV_REG); |
1166 | if ((rev & 0x00ffffff) < 0x00020200) { |
1167 | dev_info(i2c->adap.dev.parent, |
1168 | "Unknown hardware revision (%d.%d.%d.%d)\n" , |
1169 | (rev >> 24) & 0xff, (rev >> 16) & 0xff, |
1170 | (rev >> 8) & 0xff, rev & 0xff); |
1171 | pm_runtime_mark_last_busy(dev: i2c->adap.dev.parent); |
1172 | pm_runtime_put_autosuspend(dev: i2c->adap.dev.parent); |
1173 | return -EINVAL; |
1174 | } |
1175 | |
1176 | /* Fencing enabled by default. */ |
1177 | i2c->need_wr_rd_fence = true; |
1178 | |
1179 | /* Determine what mode we're in from the bitrate */ |
1180 | timing = timings[0]; |
1181 | for (i = 0; i < ARRAY_SIZE(timings); i++) { |
1182 | if (i2c->bitrate <= timings[i].max_bitrate) { |
1183 | timing = timings[i]; |
1184 | break; |
1185 | } |
1186 | } |
1187 | if (i2c->bitrate > timings[ARRAY_SIZE(timings) - 1].max_bitrate) { |
1188 | dev_warn(i2c->adap.dev.parent, |
1189 | "requested bitrate (%u) is higher than the max bitrate supported (%u)\n" , |
1190 | i2c->bitrate, |
1191 | timings[ARRAY_SIZE(timings) - 1].max_bitrate); |
1192 | timing = timings[ARRAY_SIZE(timings) - 1]; |
1193 | i2c->bitrate = timing.max_bitrate; |
1194 | } |
1195 | |
1196 | bitrate_khz = i2c->bitrate / 1000; |
1197 | clk_khz = clk_get_rate(clk: i2c->scb_clk) / 1000; |
1198 | |
1199 | /* Find the prescale that would give us that inc (approx delay = 0) */ |
1200 | prescale = SCB_OPT_INC * clk_khz / (256 * 16 * bitrate_khz); |
1201 | prescale = clamp_t(unsigned int, prescale, 1, 8); |
1202 | clk_khz /= prescale; |
1203 | |
1204 | /* Setup the clock increment value */ |
1205 | inc = (256 * 16 * bitrate_khz) / clk_khz; |
1206 | |
1207 | /* |
1208 | * The clock generation logic allows to filter glitches on the bus. |
1209 | * This filter is able to remove bus glitches shorter than 50ns. |
1210 | * If the clock enable rate is greater than 20 MHz, no filtering |
1211 | * is required, so we need to disable it. |
1212 | * If it's between the 20-40 MHz range, there's no need to divide |
1213 | * the clock to get a filter. |
1214 | */ |
1215 | if (clk_khz < 20000) { |
1216 | filt = SCB_FILT_DISABLE; |
1217 | } else if (clk_khz < 40000) { |
1218 | filt = SCB_FILT_BYPASS; |
1219 | } else { |
1220 | /* Calculate filter clock */ |
1221 | filt = (64000 / ((clk_khz / 1000) * SCB_FILT_GLITCH)); |
1222 | |
1223 | /* Scale up if needed */ |
1224 | if (64000 % ((clk_khz / 1000) * SCB_FILT_GLITCH)) |
1225 | inc++; |
1226 | |
1227 | if (filt > SCB_FILT_INC_MASK) |
1228 | filt = SCB_FILT_INC_MASK; |
1229 | |
1230 | filt = (filt & SCB_FILT_INC_MASK) << SCB_FILT_INC_SHIFT; |
1231 | } |
1232 | data = filt | ((inc & SCB_INC_MASK) << SCB_INC_SHIFT) | (prescale - 1); |
1233 | img_i2c_writel(i2c, SCB_CLK_SET_REG, value: data); |
1234 | |
1235 | /* Obtain the clock period of the fx16 clock in ns */ |
1236 | clk_period = (256 * 1000000) / (clk_khz * inc); |
1237 | |
1238 | /* Calculate the bitrate in terms of internal clock pulses */ |
1239 | int_bitrate = 1000000 / (bitrate_khz * clk_period); |
1240 | if ((1000000 % (bitrate_khz * clk_period)) >= |
1241 | ((bitrate_khz * clk_period) / 2)) |
1242 | int_bitrate++; |
1243 | |
1244 | /* |
1245 | * Setup clock duty cycle, start with 50% and adjust TCKH and TCKL |
1246 | * values from there if they don't meet minimum timing requirements |
1247 | */ |
1248 | tckh = int_bitrate / 2; |
1249 | tckl = int_bitrate - tckh; |
1250 | |
1251 | /* Adjust TCKH and TCKL values */ |
1252 | data = DIV_ROUND_UP(timing.tckl, clk_period); |
1253 | |
1254 | if (tckl < data) { |
1255 | tckl = data; |
1256 | tckh = int_bitrate - tckl; |
1257 | } |
1258 | |
1259 | if (tckh > 0) |
1260 | --tckh; |
1261 | |
1262 | if (tckl > 0) |
1263 | --tckl; |
1264 | |
1265 | img_i2c_writel(i2c, SCB_TIME_TCKH_REG, value: tckh); |
1266 | img_i2c_writel(i2c, SCB_TIME_TCKL_REG, value: tckl); |
1267 | |
1268 | /* Setup TSDH value */ |
1269 | tsdh = DIV_ROUND_UP(timing.tsdh, clk_period); |
1270 | |
1271 | if (tsdh > 1) |
1272 | data = tsdh - 1; |
1273 | else |
1274 | data = 0x01; |
1275 | img_i2c_writel(i2c, SCB_TIME_TSDH_REG, value: data); |
1276 | |
1277 | /* This value is used later */ |
1278 | tsdh = data; |
1279 | |
1280 | /* Setup TPL value */ |
1281 | data = timing.tpl / clk_period; |
1282 | if (data > 0) |
1283 | --data; |
1284 | img_i2c_writel(i2c, SCB_TIME_TPL_REG, value: data); |
1285 | |
1286 | /* Setup TPH value */ |
1287 | data = timing.tph / clk_period; |
1288 | if (data > 0) |
1289 | --data; |
1290 | img_i2c_writel(i2c, SCB_TIME_TPH_REG, value: data); |
1291 | |
1292 | /* Setup TSDL value to TPL + TSDH + 2 */ |
1293 | img_i2c_writel(i2c, SCB_TIME_TSDL_REG, value: data + tsdh + 2); |
1294 | |
1295 | /* Setup TP2S value */ |
1296 | data = timing.tp2s / clk_period; |
1297 | if (data > 0) |
1298 | --data; |
1299 | img_i2c_writel(i2c, SCB_TIME_TP2S_REG, value: data); |
1300 | |
1301 | img_i2c_writel(i2c, SCB_TIME_TBI_REG, TIMEOUT_TBI); |
1302 | img_i2c_writel(i2c, SCB_TIME_TSL_REG, TIMEOUT_TSL); |
1303 | img_i2c_writel(i2c, SCB_TIME_TDL_REG, TIMEOUT_TDL); |
1304 | |
1305 | /* Take module out of soft reset and enable clocks */ |
1306 | img_i2c_soft_reset(i2c); |
1307 | |
1308 | /* Disable all interrupts */ |
1309 | img_i2c_writel(i2c, SCB_INT_MASK_REG, value: 0); |
1310 | |
1311 | /* Clear all interrupts */ |
1312 | img_i2c_writel(i2c, SCB_INT_CLEAR_REG, value: ~0); |
1313 | |
1314 | /* Clear the scb_line_status events */ |
1315 | img_i2c_writel(i2c, SCB_CLEAR_REG, value: ~0); |
1316 | |
1317 | /* Enable interrupts */ |
1318 | img_i2c_writel(i2c, SCB_INT_MASK_REG, value: i2c->int_enable); |
1319 | |
1320 | /* Perform a synchronous sequence to reset the bus */ |
1321 | ret = img_i2c_reset_bus(i2c); |
1322 | |
1323 | pm_runtime_mark_last_busy(dev: i2c->adap.dev.parent); |
1324 | pm_runtime_put_autosuspend(dev: i2c->adap.dev.parent); |
1325 | |
1326 | return ret; |
1327 | } |
1328 | |
1329 | static int img_i2c_probe(struct platform_device *pdev) |
1330 | { |
1331 | struct device_node *node = pdev->dev.of_node; |
1332 | struct img_i2c *i2c; |
1333 | int irq, ret; |
1334 | u32 val; |
1335 | |
1336 | i2c = devm_kzalloc(dev: &pdev->dev, size: sizeof(struct img_i2c), GFP_KERNEL); |
1337 | if (!i2c) |
1338 | return -ENOMEM; |
1339 | |
1340 | i2c->base = devm_platform_ioremap_resource(pdev, index: 0); |
1341 | if (IS_ERR(ptr: i2c->base)) |
1342 | return PTR_ERR(ptr: i2c->base); |
1343 | |
1344 | irq = platform_get_irq(pdev, 0); |
1345 | if (irq < 0) |
1346 | return irq; |
1347 | |
1348 | i2c->sys_clk = devm_clk_get(dev: &pdev->dev, id: "sys" ); |
1349 | if (IS_ERR(ptr: i2c->sys_clk)) { |
1350 | dev_err(&pdev->dev, "can't get system clock\n" ); |
1351 | return PTR_ERR(ptr: i2c->sys_clk); |
1352 | } |
1353 | |
1354 | i2c->scb_clk = devm_clk_get(dev: &pdev->dev, id: "scb" ); |
1355 | if (IS_ERR(ptr: i2c->scb_clk)) { |
1356 | dev_err(&pdev->dev, "can't get core clock\n" ); |
1357 | return PTR_ERR(ptr: i2c->scb_clk); |
1358 | } |
1359 | |
1360 | ret = devm_request_irq(dev: &pdev->dev, irq, handler: img_i2c_isr, irqflags: 0, |
1361 | devname: pdev->name, dev_id: i2c); |
1362 | if (ret) { |
1363 | dev_err(&pdev->dev, "can't request irq %d\n" , irq); |
1364 | return ret; |
1365 | } |
1366 | |
1367 | /* Set up the exception check timer */ |
1368 | timer_setup(&i2c->check_timer, img_i2c_check_timer, 0); |
1369 | |
1370 | i2c->bitrate = timings[0].max_bitrate; |
1371 | if (!of_property_read_u32(np: node, propname: "clock-frequency" , out_value: &val)) |
1372 | i2c->bitrate = val; |
1373 | |
1374 | i2c_set_adapdata(adap: &i2c->adap, data: i2c); |
1375 | i2c->adap.dev.parent = &pdev->dev; |
1376 | i2c->adap.dev.of_node = node; |
1377 | i2c->adap.owner = THIS_MODULE; |
1378 | i2c->adap.algo = &img_i2c_algo; |
1379 | i2c->adap.retries = 5; |
1380 | i2c->adap.nr = pdev->id; |
1381 | snprintf(buf: i2c->adap.name, size: sizeof(i2c->adap.name), fmt: "IMG SCB I2C" ); |
1382 | |
1383 | img_i2c_switch_mode(i2c, mode: MODE_INACTIVE); |
1384 | spin_lock_init(&i2c->lock); |
1385 | init_completion(x: &i2c->msg_complete); |
1386 | |
1387 | platform_set_drvdata(pdev, data: i2c); |
1388 | |
1389 | pm_runtime_set_autosuspend_delay(dev: &pdev->dev, IMG_I2C_PM_TIMEOUT); |
1390 | pm_runtime_use_autosuspend(dev: &pdev->dev); |
1391 | pm_runtime_enable(dev: &pdev->dev); |
1392 | if (!pm_runtime_enabled(dev: &pdev->dev)) { |
1393 | ret = img_i2c_runtime_resume(dev: &pdev->dev); |
1394 | if (ret) |
1395 | return ret; |
1396 | } |
1397 | |
1398 | ret = img_i2c_init(i2c); |
1399 | if (ret) |
1400 | goto rpm_disable; |
1401 | |
1402 | ret = i2c_add_numbered_adapter(adap: &i2c->adap); |
1403 | if (ret < 0) |
1404 | goto rpm_disable; |
1405 | |
1406 | return 0; |
1407 | |
1408 | rpm_disable: |
1409 | if (!pm_runtime_enabled(dev: &pdev->dev)) |
1410 | img_i2c_runtime_suspend(dev: &pdev->dev); |
1411 | pm_runtime_disable(dev: &pdev->dev); |
1412 | pm_runtime_dont_use_autosuspend(dev: &pdev->dev); |
1413 | return ret; |
1414 | } |
1415 | |
1416 | static void img_i2c_remove(struct platform_device *dev) |
1417 | { |
1418 | struct img_i2c *i2c = platform_get_drvdata(pdev: dev); |
1419 | |
1420 | i2c_del_adapter(adap: &i2c->adap); |
1421 | pm_runtime_disable(dev: &dev->dev); |
1422 | if (!pm_runtime_status_suspended(dev: &dev->dev)) |
1423 | img_i2c_runtime_suspend(dev: &dev->dev); |
1424 | } |
1425 | |
1426 | static int img_i2c_runtime_suspend(struct device *dev) |
1427 | { |
1428 | struct img_i2c *i2c = dev_get_drvdata(dev); |
1429 | |
1430 | clk_disable_unprepare(clk: i2c->scb_clk); |
1431 | clk_disable_unprepare(clk: i2c->sys_clk); |
1432 | |
1433 | return 0; |
1434 | } |
1435 | |
1436 | static int img_i2c_runtime_resume(struct device *dev) |
1437 | { |
1438 | struct img_i2c *i2c = dev_get_drvdata(dev); |
1439 | int ret; |
1440 | |
1441 | ret = clk_prepare_enable(clk: i2c->sys_clk); |
1442 | if (ret) { |
1443 | dev_err(dev, "Unable to enable sys clock\n" ); |
1444 | return ret; |
1445 | } |
1446 | |
1447 | ret = clk_prepare_enable(clk: i2c->scb_clk); |
1448 | if (ret) { |
1449 | dev_err(dev, "Unable to enable scb clock\n" ); |
1450 | clk_disable_unprepare(clk: i2c->sys_clk); |
1451 | return ret; |
1452 | } |
1453 | |
1454 | return 0; |
1455 | } |
1456 | |
1457 | static int img_i2c_suspend(struct device *dev) |
1458 | { |
1459 | struct img_i2c *i2c = dev_get_drvdata(dev); |
1460 | int ret; |
1461 | |
1462 | ret = pm_runtime_force_suspend(dev); |
1463 | if (ret) |
1464 | return ret; |
1465 | |
1466 | img_i2c_switch_mode(i2c, mode: MODE_SUSPEND); |
1467 | |
1468 | return 0; |
1469 | } |
1470 | |
1471 | static int img_i2c_resume(struct device *dev) |
1472 | { |
1473 | struct img_i2c *i2c = dev_get_drvdata(dev); |
1474 | int ret; |
1475 | |
1476 | ret = pm_runtime_force_resume(dev); |
1477 | if (ret) |
1478 | return ret; |
1479 | |
1480 | img_i2c_init(i2c); |
1481 | |
1482 | return 0; |
1483 | } |
1484 | |
1485 | static const struct dev_pm_ops img_i2c_pm = { |
1486 | RUNTIME_PM_OPS(img_i2c_runtime_suspend, img_i2c_runtime_resume, NULL) |
1487 | SYSTEM_SLEEP_PM_OPS(img_i2c_suspend, img_i2c_resume) |
1488 | }; |
1489 | |
1490 | static const struct of_device_id img_scb_i2c_match[] = { |
1491 | { .compatible = "img,scb-i2c" }, |
1492 | { } |
1493 | }; |
1494 | MODULE_DEVICE_TABLE(of, img_scb_i2c_match); |
1495 | |
1496 | static struct platform_driver img_scb_i2c_driver = { |
1497 | .driver = { |
1498 | .name = "img-i2c-scb" , |
1499 | .of_match_table = img_scb_i2c_match, |
1500 | .pm = pm_ptr(&img_i2c_pm), |
1501 | }, |
1502 | .probe = img_i2c_probe, |
1503 | .remove_new = img_i2c_remove, |
1504 | }; |
1505 | module_platform_driver(img_scb_i2c_driver); |
1506 | |
1507 | MODULE_AUTHOR("James Hogan <jhogan@kernel.org>" ); |
1508 | MODULE_DESCRIPTION("IMG host I2C driver" ); |
1509 | MODULE_LICENSE("GPL v2" ); |
1510 | |