1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * This is i.MX low power i2c controller driver. |
4 | * |
5 | * Copyright 2016 Freescale Semiconductor, Inc. |
6 | */ |
7 | |
8 | #include <linux/clk.h> |
9 | #include <linux/completion.h> |
10 | #include <linux/delay.h> |
11 | #include <linux/err.h> |
12 | #include <linux/errno.h> |
13 | #include <linux/i2c.h> |
14 | #include <linux/init.h> |
15 | #include <linux/interrupt.h> |
16 | #include <linux/io.h> |
17 | #include <linux/kernel.h> |
18 | #include <linux/module.h> |
19 | #include <linux/of.h> |
20 | #include <linux/pinctrl/consumer.h> |
21 | #include <linux/platform_device.h> |
22 | #include <linux/pm_runtime.h> |
23 | #include <linux/sched.h> |
24 | #include <linux/slab.h> |
25 | |
26 | #define DRIVER_NAME "imx-lpi2c" |
27 | |
28 | #define LPI2C_PARAM 0x04 /* i2c RX/TX FIFO size */ |
29 | #define LPI2C_MCR 0x10 /* i2c contrl register */ |
30 | #define LPI2C_MSR 0x14 /* i2c status register */ |
31 | #define LPI2C_MIER 0x18 /* i2c interrupt enable */ |
32 | #define LPI2C_MCFGR0 0x20 /* i2c master configuration */ |
33 | #define LPI2C_MCFGR1 0x24 /* i2c master configuration */ |
34 | #define LPI2C_MCFGR2 0x28 /* i2c master configuration */ |
35 | #define LPI2C_MCFGR3 0x2C /* i2c master configuration */ |
36 | #define LPI2C_MCCR0 0x48 /* i2c master clk configuration */ |
37 | #define LPI2C_MCCR1 0x50 /* i2c master clk configuration */ |
38 | #define LPI2C_MFCR 0x58 /* i2c master FIFO control */ |
39 | #define LPI2C_MFSR 0x5C /* i2c master FIFO status */ |
40 | #define LPI2C_MTDR 0x60 /* i2c master TX data register */ |
41 | #define LPI2C_MRDR 0x70 /* i2c master RX data register */ |
42 | |
43 | /* i2c command */ |
44 | #define TRAN_DATA 0X00 |
45 | #define RECV_DATA 0X01 |
46 | #define GEN_STOP 0X02 |
47 | #define RECV_DISCARD 0X03 |
48 | #define GEN_START 0X04 |
49 | #define START_NACK 0X05 |
50 | #define START_HIGH 0X06 |
51 | #define START_HIGH_NACK 0X07 |
52 | |
53 | #define MCR_MEN BIT(0) |
54 | #define MCR_RST BIT(1) |
55 | #define MCR_DOZEN BIT(2) |
56 | #define MCR_DBGEN BIT(3) |
57 | #define MCR_RTF BIT(8) |
58 | #define MCR_RRF BIT(9) |
59 | #define MSR_TDF BIT(0) |
60 | #define MSR_RDF BIT(1) |
61 | #define MSR_SDF BIT(9) |
62 | #define MSR_NDF BIT(10) |
63 | #define MSR_ALF BIT(11) |
64 | #define MSR_MBF BIT(24) |
65 | #define MSR_BBF BIT(25) |
66 | #define MIER_TDIE BIT(0) |
67 | #define MIER_RDIE BIT(1) |
68 | #define MIER_SDIE BIT(9) |
69 | #define MIER_NDIE BIT(10) |
70 | #define MCFGR1_AUTOSTOP BIT(8) |
71 | #define MCFGR1_IGNACK BIT(9) |
72 | #define MRDR_RXEMPTY BIT(14) |
73 | |
74 | #define I2C_CLK_RATIO 2 |
75 | #define CHUNK_DATA 256 |
76 | |
77 | #define I2C_PM_TIMEOUT 10 /* ms */ |
78 | |
79 | enum lpi2c_imx_mode { |
80 | STANDARD, /* 100+Kbps */ |
81 | FAST, /* 400+Kbps */ |
82 | FAST_PLUS, /* 1.0+Mbps */ |
83 | HS, /* 3.4+Mbps */ |
84 | ULTRA_FAST, /* 5.0+Mbps */ |
85 | }; |
86 | |
87 | enum lpi2c_imx_pincfg { |
88 | TWO_PIN_OD, |
89 | TWO_PIN_OO, |
90 | TWO_PIN_PP, |
91 | FOUR_PIN_PP, |
92 | }; |
93 | |
94 | struct lpi2c_imx_struct { |
95 | struct i2c_adapter adapter; |
96 | int num_clks; |
97 | struct clk_bulk_data *clks; |
98 | void __iomem *base; |
99 | __u8 *rx_buf; |
100 | __u8 *tx_buf; |
101 | struct completion complete; |
102 | unsigned int msglen; |
103 | unsigned int delivered; |
104 | unsigned int block_data; |
105 | unsigned int bitrate; |
106 | unsigned int txfifosize; |
107 | unsigned int rxfifosize; |
108 | enum lpi2c_imx_mode mode; |
109 | }; |
110 | |
111 | static void lpi2c_imx_intctrl(struct lpi2c_imx_struct *lpi2c_imx, |
112 | unsigned int enable) |
113 | { |
114 | writel(val: enable, addr: lpi2c_imx->base + LPI2C_MIER); |
115 | } |
116 | |
117 | static int lpi2c_imx_bus_busy(struct lpi2c_imx_struct *lpi2c_imx) |
118 | { |
119 | unsigned long orig_jiffies = jiffies; |
120 | unsigned int temp; |
121 | |
122 | while (1) { |
123 | temp = readl(addr: lpi2c_imx->base + LPI2C_MSR); |
124 | |
125 | /* check for arbitration lost, clear if set */ |
126 | if (temp & MSR_ALF) { |
127 | writel(val: temp, addr: lpi2c_imx->base + LPI2C_MSR); |
128 | return -EAGAIN; |
129 | } |
130 | |
131 | if (temp & (MSR_BBF | MSR_MBF)) |
132 | break; |
133 | |
134 | if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { |
135 | dev_dbg(&lpi2c_imx->adapter.dev, "bus not work\n" ); |
136 | return -ETIMEDOUT; |
137 | } |
138 | schedule(); |
139 | } |
140 | |
141 | return 0; |
142 | } |
143 | |
144 | static void lpi2c_imx_set_mode(struct lpi2c_imx_struct *lpi2c_imx) |
145 | { |
146 | unsigned int bitrate = lpi2c_imx->bitrate; |
147 | enum lpi2c_imx_mode mode; |
148 | |
149 | if (bitrate < I2C_MAX_FAST_MODE_FREQ) |
150 | mode = STANDARD; |
151 | else if (bitrate < I2C_MAX_FAST_MODE_PLUS_FREQ) |
152 | mode = FAST; |
153 | else if (bitrate < I2C_MAX_HIGH_SPEED_MODE_FREQ) |
154 | mode = FAST_PLUS; |
155 | else if (bitrate < I2C_MAX_ULTRA_FAST_MODE_FREQ) |
156 | mode = HS; |
157 | else |
158 | mode = ULTRA_FAST; |
159 | |
160 | lpi2c_imx->mode = mode; |
161 | } |
162 | |
163 | static int lpi2c_imx_start(struct lpi2c_imx_struct *lpi2c_imx, |
164 | struct i2c_msg *msgs) |
165 | { |
166 | unsigned int temp; |
167 | |
168 | temp = readl(addr: lpi2c_imx->base + LPI2C_MCR); |
169 | temp |= MCR_RRF | MCR_RTF; |
170 | writel(val: temp, addr: lpi2c_imx->base + LPI2C_MCR); |
171 | writel(val: 0x7f00, addr: lpi2c_imx->base + LPI2C_MSR); |
172 | |
173 | temp = i2c_8bit_addr_from_msg(msg: msgs) | (GEN_START << 8); |
174 | writel(val: temp, addr: lpi2c_imx->base + LPI2C_MTDR); |
175 | |
176 | return lpi2c_imx_bus_busy(lpi2c_imx); |
177 | } |
178 | |
179 | static void lpi2c_imx_stop(struct lpi2c_imx_struct *lpi2c_imx) |
180 | { |
181 | unsigned long orig_jiffies = jiffies; |
182 | unsigned int temp; |
183 | |
184 | writel(GEN_STOP << 8, addr: lpi2c_imx->base + LPI2C_MTDR); |
185 | |
186 | do { |
187 | temp = readl(addr: lpi2c_imx->base + LPI2C_MSR); |
188 | if (temp & MSR_SDF) |
189 | break; |
190 | |
191 | if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { |
192 | dev_dbg(&lpi2c_imx->adapter.dev, "stop timeout\n" ); |
193 | break; |
194 | } |
195 | schedule(); |
196 | |
197 | } while (1); |
198 | } |
199 | |
200 | /* CLKLO = I2C_CLK_RATIO * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2 */ |
201 | static int lpi2c_imx_config(struct lpi2c_imx_struct *lpi2c_imx) |
202 | { |
203 | u8 prescale, filt, sethold, datavd; |
204 | unsigned int clk_rate, clk_cycle, clkhi, clklo; |
205 | enum lpi2c_imx_pincfg pincfg; |
206 | unsigned int temp; |
207 | |
208 | lpi2c_imx_set_mode(lpi2c_imx); |
209 | |
210 | clk_rate = clk_get_rate(clk: lpi2c_imx->clks[0].clk); |
211 | if (!clk_rate) |
212 | return -EINVAL; |
213 | |
214 | if (lpi2c_imx->mode == HS || lpi2c_imx->mode == ULTRA_FAST) |
215 | filt = 0; |
216 | else |
217 | filt = 2; |
218 | |
219 | for (prescale = 0; prescale <= 7; prescale++) { |
220 | clk_cycle = clk_rate / ((1 << prescale) * lpi2c_imx->bitrate) |
221 | - 3 - (filt >> 1); |
222 | clkhi = DIV_ROUND_UP(clk_cycle, I2C_CLK_RATIO + 1); |
223 | clklo = clk_cycle - clkhi; |
224 | if (clklo < 64) |
225 | break; |
226 | } |
227 | |
228 | if (prescale > 7) |
229 | return -EINVAL; |
230 | |
231 | /* set MCFGR1: PINCFG, PRESCALE, IGNACK */ |
232 | if (lpi2c_imx->mode == ULTRA_FAST) |
233 | pincfg = TWO_PIN_OO; |
234 | else |
235 | pincfg = TWO_PIN_OD; |
236 | temp = prescale | pincfg << 24; |
237 | |
238 | if (lpi2c_imx->mode == ULTRA_FAST) |
239 | temp |= MCFGR1_IGNACK; |
240 | |
241 | writel(val: temp, addr: lpi2c_imx->base + LPI2C_MCFGR1); |
242 | |
243 | /* set MCFGR2: FILTSDA, FILTSCL */ |
244 | temp = (filt << 16) | (filt << 24); |
245 | writel(val: temp, addr: lpi2c_imx->base + LPI2C_MCFGR2); |
246 | |
247 | /* set MCCR: DATAVD, SETHOLD, CLKHI, CLKLO */ |
248 | sethold = clkhi; |
249 | datavd = clkhi >> 1; |
250 | temp = datavd << 24 | sethold << 16 | clkhi << 8 | clklo; |
251 | |
252 | if (lpi2c_imx->mode == HS) |
253 | writel(val: temp, addr: lpi2c_imx->base + LPI2C_MCCR1); |
254 | else |
255 | writel(val: temp, addr: lpi2c_imx->base + LPI2C_MCCR0); |
256 | |
257 | return 0; |
258 | } |
259 | |
260 | static int lpi2c_imx_master_enable(struct lpi2c_imx_struct *lpi2c_imx) |
261 | { |
262 | unsigned int temp; |
263 | int ret; |
264 | |
265 | ret = pm_runtime_resume_and_get(dev: lpi2c_imx->adapter.dev.parent); |
266 | if (ret < 0) |
267 | return ret; |
268 | |
269 | temp = MCR_RST; |
270 | writel(val: temp, addr: lpi2c_imx->base + LPI2C_MCR); |
271 | writel(val: 0, addr: lpi2c_imx->base + LPI2C_MCR); |
272 | |
273 | ret = lpi2c_imx_config(lpi2c_imx); |
274 | if (ret) |
275 | goto rpm_put; |
276 | |
277 | temp = readl(addr: lpi2c_imx->base + LPI2C_MCR); |
278 | temp |= MCR_MEN; |
279 | writel(val: temp, addr: lpi2c_imx->base + LPI2C_MCR); |
280 | |
281 | return 0; |
282 | |
283 | rpm_put: |
284 | pm_runtime_mark_last_busy(dev: lpi2c_imx->adapter.dev.parent); |
285 | pm_runtime_put_autosuspend(dev: lpi2c_imx->adapter.dev.parent); |
286 | |
287 | return ret; |
288 | } |
289 | |
290 | static int lpi2c_imx_master_disable(struct lpi2c_imx_struct *lpi2c_imx) |
291 | { |
292 | u32 temp; |
293 | |
294 | temp = readl(addr: lpi2c_imx->base + LPI2C_MCR); |
295 | temp &= ~MCR_MEN; |
296 | writel(val: temp, addr: lpi2c_imx->base + LPI2C_MCR); |
297 | |
298 | pm_runtime_mark_last_busy(dev: lpi2c_imx->adapter.dev.parent); |
299 | pm_runtime_put_autosuspend(dev: lpi2c_imx->adapter.dev.parent); |
300 | |
301 | return 0; |
302 | } |
303 | |
304 | static int lpi2c_imx_msg_complete(struct lpi2c_imx_struct *lpi2c_imx) |
305 | { |
306 | unsigned long timeout; |
307 | |
308 | timeout = wait_for_completion_timeout(x: &lpi2c_imx->complete, HZ); |
309 | |
310 | return timeout ? 0 : -ETIMEDOUT; |
311 | } |
312 | |
313 | static int lpi2c_imx_txfifo_empty(struct lpi2c_imx_struct *lpi2c_imx) |
314 | { |
315 | unsigned long orig_jiffies = jiffies; |
316 | u32 txcnt; |
317 | |
318 | do { |
319 | txcnt = readl(addr: lpi2c_imx->base + LPI2C_MFSR) & 0xff; |
320 | |
321 | if (readl(addr: lpi2c_imx->base + LPI2C_MSR) & MSR_NDF) { |
322 | dev_dbg(&lpi2c_imx->adapter.dev, "NDF detected\n" ); |
323 | return -EIO; |
324 | } |
325 | |
326 | if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { |
327 | dev_dbg(&lpi2c_imx->adapter.dev, "txfifo empty timeout\n" ); |
328 | return -ETIMEDOUT; |
329 | } |
330 | schedule(); |
331 | |
332 | } while (txcnt); |
333 | |
334 | return 0; |
335 | } |
336 | |
337 | static void lpi2c_imx_set_tx_watermark(struct lpi2c_imx_struct *lpi2c_imx) |
338 | { |
339 | writel(val: lpi2c_imx->txfifosize >> 1, addr: lpi2c_imx->base + LPI2C_MFCR); |
340 | } |
341 | |
342 | static void lpi2c_imx_set_rx_watermark(struct lpi2c_imx_struct *lpi2c_imx) |
343 | { |
344 | unsigned int temp, remaining; |
345 | |
346 | remaining = lpi2c_imx->msglen - lpi2c_imx->delivered; |
347 | |
348 | if (remaining > (lpi2c_imx->rxfifosize >> 1)) |
349 | temp = lpi2c_imx->rxfifosize >> 1; |
350 | else |
351 | temp = 0; |
352 | |
353 | writel(val: temp << 16, addr: lpi2c_imx->base + LPI2C_MFCR); |
354 | } |
355 | |
356 | static void lpi2c_imx_write_txfifo(struct lpi2c_imx_struct *lpi2c_imx) |
357 | { |
358 | unsigned int data, txcnt; |
359 | |
360 | txcnt = readl(addr: lpi2c_imx->base + LPI2C_MFSR) & 0xff; |
361 | |
362 | while (txcnt < lpi2c_imx->txfifosize) { |
363 | if (lpi2c_imx->delivered == lpi2c_imx->msglen) |
364 | break; |
365 | |
366 | data = lpi2c_imx->tx_buf[lpi2c_imx->delivered++]; |
367 | writel(val: data, addr: lpi2c_imx->base + LPI2C_MTDR); |
368 | txcnt++; |
369 | } |
370 | |
371 | if (lpi2c_imx->delivered < lpi2c_imx->msglen) |
372 | lpi2c_imx_intctrl(lpi2c_imx, MIER_TDIE | MIER_NDIE); |
373 | else |
374 | complete(&lpi2c_imx->complete); |
375 | } |
376 | |
377 | static void lpi2c_imx_read_rxfifo(struct lpi2c_imx_struct *lpi2c_imx) |
378 | { |
379 | unsigned int blocklen, remaining; |
380 | unsigned int temp, data; |
381 | |
382 | do { |
383 | data = readl(addr: lpi2c_imx->base + LPI2C_MRDR); |
384 | if (data & MRDR_RXEMPTY) |
385 | break; |
386 | |
387 | lpi2c_imx->rx_buf[lpi2c_imx->delivered++] = data & 0xff; |
388 | } while (1); |
389 | |
390 | /* |
391 | * First byte is the length of remaining packet in the SMBus block |
392 | * data read. Add it to msgs->len. |
393 | */ |
394 | if (lpi2c_imx->block_data) { |
395 | blocklen = lpi2c_imx->rx_buf[0]; |
396 | lpi2c_imx->msglen += blocklen; |
397 | } |
398 | |
399 | remaining = lpi2c_imx->msglen - lpi2c_imx->delivered; |
400 | |
401 | if (!remaining) { |
402 | complete(&lpi2c_imx->complete); |
403 | return; |
404 | } |
405 | |
406 | /* not finished, still waiting for rx data */ |
407 | lpi2c_imx_set_rx_watermark(lpi2c_imx); |
408 | |
409 | /* multiple receive commands */ |
410 | if (lpi2c_imx->block_data) { |
411 | lpi2c_imx->block_data = 0; |
412 | temp = remaining; |
413 | temp |= (RECV_DATA << 8); |
414 | writel(val: temp, addr: lpi2c_imx->base + LPI2C_MTDR); |
415 | } else if (!(lpi2c_imx->delivered & 0xff)) { |
416 | temp = (remaining > CHUNK_DATA ? CHUNK_DATA : remaining) - 1; |
417 | temp |= (RECV_DATA << 8); |
418 | writel(val: temp, addr: lpi2c_imx->base + LPI2C_MTDR); |
419 | } |
420 | |
421 | lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE); |
422 | } |
423 | |
424 | static void lpi2c_imx_write(struct lpi2c_imx_struct *lpi2c_imx, |
425 | struct i2c_msg *msgs) |
426 | { |
427 | lpi2c_imx->tx_buf = msgs->buf; |
428 | lpi2c_imx_set_tx_watermark(lpi2c_imx); |
429 | lpi2c_imx_write_txfifo(lpi2c_imx); |
430 | } |
431 | |
432 | static void lpi2c_imx_read(struct lpi2c_imx_struct *lpi2c_imx, |
433 | struct i2c_msg *msgs) |
434 | { |
435 | unsigned int temp; |
436 | |
437 | lpi2c_imx->rx_buf = msgs->buf; |
438 | lpi2c_imx->block_data = msgs->flags & I2C_M_RECV_LEN; |
439 | |
440 | lpi2c_imx_set_rx_watermark(lpi2c_imx); |
441 | temp = msgs->len > CHUNK_DATA ? CHUNK_DATA - 1 : msgs->len - 1; |
442 | temp |= (RECV_DATA << 8); |
443 | writel(val: temp, addr: lpi2c_imx->base + LPI2C_MTDR); |
444 | |
445 | lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE | MIER_NDIE); |
446 | } |
447 | |
448 | static int lpi2c_imx_xfer(struct i2c_adapter *adapter, |
449 | struct i2c_msg *msgs, int num) |
450 | { |
451 | struct lpi2c_imx_struct *lpi2c_imx = i2c_get_adapdata(adap: adapter); |
452 | unsigned int temp; |
453 | int i, result; |
454 | |
455 | result = lpi2c_imx_master_enable(lpi2c_imx); |
456 | if (result) |
457 | return result; |
458 | |
459 | for (i = 0; i < num; i++) { |
460 | result = lpi2c_imx_start(lpi2c_imx, msgs: &msgs[i]); |
461 | if (result) |
462 | goto disable; |
463 | |
464 | /* quick smbus */ |
465 | if (num == 1 && msgs[0].len == 0) |
466 | goto stop; |
467 | |
468 | lpi2c_imx->rx_buf = NULL; |
469 | lpi2c_imx->tx_buf = NULL; |
470 | lpi2c_imx->delivered = 0; |
471 | lpi2c_imx->msglen = msgs[i].len; |
472 | init_completion(x: &lpi2c_imx->complete); |
473 | |
474 | if (msgs[i].flags & I2C_M_RD) |
475 | lpi2c_imx_read(lpi2c_imx, msgs: &msgs[i]); |
476 | else |
477 | lpi2c_imx_write(lpi2c_imx, msgs: &msgs[i]); |
478 | |
479 | result = lpi2c_imx_msg_complete(lpi2c_imx); |
480 | if (result) |
481 | goto stop; |
482 | |
483 | if (!(msgs[i].flags & I2C_M_RD)) { |
484 | result = lpi2c_imx_txfifo_empty(lpi2c_imx); |
485 | if (result) |
486 | goto stop; |
487 | } |
488 | } |
489 | |
490 | stop: |
491 | lpi2c_imx_stop(lpi2c_imx); |
492 | |
493 | temp = readl(addr: lpi2c_imx->base + LPI2C_MSR); |
494 | if ((temp & MSR_NDF) && !result) |
495 | result = -EIO; |
496 | |
497 | disable: |
498 | lpi2c_imx_master_disable(lpi2c_imx); |
499 | |
500 | dev_dbg(&lpi2c_imx->adapter.dev, "<%s> exit with: %s: %d\n" , __func__, |
501 | (result < 0) ? "error" : "success msg" , |
502 | (result < 0) ? result : num); |
503 | |
504 | return (result < 0) ? result : num; |
505 | } |
506 | |
507 | static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id) |
508 | { |
509 | struct lpi2c_imx_struct *lpi2c_imx = dev_id; |
510 | unsigned int enabled; |
511 | unsigned int temp; |
512 | |
513 | enabled = readl(addr: lpi2c_imx->base + LPI2C_MIER); |
514 | |
515 | lpi2c_imx_intctrl(lpi2c_imx, enable: 0); |
516 | temp = readl(addr: lpi2c_imx->base + LPI2C_MSR); |
517 | temp &= enabled; |
518 | |
519 | if (temp & MSR_NDF) |
520 | complete(&lpi2c_imx->complete); |
521 | else if (temp & MSR_RDF) |
522 | lpi2c_imx_read_rxfifo(lpi2c_imx); |
523 | else if (temp & MSR_TDF) |
524 | lpi2c_imx_write_txfifo(lpi2c_imx); |
525 | |
526 | return IRQ_HANDLED; |
527 | } |
528 | |
529 | static u32 lpi2c_imx_func(struct i2c_adapter *adapter) |
530 | { |
531 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | |
532 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; |
533 | } |
534 | |
535 | static const struct i2c_algorithm lpi2c_imx_algo = { |
536 | .master_xfer = lpi2c_imx_xfer, |
537 | .functionality = lpi2c_imx_func, |
538 | }; |
539 | |
540 | static const struct of_device_id lpi2c_imx_of_match[] = { |
541 | { .compatible = "fsl,imx7ulp-lpi2c" }, |
542 | { }, |
543 | }; |
544 | MODULE_DEVICE_TABLE(of, lpi2c_imx_of_match); |
545 | |
546 | static int lpi2c_imx_probe(struct platform_device *pdev) |
547 | { |
548 | struct lpi2c_imx_struct *lpi2c_imx; |
549 | unsigned int temp; |
550 | int irq, ret; |
551 | |
552 | lpi2c_imx = devm_kzalloc(dev: &pdev->dev, size: sizeof(*lpi2c_imx), GFP_KERNEL); |
553 | if (!lpi2c_imx) |
554 | return -ENOMEM; |
555 | |
556 | lpi2c_imx->base = devm_platform_ioremap_resource(pdev, index: 0); |
557 | if (IS_ERR(ptr: lpi2c_imx->base)) |
558 | return PTR_ERR(ptr: lpi2c_imx->base); |
559 | |
560 | irq = platform_get_irq(pdev, 0); |
561 | if (irq < 0) |
562 | return irq; |
563 | |
564 | lpi2c_imx->adapter.owner = THIS_MODULE; |
565 | lpi2c_imx->adapter.algo = &lpi2c_imx_algo; |
566 | lpi2c_imx->adapter.dev.parent = &pdev->dev; |
567 | lpi2c_imx->adapter.dev.of_node = pdev->dev.of_node; |
568 | strscpy(p: lpi2c_imx->adapter.name, q: pdev->name, |
569 | size: sizeof(lpi2c_imx->adapter.name)); |
570 | |
571 | ret = devm_clk_bulk_get_all(dev: &pdev->dev, clks: &lpi2c_imx->clks); |
572 | if (ret < 0) |
573 | return dev_err_probe(dev: &pdev->dev, err: ret, fmt: "can't get I2C peripheral clock\n" ); |
574 | lpi2c_imx->num_clks = ret; |
575 | |
576 | ret = of_property_read_u32(np: pdev->dev.of_node, |
577 | propname: "clock-frequency" , out_value: &lpi2c_imx->bitrate); |
578 | if (ret) |
579 | lpi2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; |
580 | |
581 | ret = devm_request_irq(dev: &pdev->dev, irq, handler: lpi2c_imx_isr, irqflags: 0, |
582 | devname: pdev->name, dev_id: lpi2c_imx); |
583 | if (ret) |
584 | return dev_err_probe(dev: &pdev->dev, err: ret, fmt: "can't claim irq %d\n" , irq); |
585 | |
586 | i2c_set_adapdata(adap: &lpi2c_imx->adapter, data: lpi2c_imx); |
587 | platform_set_drvdata(pdev, data: lpi2c_imx); |
588 | |
589 | ret = clk_bulk_prepare_enable(num_clks: lpi2c_imx->num_clks, clks: lpi2c_imx->clks); |
590 | if (ret) |
591 | return ret; |
592 | |
593 | pm_runtime_set_autosuspend_delay(dev: &pdev->dev, I2C_PM_TIMEOUT); |
594 | pm_runtime_use_autosuspend(dev: &pdev->dev); |
595 | pm_runtime_get_noresume(dev: &pdev->dev); |
596 | pm_runtime_set_active(dev: &pdev->dev); |
597 | pm_runtime_enable(dev: &pdev->dev); |
598 | |
599 | temp = readl(addr: lpi2c_imx->base + LPI2C_PARAM); |
600 | lpi2c_imx->txfifosize = 1 << (temp & 0x0f); |
601 | lpi2c_imx->rxfifosize = 1 << ((temp >> 8) & 0x0f); |
602 | |
603 | ret = i2c_add_adapter(adap: &lpi2c_imx->adapter); |
604 | if (ret) |
605 | goto rpm_disable; |
606 | |
607 | pm_runtime_mark_last_busy(dev: &pdev->dev); |
608 | pm_runtime_put_autosuspend(dev: &pdev->dev); |
609 | |
610 | dev_info(&lpi2c_imx->adapter.dev, "LPI2C adapter registered\n" ); |
611 | |
612 | return 0; |
613 | |
614 | rpm_disable: |
615 | pm_runtime_put(dev: &pdev->dev); |
616 | pm_runtime_disable(dev: &pdev->dev); |
617 | pm_runtime_dont_use_autosuspend(dev: &pdev->dev); |
618 | |
619 | return ret; |
620 | } |
621 | |
622 | static void lpi2c_imx_remove(struct platform_device *pdev) |
623 | { |
624 | struct lpi2c_imx_struct *lpi2c_imx = platform_get_drvdata(pdev); |
625 | |
626 | i2c_del_adapter(adap: &lpi2c_imx->adapter); |
627 | |
628 | pm_runtime_disable(dev: &pdev->dev); |
629 | pm_runtime_dont_use_autosuspend(dev: &pdev->dev); |
630 | } |
631 | |
632 | static int __maybe_unused lpi2c_runtime_suspend(struct device *dev) |
633 | { |
634 | struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev); |
635 | |
636 | clk_bulk_disable(num_clks: lpi2c_imx->num_clks, clks: lpi2c_imx->clks); |
637 | pinctrl_pm_select_sleep_state(dev); |
638 | |
639 | return 0; |
640 | } |
641 | |
642 | static int __maybe_unused lpi2c_runtime_resume(struct device *dev) |
643 | { |
644 | struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev); |
645 | int ret; |
646 | |
647 | pinctrl_pm_select_default_state(dev); |
648 | ret = clk_bulk_enable(num_clks: lpi2c_imx->num_clks, clks: lpi2c_imx->clks); |
649 | if (ret) { |
650 | dev_err(dev, "failed to enable I2C clock, ret=%d\n" , ret); |
651 | return ret; |
652 | } |
653 | |
654 | return 0; |
655 | } |
656 | |
657 | static const struct dev_pm_ops lpi2c_pm_ops = { |
658 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
659 | pm_runtime_force_resume) |
660 | SET_RUNTIME_PM_OPS(lpi2c_runtime_suspend, |
661 | lpi2c_runtime_resume, NULL) |
662 | }; |
663 | |
664 | static struct platform_driver lpi2c_imx_driver = { |
665 | .probe = lpi2c_imx_probe, |
666 | .remove_new = lpi2c_imx_remove, |
667 | .driver = { |
668 | .name = DRIVER_NAME, |
669 | .of_match_table = lpi2c_imx_of_match, |
670 | .pm = &lpi2c_pm_ops, |
671 | }, |
672 | }; |
673 | |
674 | module_platform_driver(lpi2c_imx_driver); |
675 | |
676 | MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>" ); |
677 | MODULE_DESCRIPTION("I2C adapter driver for LPI2C bus" ); |
678 | MODULE_LICENSE("GPL" ); |
679 | |