1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * Copyright (C) 2002 Motorola GSG-China |
4 | * |
5 | * Author: |
6 | * Darius Augulis, Teltonika Inc. |
7 | * |
8 | * Desc.: |
9 | * Implementation of I2C Adapter/Algorithm Driver |
10 | * for I2C Bus integrated in Freescale i.MX/MXC processors |
11 | * |
12 | * Derived from Motorola GSG China I2C example driver |
13 | * |
14 | * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de |
15 | * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de |
16 | * Copyright (C) 2007 RightHand Technologies, Inc. |
17 | * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> |
18 | * |
19 | * Copyright 2013 Freescale Semiconductor, Inc. |
20 | * Copyright 2020 NXP |
21 | * |
22 | */ |
23 | |
24 | #include <linux/acpi.h> |
25 | #include <linux/clk.h> |
26 | #include <linux/completion.h> |
27 | #include <linux/delay.h> |
28 | #include <linux/dma-mapping.h> |
29 | #include <linux/dmaengine.h> |
30 | #include <linux/dmapool.h> |
31 | #include <linux/err.h> |
32 | #include <linux/errno.h> |
33 | #include <linux/gpio/consumer.h> |
34 | #include <linux/i2c.h> |
35 | #include <linux/init.h> |
36 | #include <linux/interrupt.h> |
37 | #include <linux/io.h> |
38 | #include <linux/iopoll.h> |
39 | #include <linux/kernel.h> |
40 | #include <linux/spinlock.h> |
41 | #include <linux/hrtimer.h> |
42 | #include <linux/module.h> |
43 | #include <linux/of.h> |
44 | #include <linux/of_dma.h> |
45 | #include <linux/pinctrl/consumer.h> |
46 | #include <linux/platform_data/i2c-imx.h> |
47 | #include <linux/platform_device.h> |
48 | #include <linux/pm_runtime.h> |
49 | #include <linux/sched.h> |
50 | #include <linux/slab.h> |
51 | |
52 | /* This will be the driver name the kernel reports */ |
53 | #define DRIVER_NAME "imx-i2c" |
54 | |
55 | #define I2C_IMX_CHECK_DELAY 30000 /* Time to check for bus idle, in NS */ |
56 | |
57 | /* |
58 | * Enable DMA if transfer byte size is bigger than this threshold. |
59 | * As the hardware request, it must bigger than 4 bytes.\ |
60 | * I have set '16' here, maybe it's not the best but I think it's |
61 | * the appropriate. |
62 | */ |
63 | #define DMA_THRESHOLD 16 |
64 | #define DMA_TIMEOUT 1000 |
65 | |
66 | /* IMX I2C registers: |
67 | * the I2C register offset is different between SoCs, |
68 | * to provide support for all these chips, split the |
69 | * register offset into a fixed base address and a |
70 | * variable shift value, then the full register offset |
71 | * will be calculated by |
72 | * reg_off = ( reg_base_addr << reg_shift) |
73 | */ |
74 | #define IMX_I2C_IADR 0x00 /* i2c slave address */ |
75 | #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ |
76 | #define IMX_I2C_I2CR 0x02 /* i2c control */ |
77 | #define IMX_I2C_I2SR 0x03 /* i2c status */ |
78 | #define IMX_I2C_I2DR 0x04 /* i2c transfer data */ |
79 | |
80 | /* |
81 | * All of the layerscape series SoCs support IBIC register. |
82 | */ |
83 | #define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */ |
84 | |
85 | #define IMX_I2C_REGSHIFT 2 |
86 | #define VF610_I2C_REGSHIFT 0 |
87 | |
88 | /* Bits of IMX I2C registers */ |
89 | #define I2SR_RXAK 0x01 |
90 | #define I2SR_IIF 0x02 |
91 | #define I2SR_SRW 0x04 |
92 | #define I2SR_IAL 0x10 |
93 | #define I2SR_IBB 0x20 |
94 | #define I2SR_IAAS 0x40 |
95 | #define I2SR_ICF 0x80 |
96 | #define I2CR_DMAEN 0x02 |
97 | #define I2CR_RSTA 0x04 |
98 | #define I2CR_TXAK 0x08 |
99 | #define I2CR_MTX 0x10 |
100 | #define I2CR_MSTA 0x20 |
101 | #define I2CR_IIEN 0x40 |
102 | #define I2CR_IEN 0x80 |
103 | #define IBIC_BIIE 0x80 /* Bus idle interrupt enable */ |
104 | |
105 | /* register bits different operating codes definition: |
106 | * 1) I2SR: Interrupt flags clear operation differ between SoCs: |
107 | * - write zero to clear(w0c) INT flag on i.MX, |
108 | * - but write one to clear(w1c) INT flag on Vybrid. |
109 | * 2) I2CR: I2C module enable operation also differ between SoCs: |
110 | * - set I2CR_IEN bit enable the module on i.MX, |
111 | * - but clear I2CR_IEN bit enable the module on Vybrid. |
112 | */ |
113 | #define I2SR_CLR_OPCODE_W0C 0x0 |
114 | #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) |
115 | #define I2CR_IEN_OPCODE_0 0x0 |
116 | #define I2CR_IEN_OPCODE_1 I2CR_IEN |
117 | |
118 | #define I2C_PM_TIMEOUT 10 /* ms */ |
119 | |
120 | /* |
121 | * sorted list of clock divider, register value pairs |
122 | * taken from table 26-5, p.26-9, Freescale i.MX |
123 | * Integrated Portable System Processor Reference Manual |
124 | * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 |
125 | * |
126 | * Duplicated divider values removed from list |
127 | */ |
128 | struct imx_i2c_clk_pair { |
129 | u16 div; |
130 | u16 val; |
131 | }; |
132 | |
133 | static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { |
134 | { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, |
135 | { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, |
136 | { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, |
137 | { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, |
138 | { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, |
139 | { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, |
140 | { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, |
141 | { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, |
142 | { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, |
143 | { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, |
144 | { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, |
145 | { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, |
146 | { 3072, 0x1E }, { 3840, 0x1F } |
147 | }; |
148 | |
149 | /* Vybrid VF610 clock divider, register value pairs */ |
150 | static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { |
151 | { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, |
152 | { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, |
153 | { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, |
154 | { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, |
155 | { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, |
156 | { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, |
157 | { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, |
158 | { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, |
159 | { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, |
160 | { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, |
161 | { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, |
162 | { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, |
163 | { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, |
164 | { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, |
165 | { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, |
166 | }; |
167 | |
168 | enum imx_i2c_type { |
169 | IMX1_I2C, |
170 | IMX21_I2C, |
171 | VF610_I2C, |
172 | }; |
173 | |
174 | struct imx_i2c_hwdata { |
175 | enum imx_i2c_type devtype; |
176 | unsigned int regshift; |
177 | struct imx_i2c_clk_pair *clk_div; |
178 | unsigned int ndivs; |
179 | unsigned int i2sr_clr_opcode; |
180 | unsigned int i2cr_ien_opcode; |
181 | /* |
182 | * Errata ERR007805 or e7805: |
183 | * I2C: When the I2C clock speed is configured for 400 kHz, |
184 | * the SCL low period violates the I2C spec of 1.3 uS min. |
185 | */ |
186 | bool has_err007805; |
187 | }; |
188 | |
189 | struct imx_i2c_dma { |
190 | struct dma_chan *chan_tx; |
191 | struct dma_chan *chan_rx; |
192 | struct dma_chan *chan_using; |
193 | struct completion cmd_complete; |
194 | dma_addr_t dma_buf; |
195 | unsigned int dma_len; |
196 | enum dma_transfer_direction dma_transfer_dir; |
197 | enum dma_data_direction dma_data_dir; |
198 | }; |
199 | |
200 | struct imx_i2c_struct { |
201 | struct i2c_adapter adapter; |
202 | struct clk *clk; |
203 | struct notifier_block clk_change_nb; |
204 | void __iomem *base; |
205 | wait_queue_head_t queue; |
206 | unsigned long i2csr; |
207 | unsigned int disable_delay; |
208 | int stopped; |
209 | unsigned int ifdr; /* IMX_I2C_IFDR */ |
210 | unsigned int cur_clk; |
211 | unsigned int bitrate; |
212 | const struct imx_i2c_hwdata *hwdata; |
213 | struct i2c_bus_recovery_info rinfo; |
214 | |
215 | struct pinctrl *pinctrl; |
216 | struct pinctrl_state *pinctrl_pins_default; |
217 | struct pinctrl_state *pinctrl_pins_gpio; |
218 | |
219 | struct imx_i2c_dma *dma; |
220 | struct i2c_client *slave; |
221 | enum i2c_slave_event last_slave_event; |
222 | |
223 | /* For checking slave events. */ |
224 | spinlock_t slave_lock; |
225 | struct hrtimer slave_timer; |
226 | }; |
227 | |
228 | static const struct imx_i2c_hwdata imx1_i2c_hwdata = { |
229 | .devtype = IMX1_I2C, |
230 | .regshift = IMX_I2C_REGSHIFT, |
231 | .clk_div = imx_i2c_clk_div, |
232 | .ndivs = ARRAY_SIZE(imx_i2c_clk_div), |
233 | .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, |
234 | .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, |
235 | |
236 | }; |
237 | |
238 | static const struct imx_i2c_hwdata imx21_i2c_hwdata = { |
239 | .devtype = IMX21_I2C, |
240 | .regshift = IMX_I2C_REGSHIFT, |
241 | .clk_div = imx_i2c_clk_div, |
242 | .ndivs = ARRAY_SIZE(imx_i2c_clk_div), |
243 | .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, |
244 | .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, |
245 | |
246 | }; |
247 | |
248 | static const struct imx_i2c_hwdata imx6_i2c_hwdata = { |
249 | .devtype = IMX21_I2C, |
250 | .regshift = IMX_I2C_REGSHIFT, |
251 | .clk_div = imx_i2c_clk_div, |
252 | .ndivs = ARRAY_SIZE(imx_i2c_clk_div), |
253 | .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, |
254 | .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, |
255 | .has_err007805 = true, |
256 | }; |
257 | |
258 | static struct imx_i2c_hwdata vf610_i2c_hwdata = { |
259 | .devtype = VF610_I2C, |
260 | .regshift = VF610_I2C_REGSHIFT, |
261 | .clk_div = vf610_i2c_clk_div, |
262 | .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), |
263 | .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, |
264 | .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, |
265 | |
266 | }; |
267 | |
268 | static const struct platform_device_id imx_i2c_devtype[] = { |
269 | { |
270 | .name = "imx1-i2c" , |
271 | .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, |
272 | }, { |
273 | .name = "imx21-i2c" , |
274 | .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, |
275 | }, { |
276 | /* sentinel */ |
277 | } |
278 | }; |
279 | MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); |
280 | |
281 | static const struct of_device_id i2c_imx_dt_ids[] = { |
282 | { .compatible = "fsl,imx1-i2c" , .data = &imx1_i2c_hwdata, }, |
283 | { .compatible = "fsl,imx21-i2c" , .data = &imx21_i2c_hwdata, }, |
284 | { .compatible = "fsl,imx6q-i2c" , .data = &imx6_i2c_hwdata, }, |
285 | { .compatible = "fsl,imx6sl-i2c" , .data = &imx6_i2c_hwdata, }, |
286 | { .compatible = "fsl,imx6sll-i2c" , .data = &imx6_i2c_hwdata, }, |
287 | { .compatible = "fsl,imx6sx-i2c" , .data = &imx6_i2c_hwdata, }, |
288 | { .compatible = "fsl,imx6ul-i2c" , .data = &imx6_i2c_hwdata, }, |
289 | { .compatible = "fsl,imx7s-i2c" , .data = &imx6_i2c_hwdata, }, |
290 | { .compatible = "fsl,imx8mm-i2c" , .data = &imx6_i2c_hwdata, }, |
291 | { .compatible = "fsl,imx8mn-i2c" , .data = &imx6_i2c_hwdata, }, |
292 | { .compatible = "fsl,imx8mp-i2c" , .data = &imx6_i2c_hwdata, }, |
293 | { .compatible = "fsl,imx8mq-i2c" , .data = &imx6_i2c_hwdata, }, |
294 | { .compatible = "fsl,vf610-i2c" , .data = &vf610_i2c_hwdata, }, |
295 | { /* sentinel */ } |
296 | }; |
297 | MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); |
298 | |
299 | static const struct acpi_device_id i2c_imx_acpi_ids[] = { |
300 | {"NXP0001" , .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata}, |
301 | { } |
302 | }; |
303 | MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids); |
304 | |
305 | static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) |
306 | { |
307 | return i2c_imx->hwdata->devtype == IMX1_I2C; |
308 | } |
309 | |
310 | static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx) |
311 | { |
312 | return i2c_imx->hwdata->devtype == VF610_I2C; |
313 | } |
314 | |
315 | static inline void imx_i2c_write_reg(unsigned int val, |
316 | struct imx_i2c_struct *i2c_imx, unsigned int reg) |
317 | { |
318 | writeb(val, addr: i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); |
319 | } |
320 | |
321 | static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, |
322 | unsigned int reg) |
323 | { |
324 | return readb(addr: i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); |
325 | } |
326 | |
327 | static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits) |
328 | { |
329 | unsigned int temp; |
330 | |
331 | /* |
332 | * i2sr_clr_opcode is the value to clear all interrupts. Here we want to |
333 | * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits> |
334 | * toggled. This is required because i.MX needs W0C and Vybrid uses W1C. |
335 | */ |
336 | temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits; |
337 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2SR); |
338 | } |
339 | |
340 | /* Set up i2c controller register and i2c status register to default value. */ |
341 | static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx) |
342 | { |
343 | imx_i2c_write_reg(val: i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, |
344 | i2c_imx, IMX_I2C_I2CR); |
345 | i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); |
346 | } |
347 | |
348 | /* Functions for DMA support */ |
349 | static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, |
350 | dma_addr_t phy_addr) |
351 | { |
352 | struct imx_i2c_dma *dma; |
353 | struct dma_slave_config dma_sconfig; |
354 | struct device *dev = &i2c_imx->adapter.dev; |
355 | int ret; |
356 | |
357 | dma = devm_kzalloc(dev, size: sizeof(*dma), GFP_KERNEL); |
358 | if (!dma) |
359 | return; |
360 | |
361 | dma->chan_tx = dma_request_chan(dev, name: "tx" ); |
362 | if (IS_ERR(ptr: dma->chan_tx)) { |
363 | ret = PTR_ERR(ptr: dma->chan_tx); |
364 | if (ret != -ENODEV && ret != -EPROBE_DEFER) |
365 | dev_err(dev, "can't request DMA tx channel (%d)\n" , ret); |
366 | goto fail_al; |
367 | } |
368 | |
369 | dma_sconfig.dst_addr = phy_addr + |
370 | (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); |
371 | dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
372 | dma_sconfig.dst_maxburst = 1; |
373 | dma_sconfig.direction = DMA_MEM_TO_DEV; |
374 | ret = dmaengine_slave_config(chan: dma->chan_tx, config: &dma_sconfig); |
375 | if (ret < 0) { |
376 | dev_err(dev, "can't configure tx channel (%d)\n" , ret); |
377 | goto fail_tx; |
378 | } |
379 | |
380 | dma->chan_rx = dma_request_chan(dev, name: "rx" ); |
381 | if (IS_ERR(ptr: dma->chan_rx)) { |
382 | ret = PTR_ERR(ptr: dma->chan_rx); |
383 | if (ret != -ENODEV && ret != -EPROBE_DEFER) |
384 | dev_err(dev, "can't request DMA rx channel (%d)\n" , ret); |
385 | goto fail_tx; |
386 | } |
387 | |
388 | dma_sconfig.src_addr = phy_addr + |
389 | (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); |
390 | dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
391 | dma_sconfig.src_maxburst = 1; |
392 | dma_sconfig.direction = DMA_DEV_TO_MEM; |
393 | ret = dmaengine_slave_config(chan: dma->chan_rx, config: &dma_sconfig); |
394 | if (ret < 0) { |
395 | dev_err(dev, "can't configure rx channel (%d)\n" , ret); |
396 | goto fail_rx; |
397 | } |
398 | |
399 | i2c_imx->dma = dma; |
400 | init_completion(x: &dma->cmd_complete); |
401 | dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n" , |
402 | dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); |
403 | |
404 | return; |
405 | |
406 | fail_rx: |
407 | dma_release_channel(chan: dma->chan_rx); |
408 | fail_tx: |
409 | dma_release_channel(chan: dma->chan_tx); |
410 | fail_al: |
411 | devm_kfree(dev, p: dma); |
412 | } |
413 | |
414 | static void i2c_imx_dma_callback(void *arg) |
415 | { |
416 | struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg; |
417 | struct imx_i2c_dma *dma = i2c_imx->dma; |
418 | |
419 | dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf, |
420 | dma->dma_len, dma->dma_data_dir); |
421 | complete(&dma->cmd_complete); |
422 | } |
423 | |
424 | static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx, |
425 | struct i2c_msg *msgs) |
426 | { |
427 | struct imx_i2c_dma *dma = i2c_imx->dma; |
428 | struct dma_async_tx_descriptor *txdesc; |
429 | struct device *dev = &i2c_imx->adapter.dev; |
430 | struct device *chan_dev = dma->chan_using->device->dev; |
431 | |
432 | dma->dma_buf = dma_map_single(chan_dev, msgs->buf, |
433 | dma->dma_len, dma->dma_data_dir); |
434 | if (dma_mapping_error(dev: chan_dev, dma_addr: dma->dma_buf)) { |
435 | dev_err(dev, "DMA mapping failed\n" ); |
436 | goto err_map; |
437 | } |
438 | |
439 | txdesc = dmaengine_prep_slave_single(chan: dma->chan_using, buf: dma->dma_buf, |
440 | len: dma->dma_len, dir: dma->dma_transfer_dir, |
441 | flags: DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
442 | if (!txdesc) { |
443 | dev_err(dev, "Not able to get desc for DMA xfer\n" ); |
444 | goto err_desc; |
445 | } |
446 | |
447 | reinit_completion(x: &dma->cmd_complete); |
448 | txdesc->callback = i2c_imx_dma_callback; |
449 | txdesc->callback_param = i2c_imx; |
450 | if (dma_submit_error(cookie: dmaengine_submit(desc: txdesc))) { |
451 | dev_err(dev, "DMA submit failed\n" ); |
452 | goto err_submit; |
453 | } |
454 | |
455 | dma_async_issue_pending(chan: dma->chan_using); |
456 | return 0; |
457 | |
458 | err_submit: |
459 | dmaengine_terminate_sync(chan: dma->chan_using); |
460 | err_desc: |
461 | dma_unmap_single(chan_dev, dma->dma_buf, |
462 | dma->dma_len, dma->dma_data_dir); |
463 | err_map: |
464 | return -EINVAL; |
465 | } |
466 | |
467 | static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx) |
468 | { |
469 | struct imx_i2c_dma *dma = i2c_imx->dma; |
470 | |
471 | dma->dma_buf = 0; |
472 | dma->dma_len = 0; |
473 | |
474 | dma_release_channel(chan: dma->chan_tx); |
475 | dma->chan_tx = NULL; |
476 | |
477 | dma_release_channel(chan: dma->chan_rx); |
478 | dma->chan_rx = NULL; |
479 | |
480 | dma->chan_using = NULL; |
481 | } |
482 | |
483 | static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic) |
484 | { |
485 | unsigned long orig_jiffies = jiffies; |
486 | unsigned int temp; |
487 | |
488 | while (1) { |
489 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); |
490 | |
491 | /* check for arbitration lost */ |
492 | if (temp & I2SR_IAL) { |
493 | i2c_imx_clear_irq(i2c_imx, I2SR_IAL); |
494 | return -EAGAIN; |
495 | } |
496 | |
497 | if (for_busy && (temp & I2SR_IBB)) { |
498 | i2c_imx->stopped = 0; |
499 | break; |
500 | } |
501 | if (!for_busy && !(temp & I2SR_IBB)) { |
502 | i2c_imx->stopped = 1; |
503 | break; |
504 | } |
505 | if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { |
506 | dev_dbg(&i2c_imx->adapter.dev, |
507 | "<%s> I2C bus is busy\n" , __func__); |
508 | return -ETIMEDOUT; |
509 | } |
510 | if (atomic) |
511 | udelay(100); |
512 | else |
513 | schedule(); |
514 | } |
515 | |
516 | return 0; |
517 | } |
518 | |
519 | static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic) |
520 | { |
521 | if (atomic) { |
522 | void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift); |
523 | unsigned int regval; |
524 | |
525 | /* |
526 | * The formula for the poll timeout is documented in the RM |
527 | * Rev.5 on page 1878: |
528 | * T_min = 10/F_scl |
529 | * Set the value hard as it is done for the non-atomic use-case. |
530 | * Use 10 kHz for the calculation since this is the minimum |
531 | * allowed SMBus frequency. Also add an offset of 100us since it |
532 | * turned out that the I2SR_IIF bit isn't set correctly within |
533 | * the minimum timeout in polling mode. |
534 | */ |
535 | readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100); |
536 | i2c_imx->i2csr = regval; |
537 | i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); |
538 | } else { |
539 | wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); |
540 | } |
541 | |
542 | if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { |
543 | dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n" , __func__); |
544 | return -ETIMEDOUT; |
545 | } |
546 | |
547 | /* check for arbitration lost */ |
548 | if (i2c_imx->i2csr & I2SR_IAL) { |
549 | dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n" , __func__); |
550 | i2c_imx_clear_irq(i2c_imx, I2SR_IAL); |
551 | |
552 | i2c_imx->i2csr = 0; |
553 | return -EAGAIN; |
554 | } |
555 | |
556 | dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n" , __func__); |
557 | i2c_imx->i2csr = 0; |
558 | return 0; |
559 | } |
560 | |
561 | static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) |
562 | { |
563 | if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { |
564 | dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n" , __func__); |
565 | return -ENXIO; /* No ACK */ |
566 | } |
567 | |
568 | dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n" , __func__); |
569 | return 0; |
570 | } |
571 | |
572 | static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, |
573 | unsigned int i2c_clk_rate) |
574 | { |
575 | struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; |
576 | unsigned int div; |
577 | int i; |
578 | |
579 | if (i2c_imx->hwdata->has_err007805 && i2c_imx->bitrate > 384000) { |
580 | dev_dbg(&i2c_imx->adapter.dev, |
581 | "SoC errata ERR007805 or e7805 applies, bus frequency limited from %d Hz to 384000 Hz.\n" , |
582 | i2c_imx->bitrate); |
583 | i2c_imx->bitrate = 384000; |
584 | } |
585 | |
586 | /* Divider value calculation */ |
587 | if (i2c_imx->cur_clk == i2c_clk_rate) |
588 | return; |
589 | |
590 | i2c_imx->cur_clk = i2c_clk_rate; |
591 | |
592 | div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate); |
593 | if (div < i2c_clk_div[0].div) |
594 | i = 0; |
595 | else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) |
596 | i = i2c_imx->hwdata->ndivs - 1; |
597 | else |
598 | for (i = 0; i2c_clk_div[i].div < div; i++) |
599 | ; |
600 | |
601 | /* Store divider value */ |
602 | i2c_imx->ifdr = i2c_clk_div[i].val; |
603 | |
604 | /* |
605 | * There dummy delay is calculated. |
606 | * It should be about one I2C clock period long. |
607 | * This delay is used in I2C bus disable function |
608 | * to fix chip hardware bug. |
609 | */ |
610 | i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div, |
611 | i2c_clk_rate / 2); |
612 | |
613 | #ifdef CONFIG_I2C_DEBUG_BUS |
614 | dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n" , |
615 | i2c_clk_rate, div); |
616 | dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n" , |
617 | i2c_clk_div[i].val, i2c_clk_div[i].div); |
618 | #endif |
619 | } |
620 | |
621 | static int i2c_imx_clk_notifier_call(struct notifier_block *nb, |
622 | unsigned long action, void *data) |
623 | { |
624 | struct clk_notifier_data *ndata = data; |
625 | struct imx_i2c_struct *i2c_imx = container_of(nb, |
626 | struct imx_i2c_struct, |
627 | clk_change_nb); |
628 | |
629 | if (action & POST_RATE_CHANGE) |
630 | i2c_imx_set_clk(i2c_imx, i2c_clk_rate: ndata->new_rate); |
631 | |
632 | return NOTIFY_OK; |
633 | } |
634 | |
635 | static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic) |
636 | { |
637 | unsigned int temp = 0; |
638 | int result; |
639 | |
640 | imx_i2c_write_reg(val: i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); |
641 | /* Enable I2C controller */ |
642 | imx_i2c_write_reg(val: i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); |
643 | imx_i2c_write_reg(val: i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); |
644 | |
645 | /* Wait controller to be stable */ |
646 | if (atomic) |
647 | udelay(50); |
648 | else |
649 | usleep_range(min: 50, max: 150); |
650 | |
651 | /* Start I2C transaction */ |
652 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
653 | temp |= I2CR_MSTA; |
654 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2CR); |
655 | result = i2c_imx_bus_busy(i2c_imx, for_busy: 1, atomic); |
656 | if (result) |
657 | return result; |
658 | |
659 | temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; |
660 | if (atomic) |
661 | temp &= ~I2CR_IIEN; /* Disable interrupt */ |
662 | |
663 | temp &= ~I2CR_DMAEN; |
664 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2CR); |
665 | return result; |
666 | } |
667 | |
668 | static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic) |
669 | { |
670 | unsigned int temp = 0; |
671 | |
672 | if (!i2c_imx->stopped) { |
673 | /* Stop I2C transaction */ |
674 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
675 | if (!(temp & I2CR_MSTA)) |
676 | i2c_imx->stopped = 1; |
677 | temp &= ~(I2CR_MSTA | I2CR_MTX); |
678 | if (i2c_imx->dma) |
679 | temp &= ~I2CR_DMAEN; |
680 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2CR); |
681 | } |
682 | if (is_imx1_i2c(i2c_imx)) { |
683 | /* |
684 | * This delay caused by an i.MXL hardware bug. |
685 | * If no (or too short) delay, no "STOP" bit will be generated. |
686 | */ |
687 | udelay(i2c_imx->disable_delay); |
688 | } |
689 | |
690 | if (!i2c_imx->stopped) |
691 | i2c_imx_bus_busy(i2c_imx, for_busy: 0, atomic); |
692 | |
693 | /* Disable I2C controller */ |
694 | temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, |
695 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2CR); |
696 | } |
697 | |
698 | /* |
699 | * Enable bus idle interrupts |
700 | * Note: IBIC register will be cleared after disabled i2c module. |
701 | * All of layerscape series SoCs support IBIC register. |
702 | */ |
703 | static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx) |
704 | { |
705 | if (is_vf610_i2c(i2c_imx)) { |
706 | unsigned int temp; |
707 | |
708 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC); |
709 | temp |= IBIC_BIIE; |
710 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_IBIC); |
711 | } |
712 | } |
713 | |
714 | static void i2c_imx_slave_event(struct imx_i2c_struct *i2c_imx, |
715 | enum i2c_slave_event event, u8 *val) |
716 | { |
717 | i2c_slave_event(client: i2c_imx->slave, event, val); |
718 | i2c_imx->last_slave_event = event; |
719 | } |
720 | |
721 | static void i2c_imx_slave_finish_op(struct imx_i2c_struct *i2c_imx) |
722 | { |
723 | u8 val = 0; |
724 | |
725 | while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) { |
726 | switch (i2c_imx->last_slave_event) { |
727 | case I2C_SLAVE_READ_REQUESTED: |
728 | i2c_imx_slave_event(i2c_imx, event: I2C_SLAVE_READ_PROCESSED, |
729 | val: &val); |
730 | break; |
731 | |
732 | case I2C_SLAVE_WRITE_REQUESTED: |
733 | case I2C_SLAVE_READ_PROCESSED: |
734 | case I2C_SLAVE_WRITE_RECEIVED: |
735 | i2c_imx_slave_event(i2c_imx, event: I2C_SLAVE_STOP, val: &val); |
736 | break; |
737 | |
738 | case I2C_SLAVE_STOP: |
739 | break; |
740 | } |
741 | } |
742 | } |
743 | |
744 | /* Returns true if the timer should be restarted, false if not. */ |
745 | static irqreturn_t i2c_imx_slave_handle(struct imx_i2c_struct *i2c_imx, |
746 | unsigned int status, unsigned int ctl) |
747 | { |
748 | u8 value = 0; |
749 | |
750 | if (status & I2SR_IAL) { /* Arbitration lost */ |
751 | i2c_imx_clear_irq(i2c_imx, I2SR_IAL); |
752 | if (!(status & I2SR_IAAS)) |
753 | return IRQ_HANDLED; |
754 | } |
755 | |
756 | if (!(status & I2SR_IBB)) { |
757 | /* No master on the bus, that could mean a stop condition. */ |
758 | i2c_imx_slave_finish_op(i2c_imx); |
759 | return IRQ_HANDLED; |
760 | } |
761 | |
762 | if (!(status & I2SR_ICF)) |
763 | /* Data transfer still in progress, ignore this. */ |
764 | goto out; |
765 | |
766 | if (status & I2SR_IAAS) { /* Addressed as a slave */ |
767 | i2c_imx_slave_finish_op(i2c_imx); |
768 | if (status & I2SR_SRW) { /* Master wants to read from us*/ |
769 | dev_dbg(&i2c_imx->adapter.dev, "read requested" ); |
770 | i2c_imx_slave_event(i2c_imx, |
771 | event: I2C_SLAVE_READ_REQUESTED, val: &value); |
772 | |
773 | /* Slave transmit */ |
774 | ctl |= I2CR_MTX; |
775 | imx_i2c_write_reg(val: ctl, i2c_imx, IMX_I2C_I2CR); |
776 | |
777 | /* Send data */ |
778 | imx_i2c_write_reg(val: value, i2c_imx, IMX_I2C_I2DR); |
779 | } else { /* Master wants to write to us */ |
780 | dev_dbg(&i2c_imx->adapter.dev, "write requested" ); |
781 | i2c_imx_slave_event(i2c_imx, |
782 | event: I2C_SLAVE_WRITE_REQUESTED, val: &value); |
783 | |
784 | /* Slave receive */ |
785 | ctl &= ~I2CR_MTX; |
786 | imx_i2c_write_reg(val: ctl, i2c_imx, IMX_I2C_I2CR); |
787 | /* Dummy read */ |
788 | imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); |
789 | } |
790 | } else if (!(ctl & I2CR_MTX)) { /* Receive mode */ |
791 | value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); |
792 | i2c_imx_slave_event(i2c_imx, |
793 | event: I2C_SLAVE_WRITE_RECEIVED, val: &value); |
794 | } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */ |
795 | ctl |= I2CR_MTX; |
796 | imx_i2c_write_reg(val: ctl, i2c_imx, IMX_I2C_I2CR); |
797 | |
798 | i2c_imx_slave_event(i2c_imx, |
799 | event: I2C_SLAVE_READ_PROCESSED, val: &value); |
800 | |
801 | imx_i2c_write_reg(val: value, i2c_imx, IMX_I2C_I2DR); |
802 | } else { /* Transmit mode received NAK, operation is done */ |
803 | ctl &= ~I2CR_MTX; |
804 | imx_i2c_write_reg(val: ctl, i2c_imx, IMX_I2C_I2CR); |
805 | imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); |
806 | i2c_imx_slave_finish_op(i2c_imx); |
807 | return IRQ_HANDLED; |
808 | } |
809 | |
810 | out: |
811 | /* |
812 | * No need to check the return value here. If it returns 0 or |
813 | * 1, then everything is fine. If it returns -1, then the |
814 | * timer is running in the handler. This will still work, |
815 | * though it may be redone (or already have been done) by the |
816 | * timer function. |
817 | */ |
818 | hrtimer_try_to_cancel(timer: &i2c_imx->slave_timer); |
819 | hrtimer_forward_now(timer: &i2c_imx->slave_timer, I2C_IMX_CHECK_DELAY); |
820 | hrtimer_restart(timer: &i2c_imx->slave_timer); |
821 | return IRQ_HANDLED; |
822 | } |
823 | |
824 | static enum hrtimer_restart i2c_imx_slave_timeout(struct hrtimer *t) |
825 | { |
826 | struct imx_i2c_struct *i2c_imx = container_of(t, struct imx_i2c_struct, |
827 | slave_timer); |
828 | unsigned int ctl, status; |
829 | unsigned long flags; |
830 | |
831 | spin_lock_irqsave(&i2c_imx->slave_lock, flags); |
832 | status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); |
833 | ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
834 | i2c_imx_slave_handle(i2c_imx, status, ctl); |
835 | spin_unlock_irqrestore(lock: &i2c_imx->slave_lock, flags); |
836 | return HRTIMER_NORESTART; |
837 | } |
838 | |
839 | static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx) |
840 | { |
841 | int temp; |
842 | |
843 | /* Set slave addr. */ |
844 | imx_i2c_write_reg(val: (i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR); |
845 | |
846 | i2c_imx_reset_regs(i2c_imx); |
847 | |
848 | /* Enable module */ |
849 | temp = i2c_imx->hwdata->i2cr_ien_opcode; |
850 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2CR); |
851 | |
852 | /* Enable interrupt from i2c module */ |
853 | temp |= I2CR_IIEN; |
854 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2CR); |
855 | |
856 | i2c_imx_enable_bus_idle(i2c_imx); |
857 | } |
858 | |
859 | static int i2c_imx_reg_slave(struct i2c_client *client) |
860 | { |
861 | struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adap: client->adapter); |
862 | int ret; |
863 | |
864 | if (i2c_imx->slave) |
865 | return -EBUSY; |
866 | |
867 | i2c_imx->slave = client; |
868 | i2c_imx->last_slave_event = I2C_SLAVE_STOP; |
869 | |
870 | /* Resume */ |
871 | ret = pm_runtime_resume_and_get(dev: i2c_imx->adapter.dev.parent); |
872 | if (ret < 0) { |
873 | dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller" ); |
874 | return ret; |
875 | } |
876 | |
877 | i2c_imx_slave_init(i2c_imx); |
878 | |
879 | return 0; |
880 | } |
881 | |
882 | static int i2c_imx_unreg_slave(struct i2c_client *client) |
883 | { |
884 | struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adap: client->adapter); |
885 | int ret; |
886 | |
887 | if (!i2c_imx->slave) |
888 | return -EINVAL; |
889 | |
890 | /* Reset slave address. */ |
891 | imx_i2c_write_reg(val: 0, i2c_imx, IMX_I2C_IADR); |
892 | |
893 | i2c_imx_reset_regs(i2c_imx); |
894 | |
895 | i2c_imx->slave = NULL; |
896 | |
897 | /* Suspend */ |
898 | ret = pm_runtime_put_sync(dev: i2c_imx->adapter.dev.parent); |
899 | if (ret < 0) |
900 | dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller" ); |
901 | |
902 | return ret; |
903 | } |
904 | |
905 | static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status) |
906 | { |
907 | /* save status register */ |
908 | i2c_imx->i2csr = status; |
909 | wake_up(&i2c_imx->queue); |
910 | |
911 | return IRQ_HANDLED; |
912 | } |
913 | |
914 | static irqreturn_t i2c_imx_isr(int irq, void *dev_id) |
915 | { |
916 | struct imx_i2c_struct *i2c_imx = dev_id; |
917 | unsigned int ctl, status; |
918 | unsigned long flags; |
919 | |
920 | spin_lock_irqsave(&i2c_imx->slave_lock, flags); |
921 | status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); |
922 | ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
923 | |
924 | if (status & I2SR_IIF) { |
925 | i2c_imx_clear_irq(i2c_imx, I2SR_IIF); |
926 | if (i2c_imx->slave) { |
927 | if (!(ctl & I2CR_MSTA)) { |
928 | irqreturn_t ret; |
929 | |
930 | ret = i2c_imx_slave_handle(i2c_imx, |
931 | status, ctl); |
932 | spin_unlock_irqrestore(lock: &i2c_imx->slave_lock, |
933 | flags); |
934 | return ret; |
935 | } |
936 | i2c_imx_slave_finish_op(i2c_imx); |
937 | } |
938 | spin_unlock_irqrestore(lock: &i2c_imx->slave_lock, flags); |
939 | return i2c_imx_master_isr(i2c_imx, status); |
940 | } |
941 | spin_unlock_irqrestore(lock: &i2c_imx->slave_lock, flags); |
942 | |
943 | return IRQ_NONE; |
944 | } |
945 | |
946 | static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, |
947 | struct i2c_msg *msgs) |
948 | { |
949 | int result; |
950 | unsigned long time_left; |
951 | unsigned int temp = 0; |
952 | unsigned long orig_jiffies = jiffies; |
953 | struct imx_i2c_dma *dma = i2c_imx->dma; |
954 | struct device *dev = &i2c_imx->adapter.dev; |
955 | |
956 | dma->chan_using = dma->chan_tx; |
957 | dma->dma_transfer_dir = DMA_MEM_TO_DEV; |
958 | dma->dma_data_dir = DMA_TO_DEVICE; |
959 | dma->dma_len = msgs->len - 1; |
960 | result = i2c_imx_dma_xfer(i2c_imx, msgs); |
961 | if (result) |
962 | return result; |
963 | |
964 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
965 | temp |= I2CR_DMAEN; |
966 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2CR); |
967 | |
968 | /* |
969 | * Write slave address. |
970 | * The first byte must be transmitted by the CPU. |
971 | */ |
972 | imx_i2c_write_reg(val: i2c_8bit_addr_from_msg(msg: msgs), i2c_imx, IMX_I2C_I2DR); |
973 | time_left = wait_for_completion_timeout( |
974 | x: &i2c_imx->dma->cmd_complete, |
975 | timeout: msecs_to_jiffies(DMA_TIMEOUT)); |
976 | if (time_left == 0) { |
977 | dmaengine_terminate_sync(chan: dma->chan_using); |
978 | return -ETIMEDOUT; |
979 | } |
980 | |
981 | /* Waiting for transfer complete. */ |
982 | while (1) { |
983 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); |
984 | if (temp & I2SR_ICF) |
985 | break; |
986 | if (time_after(jiffies, orig_jiffies + |
987 | msecs_to_jiffies(DMA_TIMEOUT))) { |
988 | dev_dbg(dev, "<%s> Timeout\n" , __func__); |
989 | return -ETIMEDOUT; |
990 | } |
991 | schedule(); |
992 | } |
993 | |
994 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
995 | temp &= ~I2CR_DMAEN; |
996 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2CR); |
997 | |
998 | /* The last data byte must be transferred by the CPU. */ |
999 | imx_i2c_write_reg(val: msgs->buf[msgs->len-1], |
1000 | i2c_imx, IMX_I2C_I2DR); |
1001 | result = i2c_imx_trx_complete(i2c_imx, atomic: false); |
1002 | if (result) |
1003 | return result; |
1004 | |
1005 | return i2c_imx_acked(i2c_imx); |
1006 | } |
1007 | |
1008 | static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, |
1009 | struct i2c_msg *msgs, bool is_lastmsg) |
1010 | { |
1011 | int result; |
1012 | unsigned long time_left; |
1013 | unsigned int temp; |
1014 | unsigned long orig_jiffies = jiffies; |
1015 | struct imx_i2c_dma *dma = i2c_imx->dma; |
1016 | struct device *dev = &i2c_imx->adapter.dev; |
1017 | |
1018 | |
1019 | dma->chan_using = dma->chan_rx; |
1020 | dma->dma_transfer_dir = DMA_DEV_TO_MEM; |
1021 | dma->dma_data_dir = DMA_FROM_DEVICE; |
1022 | /* The last two data bytes must be transferred by the CPU. */ |
1023 | dma->dma_len = msgs->len - 2; |
1024 | result = i2c_imx_dma_xfer(i2c_imx, msgs); |
1025 | if (result) |
1026 | return result; |
1027 | |
1028 | time_left = wait_for_completion_timeout( |
1029 | x: &i2c_imx->dma->cmd_complete, |
1030 | timeout: msecs_to_jiffies(DMA_TIMEOUT)); |
1031 | if (time_left == 0) { |
1032 | dmaengine_terminate_sync(chan: dma->chan_using); |
1033 | return -ETIMEDOUT; |
1034 | } |
1035 | |
1036 | /* waiting for transfer complete. */ |
1037 | while (1) { |
1038 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); |
1039 | if (temp & I2SR_ICF) |
1040 | break; |
1041 | if (time_after(jiffies, orig_jiffies + |
1042 | msecs_to_jiffies(DMA_TIMEOUT))) { |
1043 | dev_dbg(dev, "<%s> Timeout\n" , __func__); |
1044 | return -ETIMEDOUT; |
1045 | } |
1046 | schedule(); |
1047 | } |
1048 | |
1049 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
1050 | temp &= ~I2CR_DMAEN; |
1051 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2CR); |
1052 | |
1053 | /* read n-1 byte data */ |
1054 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
1055 | temp |= I2CR_TXAK; |
1056 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2CR); |
1057 | |
1058 | msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); |
1059 | /* read n byte data */ |
1060 | result = i2c_imx_trx_complete(i2c_imx, atomic: false); |
1061 | if (result) |
1062 | return result; |
1063 | |
1064 | if (is_lastmsg) { |
1065 | /* |
1066 | * It must generate STOP before read I2DR to prevent |
1067 | * controller from generating another clock cycle |
1068 | */ |
1069 | dev_dbg(dev, "<%s> clear MSTA\n" , __func__); |
1070 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
1071 | if (!(temp & I2CR_MSTA)) |
1072 | i2c_imx->stopped = 1; |
1073 | temp &= ~(I2CR_MSTA | I2CR_MTX); |
1074 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2CR); |
1075 | if (!i2c_imx->stopped) |
1076 | i2c_imx_bus_busy(i2c_imx, for_busy: 0, atomic: false); |
1077 | } else { |
1078 | /* |
1079 | * For i2c master receiver repeat restart operation like: |
1080 | * read -> repeat MSTA -> read/write |
1081 | * The controller must set MTX before read the last byte in |
1082 | * the first read operation, otherwise the first read cost |
1083 | * one extra clock cycle. |
1084 | */ |
1085 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
1086 | temp |= I2CR_MTX; |
1087 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2CR); |
1088 | } |
1089 | msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); |
1090 | |
1091 | return 0; |
1092 | } |
1093 | |
1094 | static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, |
1095 | bool atomic) |
1096 | { |
1097 | int i, result; |
1098 | |
1099 | dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n" , |
1100 | __func__, i2c_8bit_addr_from_msg(msgs)); |
1101 | |
1102 | /* write slave address */ |
1103 | imx_i2c_write_reg(val: i2c_8bit_addr_from_msg(msg: msgs), i2c_imx, IMX_I2C_I2DR); |
1104 | result = i2c_imx_trx_complete(i2c_imx, atomic); |
1105 | if (result) |
1106 | return result; |
1107 | result = i2c_imx_acked(i2c_imx); |
1108 | if (result) |
1109 | return result; |
1110 | dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n" , __func__); |
1111 | |
1112 | /* write data */ |
1113 | for (i = 0; i < msgs->len; i++) { |
1114 | dev_dbg(&i2c_imx->adapter.dev, |
1115 | "<%s> write byte: B%d=0x%X\n" , |
1116 | __func__, i, msgs->buf[i]); |
1117 | imx_i2c_write_reg(val: msgs->buf[i], i2c_imx, IMX_I2C_I2DR); |
1118 | result = i2c_imx_trx_complete(i2c_imx, atomic); |
1119 | if (result) |
1120 | return result; |
1121 | result = i2c_imx_acked(i2c_imx); |
1122 | if (result) |
1123 | return result; |
1124 | } |
1125 | return 0; |
1126 | } |
1127 | |
1128 | static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, |
1129 | bool is_lastmsg, bool atomic) |
1130 | { |
1131 | int i, result; |
1132 | unsigned int temp; |
1133 | int block_data = msgs->flags & I2C_M_RECV_LEN; |
1134 | int use_dma = i2c_imx->dma && msgs->flags & I2C_M_DMA_SAFE && |
1135 | msgs->len >= DMA_THRESHOLD && !block_data; |
1136 | |
1137 | dev_dbg(&i2c_imx->adapter.dev, |
1138 | "<%s> write slave address: addr=0x%x\n" , |
1139 | __func__, i2c_8bit_addr_from_msg(msgs)); |
1140 | |
1141 | /* write slave address */ |
1142 | imx_i2c_write_reg(val: i2c_8bit_addr_from_msg(msg: msgs), i2c_imx, IMX_I2C_I2DR); |
1143 | result = i2c_imx_trx_complete(i2c_imx, atomic); |
1144 | if (result) |
1145 | return result; |
1146 | result = i2c_imx_acked(i2c_imx); |
1147 | if (result) |
1148 | return result; |
1149 | |
1150 | dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n" , __func__); |
1151 | |
1152 | /* setup bus to read data */ |
1153 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
1154 | temp &= ~I2CR_MTX; |
1155 | |
1156 | /* |
1157 | * Reset the I2CR_TXAK flag initially for SMBus block read since the |
1158 | * length is unknown |
1159 | */ |
1160 | if ((msgs->len - 1) || block_data) |
1161 | temp &= ~I2CR_TXAK; |
1162 | if (use_dma) |
1163 | temp |= I2CR_DMAEN; |
1164 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2CR); |
1165 | imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ |
1166 | |
1167 | dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n" , __func__); |
1168 | |
1169 | if (use_dma) |
1170 | return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg); |
1171 | |
1172 | /* read data */ |
1173 | for (i = 0; i < msgs->len; i++) { |
1174 | u8 len = 0; |
1175 | |
1176 | result = i2c_imx_trx_complete(i2c_imx, atomic); |
1177 | if (result) |
1178 | return result; |
1179 | /* |
1180 | * First byte is the length of remaining packet |
1181 | * in the SMBus block data read. Add it to |
1182 | * msgs->len. |
1183 | */ |
1184 | if ((!i) && block_data) { |
1185 | len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); |
1186 | if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) |
1187 | return -EPROTO; |
1188 | dev_dbg(&i2c_imx->adapter.dev, |
1189 | "<%s> read length: 0x%X\n" , |
1190 | __func__, len); |
1191 | msgs->len += len; |
1192 | } |
1193 | if (i == (msgs->len - 1)) { |
1194 | if (is_lastmsg) { |
1195 | /* |
1196 | * It must generate STOP before read I2DR to prevent |
1197 | * controller from generating another clock cycle |
1198 | */ |
1199 | dev_dbg(&i2c_imx->adapter.dev, |
1200 | "<%s> clear MSTA\n" , __func__); |
1201 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
1202 | if (!(temp & I2CR_MSTA)) |
1203 | i2c_imx->stopped = 1; |
1204 | temp &= ~(I2CR_MSTA | I2CR_MTX); |
1205 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2CR); |
1206 | if (!i2c_imx->stopped) |
1207 | i2c_imx_bus_busy(i2c_imx, for_busy: 0, atomic); |
1208 | } else { |
1209 | /* |
1210 | * For i2c master receiver repeat restart operation like: |
1211 | * read -> repeat MSTA -> read/write |
1212 | * The controller must set MTX before read the last byte in |
1213 | * the first read operation, otherwise the first read cost |
1214 | * one extra clock cycle. |
1215 | */ |
1216 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
1217 | temp |= I2CR_MTX; |
1218 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2CR); |
1219 | } |
1220 | } else if (i == (msgs->len - 2)) { |
1221 | dev_dbg(&i2c_imx->adapter.dev, |
1222 | "<%s> set TXAK\n" , __func__); |
1223 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
1224 | temp |= I2CR_TXAK; |
1225 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2CR); |
1226 | } |
1227 | if ((!i) && block_data) |
1228 | msgs->buf[0] = len; |
1229 | else |
1230 | msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); |
1231 | dev_dbg(&i2c_imx->adapter.dev, |
1232 | "<%s> read byte: B%d=0x%X\n" , |
1233 | __func__, i, msgs->buf[i]); |
1234 | } |
1235 | return 0; |
1236 | } |
1237 | |
1238 | static int i2c_imx_xfer_common(struct i2c_adapter *adapter, |
1239 | struct i2c_msg *msgs, int num, bool atomic) |
1240 | { |
1241 | unsigned int i, temp; |
1242 | int result; |
1243 | bool is_lastmsg = false; |
1244 | struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adap: adapter); |
1245 | |
1246 | /* Start I2C transfer */ |
1247 | result = i2c_imx_start(i2c_imx, atomic); |
1248 | if (result) { |
1249 | /* |
1250 | * Bus recovery uses gpiod_get_value_cansleep() which is not |
1251 | * allowed within atomic context. |
1252 | */ |
1253 | if (!atomic && i2c_imx->adapter.bus_recovery_info) { |
1254 | i2c_recover_bus(adap: &i2c_imx->adapter); |
1255 | result = i2c_imx_start(i2c_imx, atomic); |
1256 | } |
1257 | } |
1258 | |
1259 | if (result) |
1260 | goto fail0; |
1261 | |
1262 | /* read/write data */ |
1263 | for (i = 0; i < num; i++) { |
1264 | if (i == num - 1) |
1265 | is_lastmsg = true; |
1266 | |
1267 | if (i) { |
1268 | dev_dbg(&i2c_imx->adapter.dev, |
1269 | "<%s> repeated start\n" , __func__); |
1270 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
1271 | temp |= I2CR_RSTA; |
1272 | imx_i2c_write_reg(val: temp, i2c_imx, IMX_I2C_I2CR); |
1273 | result = i2c_imx_bus_busy(i2c_imx, for_busy: 1, atomic); |
1274 | if (result) |
1275 | goto fail0; |
1276 | } |
1277 | dev_dbg(&i2c_imx->adapter.dev, |
1278 | "<%s> transfer message: %d\n" , __func__, i); |
1279 | /* write/read data */ |
1280 | #ifdef CONFIG_I2C_DEBUG_BUS |
1281 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); |
1282 | dev_dbg(&i2c_imx->adapter.dev, |
1283 | "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n" , |
1284 | __func__, |
1285 | (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), |
1286 | (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), |
1287 | (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); |
1288 | temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); |
1289 | dev_dbg(&i2c_imx->adapter.dev, |
1290 | "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n" , |
1291 | __func__, |
1292 | (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), |
1293 | (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), |
1294 | (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), |
1295 | (temp & I2SR_RXAK ? 1 : 0)); |
1296 | #endif |
1297 | if (msgs[i].flags & I2C_M_RD) { |
1298 | result = i2c_imx_read(i2c_imx, msgs: &msgs[i], is_lastmsg, atomic); |
1299 | } else { |
1300 | if (!atomic && |
1301 | i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD && |
1302 | msgs[i].flags & I2C_M_DMA_SAFE) |
1303 | result = i2c_imx_dma_write(i2c_imx, msgs: &msgs[i]); |
1304 | else |
1305 | result = i2c_imx_write(i2c_imx, msgs: &msgs[i], atomic); |
1306 | } |
1307 | if (result) |
1308 | goto fail0; |
1309 | } |
1310 | |
1311 | fail0: |
1312 | /* Stop I2C transfer */ |
1313 | i2c_imx_stop(i2c_imx, atomic); |
1314 | |
1315 | dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n" , __func__, |
1316 | (result < 0) ? "error" : "success msg" , |
1317 | (result < 0) ? result : num); |
1318 | /* After data is transferred, switch to slave mode(as a receiver) */ |
1319 | if (i2c_imx->slave) |
1320 | i2c_imx_slave_init(i2c_imx); |
1321 | |
1322 | return (result < 0) ? result : num; |
1323 | } |
1324 | |
1325 | static int i2c_imx_xfer(struct i2c_adapter *adapter, |
1326 | struct i2c_msg *msgs, int num) |
1327 | { |
1328 | struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adap: adapter); |
1329 | int result; |
1330 | |
1331 | result = pm_runtime_resume_and_get(dev: i2c_imx->adapter.dev.parent); |
1332 | if (result < 0) |
1333 | return result; |
1334 | |
1335 | result = i2c_imx_xfer_common(adapter, msgs, num, atomic: false); |
1336 | |
1337 | pm_runtime_mark_last_busy(dev: i2c_imx->adapter.dev.parent); |
1338 | pm_runtime_put_autosuspend(dev: i2c_imx->adapter.dev.parent); |
1339 | |
1340 | return result; |
1341 | } |
1342 | |
1343 | static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter, |
1344 | struct i2c_msg *msgs, int num) |
1345 | { |
1346 | struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adap: adapter); |
1347 | int result; |
1348 | |
1349 | result = clk_enable(clk: i2c_imx->clk); |
1350 | if (result) |
1351 | return result; |
1352 | |
1353 | result = i2c_imx_xfer_common(adapter, msgs, num, atomic: true); |
1354 | |
1355 | clk_disable(clk: i2c_imx->clk); |
1356 | |
1357 | return result; |
1358 | } |
1359 | |
1360 | static void i2c_imx_prepare_recovery(struct i2c_adapter *adap) |
1361 | { |
1362 | struct imx_i2c_struct *i2c_imx; |
1363 | |
1364 | i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); |
1365 | |
1366 | pinctrl_select_state(p: i2c_imx->pinctrl, s: i2c_imx->pinctrl_pins_gpio); |
1367 | } |
1368 | |
1369 | static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap) |
1370 | { |
1371 | struct imx_i2c_struct *i2c_imx; |
1372 | |
1373 | i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); |
1374 | |
1375 | pinctrl_select_state(p: i2c_imx->pinctrl, s: i2c_imx->pinctrl_pins_default); |
1376 | } |
1377 | |
1378 | /* |
1379 | * We switch SCL and SDA to their GPIO function and do some bitbanging |
1380 | * for bus recovery. These alternative pinmux settings can be |
1381 | * described in the device tree by a separate pinctrl state "gpio". If |
1382 | * this is missing this is not a big problem, the only implication is |
1383 | * that we can't do bus recovery. |
1384 | */ |
1385 | static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, |
1386 | struct platform_device *pdev) |
1387 | { |
1388 | struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo; |
1389 | |
1390 | i2c_imx->pinctrl = devm_pinctrl_get(dev: &pdev->dev); |
1391 | if (!i2c_imx->pinctrl) { |
1392 | dev_info(&pdev->dev, "pinctrl unavailable, bus recovery not supported\n" ); |
1393 | return 0; |
1394 | } |
1395 | if (IS_ERR(ptr: i2c_imx->pinctrl)) { |
1396 | dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n" ); |
1397 | return PTR_ERR(ptr: i2c_imx->pinctrl); |
1398 | } |
1399 | |
1400 | i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(p: i2c_imx->pinctrl, |
1401 | PINCTRL_STATE_DEFAULT); |
1402 | i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(p: i2c_imx->pinctrl, |
1403 | name: "gpio" ); |
1404 | rinfo->sda_gpiod = devm_gpiod_get(dev: &pdev->dev, con_id: "sda" , flags: GPIOD_IN); |
1405 | rinfo->scl_gpiod = devm_gpiod_get(dev: &pdev->dev, con_id: "scl" , flags: GPIOD_OUT_HIGH_OPEN_DRAIN); |
1406 | |
1407 | if (PTR_ERR(ptr: rinfo->sda_gpiod) == -EPROBE_DEFER || |
1408 | PTR_ERR(ptr: rinfo->scl_gpiod) == -EPROBE_DEFER) { |
1409 | return -EPROBE_DEFER; |
1410 | } else if (IS_ERR(ptr: rinfo->sda_gpiod) || |
1411 | IS_ERR(ptr: rinfo->scl_gpiod) || |
1412 | IS_ERR(ptr: i2c_imx->pinctrl_pins_default) || |
1413 | IS_ERR(ptr: i2c_imx->pinctrl_pins_gpio)) { |
1414 | dev_dbg(&pdev->dev, "recovery information incomplete\n" ); |
1415 | return 0; |
1416 | } |
1417 | |
1418 | dev_dbg(&pdev->dev, "using scl%s for recovery\n" , |
1419 | rinfo->sda_gpiod ? ",sda" : "" ); |
1420 | |
1421 | rinfo->prepare_recovery = i2c_imx_prepare_recovery; |
1422 | rinfo->unprepare_recovery = i2c_imx_unprepare_recovery; |
1423 | rinfo->recover_bus = i2c_generic_scl_recovery; |
1424 | i2c_imx->adapter.bus_recovery_info = rinfo; |
1425 | |
1426 | return 0; |
1427 | } |
1428 | |
1429 | static u32 i2c_imx_func(struct i2c_adapter *adapter) |
1430 | { |
1431 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1432 | | I2C_FUNC_SMBUS_READ_BLOCK_DATA; |
1433 | } |
1434 | |
1435 | static const struct i2c_algorithm i2c_imx_algo = { |
1436 | .master_xfer = i2c_imx_xfer, |
1437 | .master_xfer_atomic = i2c_imx_xfer_atomic, |
1438 | .functionality = i2c_imx_func, |
1439 | .reg_slave = i2c_imx_reg_slave, |
1440 | .unreg_slave = i2c_imx_unreg_slave, |
1441 | }; |
1442 | |
1443 | static int i2c_imx_probe(struct platform_device *pdev) |
1444 | { |
1445 | struct imx_i2c_struct *i2c_imx; |
1446 | struct resource *res; |
1447 | struct imxi2c_platform_data *pdata = dev_get_platdata(dev: &pdev->dev); |
1448 | void __iomem *base; |
1449 | int irq, ret; |
1450 | dma_addr_t phy_addr; |
1451 | const struct imx_i2c_hwdata *match; |
1452 | |
1453 | irq = platform_get_irq(pdev, 0); |
1454 | if (irq < 0) |
1455 | return irq; |
1456 | |
1457 | base = devm_platform_get_and_ioremap_resource(pdev, index: 0, res: &res); |
1458 | if (IS_ERR(ptr: base)) |
1459 | return PTR_ERR(ptr: base); |
1460 | |
1461 | phy_addr = (dma_addr_t)res->start; |
1462 | i2c_imx = devm_kzalloc(dev: &pdev->dev, size: sizeof(*i2c_imx), GFP_KERNEL); |
1463 | if (!i2c_imx) |
1464 | return -ENOMEM; |
1465 | |
1466 | spin_lock_init(&i2c_imx->slave_lock); |
1467 | hrtimer_init(timer: &i2c_imx->slave_timer, CLOCK_MONOTONIC, mode: HRTIMER_MODE_ABS); |
1468 | i2c_imx->slave_timer.function = i2c_imx_slave_timeout; |
1469 | |
1470 | match = device_get_match_data(dev: &pdev->dev); |
1471 | if (match) |
1472 | i2c_imx->hwdata = match; |
1473 | else |
1474 | i2c_imx->hwdata = (struct imx_i2c_hwdata *) |
1475 | platform_get_device_id(pdev)->driver_data; |
1476 | |
1477 | /* Setup i2c_imx driver structure */ |
1478 | strscpy(p: i2c_imx->adapter.name, q: pdev->name, size: sizeof(i2c_imx->adapter.name)); |
1479 | i2c_imx->adapter.owner = THIS_MODULE; |
1480 | i2c_imx->adapter.algo = &i2c_imx_algo; |
1481 | i2c_imx->adapter.dev.parent = &pdev->dev; |
1482 | i2c_imx->adapter.nr = pdev->id; |
1483 | i2c_imx->adapter.dev.of_node = pdev->dev.of_node; |
1484 | i2c_imx->base = base; |
1485 | ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev)); |
1486 | |
1487 | /* Get I2C clock */ |
1488 | i2c_imx->clk = devm_clk_get_enabled(dev: &pdev->dev, NULL); |
1489 | if (IS_ERR(ptr: i2c_imx->clk)) |
1490 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: i2c_imx->clk), |
1491 | fmt: "can't get I2C clock\n" ); |
1492 | |
1493 | /* Init queue */ |
1494 | init_waitqueue_head(&i2c_imx->queue); |
1495 | |
1496 | /* Set up adapter data */ |
1497 | i2c_set_adapdata(adap: &i2c_imx->adapter, data: i2c_imx); |
1498 | |
1499 | /* Set up platform driver data */ |
1500 | platform_set_drvdata(pdev, data: i2c_imx); |
1501 | |
1502 | pm_runtime_set_autosuspend_delay(dev: &pdev->dev, I2C_PM_TIMEOUT); |
1503 | pm_runtime_use_autosuspend(dev: &pdev->dev); |
1504 | pm_runtime_set_active(dev: &pdev->dev); |
1505 | pm_runtime_enable(dev: &pdev->dev); |
1506 | |
1507 | ret = pm_runtime_get_sync(dev: &pdev->dev); |
1508 | if (ret < 0) |
1509 | goto rpm_disable; |
1510 | |
1511 | /* Request IRQ */ |
1512 | ret = request_irq(irq, handler: i2c_imx_isr, IRQF_SHARED, name: pdev->name, dev: i2c_imx); |
1513 | if (ret) { |
1514 | dev_err(&pdev->dev, "can't claim irq %d\n" , irq); |
1515 | goto rpm_disable; |
1516 | } |
1517 | |
1518 | /* Set up clock divider */ |
1519 | i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; |
1520 | ret = of_property_read_u32(np: pdev->dev.of_node, |
1521 | propname: "clock-frequency" , out_value: &i2c_imx->bitrate); |
1522 | if (ret < 0 && pdata && pdata->bitrate) |
1523 | i2c_imx->bitrate = pdata->bitrate; |
1524 | i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; |
1525 | clk_notifier_register(clk: i2c_imx->clk, nb: &i2c_imx->clk_change_nb); |
1526 | i2c_imx_set_clk(i2c_imx, i2c_clk_rate: clk_get_rate(clk: i2c_imx->clk)); |
1527 | |
1528 | i2c_imx_reset_regs(i2c_imx); |
1529 | |
1530 | /* Init optional bus recovery function */ |
1531 | ret = i2c_imx_init_recovery_info(i2c_imx, pdev); |
1532 | /* Give it another chance if pinctrl used is not ready yet */ |
1533 | if (ret == -EPROBE_DEFER) |
1534 | goto clk_notifier_unregister; |
1535 | |
1536 | /* Add I2C adapter */ |
1537 | ret = i2c_add_numbered_adapter(adap: &i2c_imx->adapter); |
1538 | if (ret < 0) |
1539 | goto clk_notifier_unregister; |
1540 | |
1541 | pm_runtime_mark_last_busy(dev: &pdev->dev); |
1542 | pm_runtime_put_autosuspend(dev: &pdev->dev); |
1543 | |
1544 | dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n" , irq); |
1545 | dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n" , res); |
1546 | dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n" , |
1547 | i2c_imx->adapter.name); |
1548 | dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n" ); |
1549 | |
1550 | /* Init DMA config if supported */ |
1551 | i2c_imx_dma_request(i2c_imx, phy_addr); |
1552 | |
1553 | return 0; /* Return OK */ |
1554 | |
1555 | clk_notifier_unregister: |
1556 | clk_notifier_unregister(clk: i2c_imx->clk, nb: &i2c_imx->clk_change_nb); |
1557 | free_irq(irq, i2c_imx); |
1558 | rpm_disable: |
1559 | pm_runtime_put_noidle(dev: &pdev->dev); |
1560 | pm_runtime_disable(dev: &pdev->dev); |
1561 | pm_runtime_set_suspended(dev: &pdev->dev); |
1562 | pm_runtime_dont_use_autosuspend(dev: &pdev->dev); |
1563 | return ret; |
1564 | } |
1565 | |
1566 | static void i2c_imx_remove(struct platform_device *pdev) |
1567 | { |
1568 | struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); |
1569 | int irq, ret; |
1570 | |
1571 | ret = pm_runtime_get_sync(dev: &pdev->dev); |
1572 | |
1573 | hrtimer_cancel(timer: &i2c_imx->slave_timer); |
1574 | |
1575 | /* remove adapter */ |
1576 | dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n" ); |
1577 | i2c_del_adapter(adap: &i2c_imx->adapter); |
1578 | |
1579 | if (i2c_imx->dma) |
1580 | i2c_imx_dma_free(i2c_imx); |
1581 | |
1582 | if (ret >= 0) { |
1583 | /* setup chip registers to defaults */ |
1584 | imx_i2c_write_reg(val: 0, i2c_imx, IMX_I2C_IADR); |
1585 | imx_i2c_write_reg(val: 0, i2c_imx, IMX_I2C_IFDR); |
1586 | imx_i2c_write_reg(val: 0, i2c_imx, IMX_I2C_I2CR); |
1587 | imx_i2c_write_reg(val: 0, i2c_imx, IMX_I2C_I2SR); |
1588 | } |
1589 | |
1590 | clk_notifier_unregister(clk: i2c_imx->clk, nb: &i2c_imx->clk_change_nb); |
1591 | irq = platform_get_irq(pdev, 0); |
1592 | if (irq >= 0) |
1593 | free_irq(irq, i2c_imx); |
1594 | |
1595 | pm_runtime_put_noidle(dev: &pdev->dev); |
1596 | pm_runtime_disable(dev: &pdev->dev); |
1597 | } |
1598 | |
1599 | static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev) |
1600 | { |
1601 | struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); |
1602 | |
1603 | clk_disable(clk: i2c_imx->clk); |
1604 | |
1605 | return 0; |
1606 | } |
1607 | |
1608 | static int __maybe_unused i2c_imx_runtime_resume(struct device *dev) |
1609 | { |
1610 | struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); |
1611 | int ret; |
1612 | |
1613 | ret = clk_enable(clk: i2c_imx->clk); |
1614 | if (ret) |
1615 | dev_err(dev, "can't enable I2C clock, ret=%d\n" , ret); |
1616 | |
1617 | return ret; |
1618 | } |
1619 | |
1620 | static const struct dev_pm_ops i2c_imx_pm_ops = { |
1621 | SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend, |
1622 | i2c_imx_runtime_resume, NULL) |
1623 | }; |
1624 | |
1625 | static struct platform_driver i2c_imx_driver = { |
1626 | .probe = i2c_imx_probe, |
1627 | .remove_new = i2c_imx_remove, |
1628 | .driver = { |
1629 | .name = DRIVER_NAME, |
1630 | .pm = &i2c_imx_pm_ops, |
1631 | .of_match_table = i2c_imx_dt_ids, |
1632 | .acpi_match_table = i2c_imx_acpi_ids, |
1633 | }, |
1634 | .id_table = imx_i2c_devtype, |
1635 | }; |
1636 | |
1637 | static int __init i2c_adap_imx_init(void) |
1638 | { |
1639 | return platform_driver_register(&i2c_imx_driver); |
1640 | } |
1641 | subsys_initcall(i2c_adap_imx_init); |
1642 | |
1643 | static void __exit i2c_adap_imx_exit(void) |
1644 | { |
1645 | platform_driver_unregister(&i2c_imx_driver); |
1646 | } |
1647 | module_exit(i2c_adap_imx_exit); |
1648 | |
1649 | MODULE_LICENSE("GPL" ); |
1650 | MODULE_AUTHOR("Darius Augulis" ); |
1651 | MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus" ); |
1652 | MODULE_ALIAS("platform:" DRIVER_NAME); |
1653 | |