1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2014 MediaTek Inc. |
4 | * Author: Xudong Chen <xudong.chen@mediatek.com> |
5 | */ |
6 | |
7 | #include <linux/clk.h> |
8 | #include <linux/completion.h> |
9 | #include <linux/delay.h> |
10 | #include <linux/device.h> |
11 | #include <linux/dma-mapping.h> |
12 | #include <linux/err.h> |
13 | #include <linux/errno.h> |
14 | #include <linux/i2c.h> |
15 | #include <linux/init.h> |
16 | #include <linux/interrupt.h> |
17 | #include <linux/io.h> |
18 | #include <linux/iopoll.h> |
19 | #include <linux/kernel.h> |
20 | #include <linux/mm.h> |
21 | #include <linux/module.h> |
22 | #include <linux/of.h> |
23 | #include <linux/platform_device.h> |
24 | #include <linux/scatterlist.h> |
25 | #include <linux/sched.h> |
26 | #include <linux/slab.h> |
27 | |
28 | #define I2C_RS_TRANSFER (1 << 4) |
29 | #define I2C_ARB_LOST (1 << 3) |
30 | #define I2C_HS_NACKERR (1 << 2) |
31 | #define I2C_ACKERR (1 << 1) |
32 | #define I2C_TRANSAC_COMP (1 << 0) |
33 | #define I2C_TRANSAC_START (1 << 0) |
34 | #define I2C_RS_MUL_CNFG (1 << 15) |
35 | #define I2C_RS_MUL_TRIG (1 << 14) |
36 | #define I2C_DCM_DISABLE 0x0000 |
37 | #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 |
38 | #define I2C_IO_CONFIG_PUSH_PULL 0x0000 |
39 | #define I2C_SOFT_RST 0x0001 |
40 | #define I2C_HANDSHAKE_RST 0x0020 |
41 | #define I2C_FIFO_ADDR_CLR 0x0001 |
42 | #define I2C_DELAY_LEN 0x0002 |
43 | #define I2C_ST_START_CON 0x8001 |
44 | #define I2C_FS_START_CON 0x1800 |
45 | #define I2C_TIME_CLR_VALUE 0x0000 |
46 | #define I2C_TIME_DEFAULT_VALUE 0x0003 |
47 | #define I2C_WRRD_TRANAC_VALUE 0x0002 |
48 | #define I2C_RD_TRANAC_VALUE 0x0001 |
49 | #define I2C_SCL_MIS_COMP_VALUE 0x0000 |
50 | #define I2C_CHN_CLR_FLAG 0x0000 |
51 | #define I2C_RELIABILITY 0x0010 |
52 | #define I2C_DMAACK_ENABLE 0x0008 |
53 | |
54 | #define I2C_DMA_CON_TX 0x0000 |
55 | #define I2C_DMA_CON_RX 0x0001 |
56 | #define I2C_DMA_ASYNC_MODE 0x0004 |
57 | #define I2C_DMA_SKIP_CONFIG 0x0010 |
58 | #define I2C_DMA_DIR_CHANGE 0x0200 |
59 | #define I2C_DMA_START_EN 0x0001 |
60 | #define I2C_DMA_INT_FLAG_NONE 0x0000 |
61 | #define I2C_DMA_CLR_FLAG 0x0000 |
62 | #define I2C_DMA_WARM_RST 0x0001 |
63 | #define I2C_DMA_HARD_RST 0x0002 |
64 | #define I2C_DMA_HANDSHAKE_RST 0x0004 |
65 | |
66 | #define MAX_SAMPLE_CNT_DIV 8 |
67 | #define MAX_STEP_CNT_DIV 64 |
68 | #define MAX_CLOCK_DIV_8BITS 256 |
69 | #define MAX_CLOCK_DIV_5BITS 32 |
70 | #define MAX_HS_STEP_CNT_DIV 8 |
71 | #define I2C_STANDARD_MODE_BUFFER (1000 / 3) |
72 | #define I2C_FAST_MODE_BUFFER (300 / 3) |
73 | #define I2C_FAST_MODE_PLUS_BUFFER (20 / 3) |
74 | |
75 | #define I2C_CONTROL_RS (0x1 << 1) |
76 | #define I2C_CONTROL_DMA_EN (0x1 << 2) |
77 | #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) |
78 | #define I2C_CONTROL_DIR_CHANGE (0x1 << 4) |
79 | #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) |
80 | #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) |
81 | #define I2C_CONTROL_DMAACK_EN (0x1 << 8) |
82 | #define I2C_CONTROL_ASYNC_MODE (0x1 << 9) |
83 | #define I2C_CONTROL_WRAPPER (0x1 << 0) |
84 | |
85 | #define I2C_DRV_NAME "i2c-mt65xx" |
86 | |
87 | /** |
88 | * enum i2c_mt65xx_clks - Clocks enumeration for MT65XX I2C |
89 | * |
90 | * @I2C_MT65XX_CLK_MAIN: main clock for i2c bus |
91 | * @I2C_MT65XX_CLK_DMA: DMA clock for i2c via DMA |
92 | * @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC |
93 | * @I2C_MT65XX_CLK_ARB: Arbitrator clock for i2c |
94 | * @I2C_MT65XX_CLK_MAX: Number of supported clocks |
95 | */ |
96 | enum i2c_mt65xx_clks { |
97 | I2C_MT65XX_CLK_MAIN = 0, |
98 | I2C_MT65XX_CLK_DMA, |
99 | I2C_MT65XX_CLK_PMIC, |
100 | I2C_MT65XX_CLK_ARB, |
101 | I2C_MT65XX_CLK_MAX |
102 | }; |
103 | |
104 | static const char * const i2c_mt65xx_clk_ids[I2C_MT65XX_CLK_MAX] = { |
105 | "main" , "dma" , "pmic" , "arb" |
106 | }; |
107 | |
108 | enum DMA_REGS_OFFSET { |
109 | OFFSET_INT_FLAG = 0x0, |
110 | OFFSET_INT_EN = 0x04, |
111 | OFFSET_EN = 0x08, |
112 | OFFSET_RST = 0x0c, |
113 | OFFSET_CON = 0x18, |
114 | OFFSET_TX_MEM_ADDR = 0x1c, |
115 | OFFSET_RX_MEM_ADDR = 0x20, |
116 | OFFSET_TX_LEN = 0x24, |
117 | OFFSET_RX_LEN = 0x28, |
118 | OFFSET_TX_4G_MODE = 0x54, |
119 | OFFSET_RX_4G_MODE = 0x58, |
120 | }; |
121 | |
122 | enum i2c_trans_st_rs { |
123 | I2C_TRANS_STOP = 0, |
124 | I2C_TRANS_REPEATED_START, |
125 | }; |
126 | |
127 | enum mtk_trans_op { |
128 | I2C_MASTER_WR = 1, |
129 | I2C_MASTER_RD, |
130 | I2C_MASTER_WRRD, |
131 | }; |
132 | |
133 | enum I2C_REGS_OFFSET { |
134 | OFFSET_DATA_PORT, |
135 | OFFSET_SLAVE_ADDR, |
136 | OFFSET_INTR_MASK, |
137 | OFFSET_INTR_STAT, |
138 | OFFSET_CONTROL, |
139 | OFFSET_TRANSFER_LEN, |
140 | OFFSET_TRANSAC_LEN, |
141 | OFFSET_DELAY_LEN, |
142 | OFFSET_TIMING, |
143 | OFFSET_START, |
144 | OFFSET_EXT_CONF, |
145 | OFFSET_FIFO_STAT, |
146 | OFFSET_FIFO_THRESH, |
147 | OFFSET_FIFO_ADDR_CLR, |
148 | OFFSET_IO_CONFIG, |
149 | OFFSET_RSV_DEBUG, |
150 | OFFSET_HS, |
151 | OFFSET_SOFTRESET, |
152 | OFFSET_DCM_EN, |
153 | OFFSET_MULTI_DMA, |
154 | OFFSET_PATH_DIR, |
155 | OFFSET_DEBUGSTAT, |
156 | OFFSET_DEBUGCTRL, |
157 | OFFSET_TRANSFER_LEN_AUX, |
158 | OFFSET_CLOCK_DIV, |
159 | OFFSET_LTIMING, |
160 | OFFSET_SCL_HIGH_LOW_RATIO, |
161 | OFFSET_HS_SCL_HIGH_LOW_RATIO, |
162 | OFFSET_SCL_MIS_COMP_POINT, |
163 | OFFSET_STA_STO_AC_TIMING, |
164 | OFFSET_HS_STA_STO_AC_TIMING, |
165 | OFFSET_SDA_TIMING, |
166 | }; |
167 | |
168 | static const u16 mt_i2c_regs_v1[] = { |
169 | [OFFSET_DATA_PORT] = 0x0, |
170 | [OFFSET_SLAVE_ADDR] = 0x4, |
171 | [OFFSET_INTR_MASK] = 0x8, |
172 | [OFFSET_INTR_STAT] = 0xc, |
173 | [OFFSET_CONTROL] = 0x10, |
174 | [OFFSET_TRANSFER_LEN] = 0x14, |
175 | [OFFSET_TRANSAC_LEN] = 0x18, |
176 | [OFFSET_DELAY_LEN] = 0x1c, |
177 | [OFFSET_TIMING] = 0x20, |
178 | [OFFSET_START] = 0x24, |
179 | [OFFSET_EXT_CONF] = 0x28, |
180 | [OFFSET_FIFO_STAT] = 0x30, |
181 | [OFFSET_FIFO_THRESH] = 0x34, |
182 | [OFFSET_FIFO_ADDR_CLR] = 0x38, |
183 | [OFFSET_IO_CONFIG] = 0x40, |
184 | [OFFSET_RSV_DEBUG] = 0x44, |
185 | [OFFSET_HS] = 0x48, |
186 | [OFFSET_SOFTRESET] = 0x50, |
187 | [OFFSET_DCM_EN] = 0x54, |
188 | [OFFSET_PATH_DIR] = 0x60, |
189 | [OFFSET_DEBUGSTAT] = 0x64, |
190 | [OFFSET_DEBUGCTRL] = 0x68, |
191 | [OFFSET_TRANSFER_LEN_AUX] = 0x6c, |
192 | [OFFSET_CLOCK_DIV] = 0x70, |
193 | [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74, |
194 | [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78, |
195 | [OFFSET_SCL_MIS_COMP_POINT] = 0x7C, |
196 | [OFFSET_STA_STO_AC_TIMING] = 0x80, |
197 | [OFFSET_HS_STA_STO_AC_TIMING] = 0x84, |
198 | [OFFSET_SDA_TIMING] = 0x88, |
199 | }; |
200 | |
201 | static const u16 mt_i2c_regs_v2[] = { |
202 | [OFFSET_DATA_PORT] = 0x0, |
203 | [OFFSET_SLAVE_ADDR] = 0x4, |
204 | [OFFSET_INTR_MASK] = 0x8, |
205 | [OFFSET_INTR_STAT] = 0xc, |
206 | [OFFSET_CONTROL] = 0x10, |
207 | [OFFSET_TRANSFER_LEN] = 0x14, |
208 | [OFFSET_TRANSAC_LEN] = 0x18, |
209 | [OFFSET_DELAY_LEN] = 0x1c, |
210 | [OFFSET_TIMING] = 0x20, |
211 | [OFFSET_START] = 0x24, |
212 | [OFFSET_EXT_CONF] = 0x28, |
213 | [OFFSET_LTIMING] = 0x2c, |
214 | [OFFSET_HS] = 0x30, |
215 | [OFFSET_IO_CONFIG] = 0x34, |
216 | [OFFSET_FIFO_ADDR_CLR] = 0x38, |
217 | [OFFSET_SDA_TIMING] = 0x3c, |
218 | [OFFSET_TRANSFER_LEN_AUX] = 0x44, |
219 | [OFFSET_CLOCK_DIV] = 0x48, |
220 | [OFFSET_SOFTRESET] = 0x50, |
221 | [OFFSET_MULTI_DMA] = 0x8c, |
222 | [OFFSET_SCL_MIS_COMP_POINT] = 0x90, |
223 | [OFFSET_DEBUGSTAT] = 0xe4, |
224 | [OFFSET_DEBUGCTRL] = 0xe8, |
225 | [OFFSET_FIFO_STAT] = 0xf4, |
226 | [OFFSET_FIFO_THRESH] = 0xf8, |
227 | [OFFSET_DCM_EN] = 0xf88, |
228 | }; |
229 | |
230 | static const u16 mt_i2c_regs_v3[] = { |
231 | [OFFSET_DATA_PORT] = 0x0, |
232 | [OFFSET_INTR_MASK] = 0x8, |
233 | [OFFSET_INTR_STAT] = 0xc, |
234 | [OFFSET_CONTROL] = 0x10, |
235 | [OFFSET_TRANSFER_LEN] = 0x14, |
236 | [OFFSET_TRANSAC_LEN] = 0x18, |
237 | [OFFSET_DELAY_LEN] = 0x1c, |
238 | [OFFSET_TIMING] = 0x20, |
239 | [OFFSET_START] = 0x24, |
240 | [OFFSET_EXT_CONF] = 0x28, |
241 | [OFFSET_LTIMING] = 0x2c, |
242 | [OFFSET_HS] = 0x30, |
243 | [OFFSET_IO_CONFIG] = 0x34, |
244 | [OFFSET_FIFO_ADDR_CLR] = 0x38, |
245 | [OFFSET_SDA_TIMING] = 0x3c, |
246 | [OFFSET_TRANSFER_LEN_AUX] = 0x44, |
247 | [OFFSET_CLOCK_DIV] = 0x48, |
248 | [OFFSET_SOFTRESET] = 0x50, |
249 | [OFFSET_MULTI_DMA] = 0x8c, |
250 | [OFFSET_SCL_MIS_COMP_POINT] = 0x90, |
251 | [OFFSET_SLAVE_ADDR] = 0x94, |
252 | [OFFSET_DEBUGSTAT] = 0xe4, |
253 | [OFFSET_DEBUGCTRL] = 0xe8, |
254 | [OFFSET_FIFO_STAT] = 0xf4, |
255 | [OFFSET_FIFO_THRESH] = 0xf8, |
256 | [OFFSET_DCM_EN] = 0xf88, |
257 | }; |
258 | |
259 | struct mtk_i2c_compatible { |
260 | const struct i2c_adapter_quirks *quirks; |
261 | const u16 *regs; |
262 | unsigned char pmic_i2c: 1; |
263 | unsigned char dcm: 1; |
264 | unsigned char auto_restart: 1; |
265 | unsigned char aux_len_reg: 1; |
266 | unsigned char timing_adjust: 1; |
267 | unsigned char dma_sync: 1; |
268 | unsigned char ltiming_adjust: 1; |
269 | unsigned char apdma_sync: 1; |
270 | unsigned char max_dma_support; |
271 | }; |
272 | |
273 | struct mtk_i2c_ac_timing { |
274 | u16 htiming; |
275 | u16 ltiming; |
276 | u16 hs; |
277 | u16 ext; |
278 | u16 inter_clk_div; |
279 | u16 scl_hl_ratio; |
280 | u16 hs_scl_hl_ratio; |
281 | u16 sta_stop; |
282 | u16 hs_sta_stop; |
283 | u16 sda_timing; |
284 | }; |
285 | |
286 | struct mtk_i2c { |
287 | struct i2c_adapter adap; /* i2c host adapter */ |
288 | struct device *dev; |
289 | struct completion msg_complete; |
290 | struct i2c_timings timing_info; |
291 | |
292 | /* set in i2c probe */ |
293 | void __iomem *base; /* i2c base addr */ |
294 | void __iomem *pdmabase; /* dma base address*/ |
295 | struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */ |
296 | bool have_pmic; /* can use i2c pins from PMIC */ |
297 | bool use_push_pull; /* IO config push-pull mode */ |
298 | |
299 | u16 irq_stat; /* interrupt status */ |
300 | unsigned int clk_src_div; |
301 | unsigned int speed_hz; /* The speed in transfer */ |
302 | enum mtk_trans_op op; |
303 | u16 timing_reg; |
304 | u16 high_speed_reg; |
305 | u16 ltiming_reg; |
306 | unsigned char auto_restart; |
307 | bool ignore_restart_irq; |
308 | struct mtk_i2c_ac_timing ac_timing; |
309 | const struct mtk_i2c_compatible *dev_comp; |
310 | }; |
311 | |
312 | /** |
313 | * struct i2c_spec_values: |
314 | * @min_low_ns: min LOW period of the SCL clock |
315 | * @min_su_sta_ns: min set-up time for a repeated START condition |
316 | * @max_hd_dat_ns: max data hold time |
317 | * @min_su_dat_ns: min data set-up time |
318 | */ |
319 | struct i2c_spec_values { |
320 | unsigned int min_low_ns; |
321 | unsigned int min_su_sta_ns; |
322 | unsigned int max_hd_dat_ns; |
323 | unsigned int min_su_dat_ns; |
324 | }; |
325 | |
326 | static const struct i2c_spec_values standard_mode_spec = { |
327 | .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER, |
328 | .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER, |
329 | .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER, |
330 | .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER, |
331 | }; |
332 | |
333 | static const struct i2c_spec_values fast_mode_spec = { |
334 | .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER, |
335 | .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER, |
336 | .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER, |
337 | .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER, |
338 | }; |
339 | |
340 | static const struct i2c_spec_values fast_mode_plus_spec = { |
341 | .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER, |
342 | .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER, |
343 | .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER, |
344 | .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER, |
345 | }; |
346 | |
347 | static const struct i2c_adapter_quirks mt6577_i2c_quirks = { |
348 | .flags = I2C_AQ_COMB_WRITE_THEN_READ, |
349 | .max_num_msgs = 1, |
350 | .max_write_len = 255, |
351 | .max_read_len = 255, |
352 | .max_comb_1st_msg_len = 255, |
353 | .max_comb_2nd_msg_len = 31, |
354 | }; |
355 | |
356 | static const struct i2c_adapter_quirks mt7622_i2c_quirks = { |
357 | .max_num_msgs = 255, |
358 | }; |
359 | |
360 | static const struct i2c_adapter_quirks mt8183_i2c_quirks = { |
361 | .flags = I2C_AQ_NO_ZERO_LEN, |
362 | }; |
363 | |
364 | static const struct mtk_i2c_compatible mt2712_compat = { |
365 | .regs = mt_i2c_regs_v1, |
366 | .pmic_i2c = 0, |
367 | .dcm = 1, |
368 | .auto_restart = 1, |
369 | .aux_len_reg = 1, |
370 | .timing_adjust = 1, |
371 | .dma_sync = 0, |
372 | .ltiming_adjust = 0, |
373 | .apdma_sync = 0, |
374 | .max_dma_support = 33, |
375 | }; |
376 | |
377 | static const struct mtk_i2c_compatible mt6577_compat = { |
378 | .quirks = &mt6577_i2c_quirks, |
379 | .regs = mt_i2c_regs_v1, |
380 | .pmic_i2c = 0, |
381 | .dcm = 1, |
382 | .auto_restart = 0, |
383 | .aux_len_reg = 0, |
384 | .timing_adjust = 0, |
385 | .dma_sync = 0, |
386 | .ltiming_adjust = 0, |
387 | .apdma_sync = 0, |
388 | .max_dma_support = 32, |
389 | }; |
390 | |
391 | static const struct mtk_i2c_compatible mt6589_compat = { |
392 | .quirks = &mt6577_i2c_quirks, |
393 | .regs = mt_i2c_regs_v1, |
394 | .pmic_i2c = 1, |
395 | .dcm = 0, |
396 | .auto_restart = 0, |
397 | .aux_len_reg = 0, |
398 | .timing_adjust = 0, |
399 | .dma_sync = 0, |
400 | .ltiming_adjust = 0, |
401 | .apdma_sync = 0, |
402 | .max_dma_support = 32, |
403 | }; |
404 | |
405 | static const struct mtk_i2c_compatible mt7622_compat = { |
406 | .quirks = &mt7622_i2c_quirks, |
407 | .regs = mt_i2c_regs_v1, |
408 | .pmic_i2c = 0, |
409 | .dcm = 1, |
410 | .auto_restart = 1, |
411 | .aux_len_reg = 1, |
412 | .timing_adjust = 0, |
413 | .dma_sync = 0, |
414 | .ltiming_adjust = 0, |
415 | .apdma_sync = 0, |
416 | .max_dma_support = 32, |
417 | }; |
418 | |
419 | static const struct mtk_i2c_compatible mt8168_compat = { |
420 | .regs = mt_i2c_regs_v1, |
421 | .pmic_i2c = 0, |
422 | .dcm = 1, |
423 | .auto_restart = 1, |
424 | .aux_len_reg = 1, |
425 | .timing_adjust = 1, |
426 | .dma_sync = 1, |
427 | .ltiming_adjust = 0, |
428 | .apdma_sync = 0, |
429 | .max_dma_support = 33, |
430 | }; |
431 | |
432 | static const struct mtk_i2c_compatible mt7981_compat = { |
433 | .regs = mt_i2c_regs_v3, |
434 | .pmic_i2c = 0, |
435 | .dcm = 0, |
436 | .auto_restart = 1, |
437 | .aux_len_reg = 1, |
438 | .timing_adjust = 1, |
439 | .dma_sync = 1, |
440 | .ltiming_adjust = 1, |
441 | .max_dma_support = 33 |
442 | }; |
443 | |
444 | static const struct mtk_i2c_compatible mt7986_compat = { |
445 | .quirks = &mt7622_i2c_quirks, |
446 | .regs = mt_i2c_regs_v1, |
447 | .pmic_i2c = 0, |
448 | .dcm = 1, |
449 | .auto_restart = 1, |
450 | .aux_len_reg = 1, |
451 | .timing_adjust = 0, |
452 | .dma_sync = 1, |
453 | .ltiming_adjust = 0, |
454 | .max_dma_support = 32, |
455 | }; |
456 | |
457 | static const struct mtk_i2c_compatible mt8173_compat = { |
458 | .regs = mt_i2c_regs_v1, |
459 | .pmic_i2c = 0, |
460 | .dcm = 1, |
461 | .auto_restart = 1, |
462 | .aux_len_reg = 1, |
463 | .timing_adjust = 0, |
464 | .dma_sync = 0, |
465 | .ltiming_adjust = 0, |
466 | .apdma_sync = 0, |
467 | .max_dma_support = 33, |
468 | }; |
469 | |
470 | static const struct mtk_i2c_compatible mt8183_compat = { |
471 | .quirks = &mt8183_i2c_quirks, |
472 | .regs = mt_i2c_regs_v2, |
473 | .pmic_i2c = 0, |
474 | .dcm = 0, |
475 | .auto_restart = 1, |
476 | .aux_len_reg = 1, |
477 | .timing_adjust = 1, |
478 | .dma_sync = 1, |
479 | .ltiming_adjust = 1, |
480 | .apdma_sync = 0, |
481 | .max_dma_support = 33, |
482 | }; |
483 | |
484 | static const struct mtk_i2c_compatible mt8186_compat = { |
485 | .regs = mt_i2c_regs_v2, |
486 | .pmic_i2c = 0, |
487 | .dcm = 0, |
488 | .auto_restart = 1, |
489 | .aux_len_reg = 1, |
490 | .timing_adjust = 1, |
491 | .dma_sync = 0, |
492 | .ltiming_adjust = 1, |
493 | .apdma_sync = 0, |
494 | .max_dma_support = 36, |
495 | }; |
496 | |
497 | static const struct mtk_i2c_compatible mt8188_compat = { |
498 | .regs = mt_i2c_regs_v3, |
499 | .pmic_i2c = 0, |
500 | .dcm = 0, |
501 | .auto_restart = 1, |
502 | .aux_len_reg = 1, |
503 | .timing_adjust = 1, |
504 | .dma_sync = 0, |
505 | .ltiming_adjust = 1, |
506 | .apdma_sync = 1, |
507 | .max_dma_support = 36, |
508 | }; |
509 | |
510 | static const struct mtk_i2c_compatible mt8192_compat = { |
511 | .quirks = &mt8183_i2c_quirks, |
512 | .regs = mt_i2c_regs_v2, |
513 | .pmic_i2c = 0, |
514 | .dcm = 0, |
515 | .auto_restart = 1, |
516 | .aux_len_reg = 1, |
517 | .timing_adjust = 1, |
518 | .dma_sync = 1, |
519 | .ltiming_adjust = 1, |
520 | .apdma_sync = 1, |
521 | .max_dma_support = 36, |
522 | }; |
523 | |
524 | static const struct of_device_id mtk_i2c_of_match[] = { |
525 | { .compatible = "mediatek,mt2712-i2c" , .data = &mt2712_compat }, |
526 | { .compatible = "mediatek,mt6577-i2c" , .data = &mt6577_compat }, |
527 | { .compatible = "mediatek,mt6589-i2c" , .data = &mt6589_compat }, |
528 | { .compatible = "mediatek,mt7622-i2c" , .data = &mt7622_compat }, |
529 | { .compatible = "mediatek,mt7981-i2c" , .data = &mt7981_compat }, |
530 | { .compatible = "mediatek,mt7986-i2c" , .data = &mt7986_compat }, |
531 | { .compatible = "mediatek,mt8168-i2c" , .data = &mt8168_compat }, |
532 | { .compatible = "mediatek,mt8173-i2c" , .data = &mt8173_compat }, |
533 | { .compatible = "mediatek,mt8183-i2c" , .data = &mt8183_compat }, |
534 | { .compatible = "mediatek,mt8186-i2c" , .data = &mt8186_compat }, |
535 | { .compatible = "mediatek,mt8188-i2c" , .data = &mt8188_compat }, |
536 | { .compatible = "mediatek,mt8192-i2c" , .data = &mt8192_compat }, |
537 | {} |
538 | }; |
539 | MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); |
540 | |
541 | static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg) |
542 | { |
543 | return readw(addr: i2c->base + i2c->dev_comp->regs[reg]); |
544 | } |
545 | |
546 | static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val, |
547 | enum I2C_REGS_OFFSET reg) |
548 | { |
549 | writew(val, addr: i2c->base + i2c->dev_comp->regs[reg]); |
550 | } |
551 | |
552 | static void mtk_i2c_init_hw(struct mtk_i2c *i2c) |
553 | { |
554 | u16 control_reg; |
555 | u16 intr_stat_reg; |
556 | u16 ext_conf_val; |
557 | |
558 | mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, reg: OFFSET_START); |
559 | intr_stat_reg = mtk_i2c_readw(i2c, reg: OFFSET_INTR_STAT); |
560 | mtk_i2c_writew(i2c, val: intr_stat_reg, reg: OFFSET_INTR_STAT); |
561 | |
562 | if (i2c->dev_comp->apdma_sync) { |
563 | writel(I2C_DMA_WARM_RST, addr: i2c->pdmabase + OFFSET_RST); |
564 | udelay(10); |
565 | writel(I2C_DMA_CLR_FLAG, addr: i2c->pdmabase + OFFSET_RST); |
566 | udelay(10); |
567 | writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST, |
568 | addr: i2c->pdmabase + OFFSET_RST); |
569 | mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST, |
570 | reg: OFFSET_SOFTRESET); |
571 | udelay(10); |
572 | writel(I2C_DMA_CLR_FLAG, addr: i2c->pdmabase + OFFSET_RST); |
573 | mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, reg: OFFSET_SOFTRESET); |
574 | } else { |
575 | writel(I2C_DMA_HARD_RST, addr: i2c->pdmabase + OFFSET_RST); |
576 | udelay(50); |
577 | writel(I2C_DMA_CLR_FLAG, addr: i2c->pdmabase + OFFSET_RST); |
578 | mtk_i2c_writew(i2c, I2C_SOFT_RST, reg: OFFSET_SOFTRESET); |
579 | } |
580 | |
581 | /* Set ioconfig */ |
582 | if (i2c->use_push_pull) |
583 | mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, reg: OFFSET_IO_CONFIG); |
584 | else |
585 | mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, reg: OFFSET_IO_CONFIG); |
586 | |
587 | if (i2c->dev_comp->dcm) |
588 | mtk_i2c_writew(i2c, I2C_DCM_DISABLE, reg: OFFSET_DCM_EN); |
589 | |
590 | mtk_i2c_writew(i2c, val: i2c->timing_reg, reg: OFFSET_TIMING); |
591 | mtk_i2c_writew(i2c, val: i2c->high_speed_reg, reg: OFFSET_HS); |
592 | if (i2c->dev_comp->ltiming_adjust) |
593 | mtk_i2c_writew(i2c, val: i2c->ltiming_reg, reg: OFFSET_LTIMING); |
594 | |
595 | if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ) |
596 | ext_conf_val = I2C_ST_START_CON; |
597 | else |
598 | ext_conf_val = I2C_FS_START_CON; |
599 | |
600 | if (i2c->dev_comp->timing_adjust) { |
601 | ext_conf_val = i2c->ac_timing.ext; |
602 | mtk_i2c_writew(i2c, val: i2c->ac_timing.inter_clk_div, |
603 | reg: OFFSET_CLOCK_DIV); |
604 | mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE, |
605 | reg: OFFSET_SCL_MIS_COMP_POINT); |
606 | mtk_i2c_writew(i2c, val: i2c->ac_timing.sda_timing, |
607 | reg: OFFSET_SDA_TIMING); |
608 | |
609 | if (i2c->dev_comp->ltiming_adjust) { |
610 | mtk_i2c_writew(i2c, val: i2c->ac_timing.htiming, |
611 | reg: OFFSET_TIMING); |
612 | mtk_i2c_writew(i2c, val: i2c->ac_timing.hs, reg: OFFSET_HS); |
613 | mtk_i2c_writew(i2c, val: i2c->ac_timing.ltiming, |
614 | reg: OFFSET_LTIMING); |
615 | } else { |
616 | mtk_i2c_writew(i2c, val: i2c->ac_timing.scl_hl_ratio, |
617 | reg: OFFSET_SCL_HIGH_LOW_RATIO); |
618 | mtk_i2c_writew(i2c, val: i2c->ac_timing.hs_scl_hl_ratio, |
619 | reg: OFFSET_HS_SCL_HIGH_LOW_RATIO); |
620 | mtk_i2c_writew(i2c, val: i2c->ac_timing.sta_stop, |
621 | reg: OFFSET_STA_STO_AC_TIMING); |
622 | mtk_i2c_writew(i2c, val: i2c->ac_timing.hs_sta_stop, |
623 | reg: OFFSET_HS_STA_STO_AC_TIMING); |
624 | } |
625 | } |
626 | mtk_i2c_writew(i2c, val: ext_conf_val, reg: OFFSET_EXT_CONF); |
627 | |
628 | /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ |
629 | if (i2c->have_pmic) |
630 | mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, reg: OFFSET_PATH_DIR); |
631 | |
632 | control_reg = I2C_CONTROL_ACKERR_DET_EN | |
633 | I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN; |
634 | if (i2c->dev_comp->dma_sync) |
635 | control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE; |
636 | |
637 | mtk_i2c_writew(i2c, val: control_reg, reg: OFFSET_CONTROL); |
638 | mtk_i2c_writew(i2c, I2C_DELAY_LEN, reg: OFFSET_DELAY_LEN); |
639 | } |
640 | |
641 | static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed) |
642 | { |
643 | if (speed <= I2C_MAX_STANDARD_MODE_FREQ) |
644 | return &standard_mode_spec; |
645 | else if (speed <= I2C_MAX_FAST_MODE_FREQ) |
646 | return &fast_mode_spec; |
647 | else |
648 | return &fast_mode_plus_spec; |
649 | } |
650 | |
651 | static int mtk_i2c_max_step_cnt(unsigned int target_speed) |
652 | { |
653 | if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) |
654 | return MAX_HS_STEP_CNT_DIV; |
655 | else |
656 | return MAX_STEP_CNT_DIV; |
657 | } |
658 | |
659 | static int mtk_i2c_get_clk_div_restri(struct mtk_i2c *i2c, |
660 | unsigned int sample_cnt) |
661 | { |
662 | int clk_div_restri = 0; |
663 | |
664 | if (i2c->dev_comp->ltiming_adjust == 0) |
665 | return 0; |
666 | |
667 | if (sample_cnt == 1) { |
668 | if (i2c->ac_timing.inter_clk_div == 0) |
669 | clk_div_restri = 0; |
670 | else |
671 | clk_div_restri = 1; |
672 | } else { |
673 | if (i2c->ac_timing.inter_clk_div == 0) |
674 | clk_div_restri = -1; |
675 | else if (i2c->ac_timing.inter_clk_div == 1) |
676 | clk_div_restri = 0; |
677 | else |
678 | clk_div_restri = 1; |
679 | } |
680 | |
681 | return clk_div_restri; |
682 | } |
683 | |
684 | /* |
685 | * Check and Calculate i2c ac-timing |
686 | * |
687 | * Hardware design: |
688 | * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src |
689 | * xxx_cnt_div = spec->min_xxx_ns / sample_ns |
690 | * |
691 | * Sample_ns is rounded down for xxx_cnt_div would be greater |
692 | * than the smallest spec. |
693 | * The sda_timing is chosen as the middle value between |
694 | * the largest and smallest. |
695 | */ |
696 | static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c, |
697 | unsigned int clk_src, |
698 | unsigned int check_speed, |
699 | unsigned int step_cnt, |
700 | unsigned int sample_cnt) |
701 | { |
702 | const struct i2c_spec_values *spec; |
703 | unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt; |
704 | unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f; |
705 | unsigned int sample_ns = div_u64(dividend: 1000000000ULL * (sample_cnt + 1), |
706 | divisor: clk_src); |
707 | |
708 | if (!i2c->dev_comp->timing_adjust) |
709 | return 0; |
710 | |
711 | if (i2c->dev_comp->ltiming_adjust) |
712 | max_sta_cnt = 0x100; |
713 | |
714 | spec = mtk_i2c_get_spec(speed: check_speed); |
715 | |
716 | if (i2c->dev_comp->ltiming_adjust) |
717 | clk_ns = 1000000000 / clk_src; |
718 | else |
719 | clk_ns = sample_ns / 2; |
720 | |
721 | su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns + |
722 | i2c->timing_info.scl_int_delay_ns, clk_ns); |
723 | if (su_sta_cnt > max_sta_cnt) |
724 | return -1; |
725 | |
726 | low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns); |
727 | max_step_cnt = mtk_i2c_max_step_cnt(target_speed: check_speed); |
728 | if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) { |
729 | if (low_cnt > step_cnt) { |
730 | high_cnt = 2 * step_cnt - low_cnt; |
731 | } else { |
732 | high_cnt = step_cnt; |
733 | low_cnt = step_cnt; |
734 | } |
735 | } else { |
736 | return -2; |
737 | } |
738 | |
739 | sda_max = spec->max_hd_dat_ns / sample_ns; |
740 | if (sda_max > low_cnt) |
741 | sda_max = 0; |
742 | |
743 | sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns); |
744 | if (sda_min < low_cnt) |
745 | sda_min = 0; |
746 | |
747 | if (sda_min > sda_max) |
748 | return -3; |
749 | |
750 | if (check_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { |
751 | if (i2c->dev_comp->ltiming_adjust) { |
752 | i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE | |
753 | (sample_cnt << 12) | (high_cnt << 8); |
754 | i2c->ac_timing.ltiming &= ~GENMASK(15, 9); |
755 | i2c->ac_timing.ltiming |= (sample_cnt << 12) | |
756 | (low_cnt << 9); |
757 | i2c->ac_timing.ext &= ~GENMASK(7, 1); |
758 | i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0); |
759 | } else { |
760 | i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) | |
761 | (high_cnt << 6) | low_cnt; |
762 | i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) | |
763 | su_sta_cnt; |
764 | } |
765 | i2c->ac_timing.sda_timing &= ~GENMASK(11, 6); |
766 | i2c->ac_timing.sda_timing |= (1 << 12) | |
767 | ((sda_max + sda_min) / 2) << 6; |
768 | } else { |
769 | if (i2c->dev_comp->ltiming_adjust) { |
770 | i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt); |
771 | i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt); |
772 | i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0); |
773 | } else { |
774 | i2c->ac_timing.scl_hl_ratio = (1 << 12) | |
775 | (high_cnt << 6) | low_cnt; |
776 | i2c->ac_timing.sta_stop = (su_sta_cnt << 8) | |
777 | su_sta_cnt; |
778 | } |
779 | |
780 | i2c->ac_timing.sda_timing = (1 << 12) | |
781 | (sda_max + sda_min) / 2; |
782 | } |
783 | |
784 | return 0; |
785 | } |
786 | |
787 | /* |
788 | * Calculate i2c port speed |
789 | * |
790 | * Hardware design: |
791 | * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt) |
792 | * clock_div: fixed in hardware, but may be various in different SoCs |
793 | * |
794 | * The calculation want to pick the highest bus frequency that is still |
795 | * less than or equal to i2c->speed_hz. The calculation try to get |
796 | * sample_cnt and step_cn |
797 | */ |
798 | static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, |
799 | unsigned int target_speed, |
800 | unsigned int *timing_step_cnt, |
801 | unsigned int *timing_sample_cnt) |
802 | { |
803 | unsigned int step_cnt; |
804 | unsigned int sample_cnt; |
805 | unsigned int max_step_cnt; |
806 | unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV; |
807 | unsigned int base_step_cnt; |
808 | unsigned int opt_div; |
809 | unsigned int best_mul; |
810 | unsigned int cnt_mul; |
811 | int ret = -EINVAL; |
812 | int clk_div_restri = 0; |
813 | |
814 | if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ) |
815 | target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ; |
816 | |
817 | max_step_cnt = mtk_i2c_max_step_cnt(target_speed); |
818 | base_step_cnt = max_step_cnt; |
819 | /* Find the best combination */ |
820 | opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed); |
821 | best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; |
822 | |
823 | /* Search for the best pair (sample_cnt, step_cnt) with |
824 | * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV |
825 | * 0 < step_cnt < max_step_cnt |
826 | * sample_cnt * step_cnt >= opt_div |
827 | * optimizing for sample_cnt * step_cnt being minimal |
828 | */ |
829 | for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { |
830 | clk_div_restri = mtk_i2c_get_clk_div_restri(i2c, sample_cnt); |
831 | step_cnt = DIV_ROUND_UP(opt_div + clk_div_restri, sample_cnt); |
832 | cnt_mul = step_cnt * sample_cnt; |
833 | if (step_cnt > max_step_cnt) |
834 | continue; |
835 | |
836 | if (cnt_mul < best_mul) { |
837 | ret = mtk_i2c_check_ac_timing(i2c, clk_src, |
838 | check_speed: target_speed, step_cnt: step_cnt - 1, sample_cnt: sample_cnt - 1); |
839 | if (ret) |
840 | continue; |
841 | |
842 | best_mul = cnt_mul; |
843 | base_sample_cnt = sample_cnt; |
844 | base_step_cnt = step_cnt; |
845 | if (best_mul == (opt_div + clk_div_restri)) |
846 | break; |
847 | } |
848 | } |
849 | |
850 | if (ret) |
851 | return -EINVAL; |
852 | |
853 | sample_cnt = base_sample_cnt; |
854 | step_cnt = base_step_cnt; |
855 | |
856 | if ((clk_src / (2 * (sample_cnt * step_cnt - clk_div_restri))) > |
857 | target_speed) { |
858 | /* In this case, hardware can't support such |
859 | * low i2c_bus_freq |
860 | */ |
861 | dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n" , target_speed); |
862 | return -EINVAL; |
863 | } |
864 | |
865 | *timing_step_cnt = step_cnt - 1; |
866 | *timing_sample_cnt = sample_cnt - 1; |
867 | |
868 | return 0; |
869 | } |
870 | |
871 | static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) |
872 | { |
873 | unsigned int clk_src; |
874 | unsigned int step_cnt; |
875 | unsigned int sample_cnt; |
876 | unsigned int l_step_cnt; |
877 | unsigned int l_sample_cnt; |
878 | unsigned int target_speed; |
879 | unsigned int clk_div; |
880 | unsigned int max_clk_div; |
881 | int ret; |
882 | |
883 | target_speed = i2c->speed_hz; |
884 | parent_clk /= i2c->clk_src_div; |
885 | |
886 | if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust) |
887 | max_clk_div = MAX_CLOCK_DIV_5BITS; |
888 | else if (i2c->dev_comp->timing_adjust) |
889 | max_clk_div = MAX_CLOCK_DIV_8BITS; |
890 | else |
891 | max_clk_div = 1; |
892 | |
893 | for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { |
894 | clk_src = parent_clk / clk_div; |
895 | i2c->ac_timing.inter_clk_div = clk_div - 1; |
896 | |
897 | if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { |
898 | /* Set master code speed register */ |
899 | ret = mtk_i2c_calculate_speed(i2c, clk_src, |
900 | I2C_MAX_FAST_MODE_FREQ, |
901 | timing_step_cnt: &l_step_cnt, |
902 | timing_sample_cnt: &l_sample_cnt); |
903 | if (ret < 0) |
904 | continue; |
905 | |
906 | i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; |
907 | |
908 | /* Set the high speed mode register */ |
909 | ret = mtk_i2c_calculate_speed(i2c, clk_src, |
910 | target_speed, timing_step_cnt: &step_cnt, |
911 | timing_sample_cnt: &sample_cnt); |
912 | if (ret < 0) |
913 | continue; |
914 | |
915 | i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | |
916 | (sample_cnt << 12) | (step_cnt << 8); |
917 | |
918 | if (i2c->dev_comp->ltiming_adjust) |
919 | i2c->ltiming_reg = |
920 | (l_sample_cnt << 6) | l_step_cnt | |
921 | (sample_cnt << 12) | (step_cnt << 9); |
922 | } else { |
923 | ret = mtk_i2c_calculate_speed(i2c, clk_src, |
924 | target_speed, timing_step_cnt: &l_step_cnt, |
925 | timing_sample_cnt: &l_sample_cnt); |
926 | if (ret < 0) |
927 | continue; |
928 | |
929 | i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; |
930 | |
931 | /* Disable the high speed transaction */ |
932 | i2c->high_speed_reg = I2C_TIME_CLR_VALUE; |
933 | |
934 | if (i2c->dev_comp->ltiming_adjust) |
935 | i2c->ltiming_reg = |
936 | (l_sample_cnt << 6) | l_step_cnt; |
937 | } |
938 | |
939 | break; |
940 | } |
941 | |
942 | |
943 | return 0; |
944 | } |
945 | |
946 | static void i2c_dump_register(struct mtk_i2c *i2c) |
947 | { |
948 | dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n" , |
949 | mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR), |
950 | mtk_i2c_readw(i2c, OFFSET_INTR_MASK)); |
951 | dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n" , |
952 | mtk_i2c_readw(i2c, OFFSET_INTR_STAT), |
953 | mtk_i2c_readw(i2c, OFFSET_CONTROL)); |
954 | dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n" , |
955 | mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN), |
956 | mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN)); |
957 | dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n" , |
958 | mtk_i2c_readw(i2c, OFFSET_DELAY_LEN), |
959 | mtk_i2c_readw(i2c, OFFSET_TIMING)); |
960 | dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n" , |
961 | mtk_i2c_readw(i2c, OFFSET_START), |
962 | mtk_i2c_readw(i2c, OFFSET_EXT_CONF)); |
963 | dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n" , |
964 | mtk_i2c_readw(i2c, OFFSET_HS), |
965 | mtk_i2c_readw(i2c, OFFSET_IO_CONFIG)); |
966 | dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n" , |
967 | mtk_i2c_readw(i2c, OFFSET_DCM_EN), |
968 | mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX)); |
969 | dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n" , |
970 | mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV), |
971 | mtk_i2c_readw(i2c, OFFSET_FIFO_STAT)); |
972 | dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n" , |
973 | mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL), |
974 | mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT)); |
975 | if (i2c->dev_comp->regs == mt_i2c_regs_v2) { |
976 | dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n" , |
977 | mtk_i2c_readw(i2c, OFFSET_LTIMING), |
978 | mtk_i2c_readw(i2c, OFFSET_MULTI_DMA)); |
979 | } |
980 | dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n" , |
981 | readl(i2c->pdmabase + OFFSET_INT_FLAG), |
982 | readl(i2c->pdmabase + OFFSET_INT_EN)); |
983 | dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n" , |
984 | readl(i2c->pdmabase + OFFSET_EN), |
985 | readl(i2c->pdmabase + OFFSET_CON)); |
986 | dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n" , |
987 | readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR), |
988 | readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR)); |
989 | dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n" , |
990 | readl(i2c->pdmabase + OFFSET_TX_LEN), |
991 | readl(i2c->pdmabase + OFFSET_RX_LEN)); |
992 | dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x" , |
993 | readl(i2c->pdmabase + OFFSET_TX_4G_MODE), |
994 | readl(i2c->pdmabase + OFFSET_RX_4G_MODE)); |
995 | } |
996 | |
997 | static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, |
998 | int num, int left_num) |
999 | { |
1000 | u16 addr_reg; |
1001 | u16 start_reg; |
1002 | u16 control_reg; |
1003 | u16 restart_flag = 0; |
1004 | u16 dma_sync = 0; |
1005 | u32 reg_4g_mode; |
1006 | u32 reg_dma_reset; |
1007 | u8 *dma_rd_buf = NULL; |
1008 | u8 *dma_wr_buf = NULL; |
1009 | dma_addr_t rpaddr = 0; |
1010 | dma_addr_t wpaddr = 0; |
1011 | int ret; |
1012 | |
1013 | i2c->irq_stat = 0; |
1014 | |
1015 | if (i2c->auto_restart) |
1016 | restart_flag = I2C_RS_TRANSFER; |
1017 | |
1018 | reinit_completion(x: &i2c->msg_complete); |
1019 | |
1020 | if (i2c->dev_comp->apdma_sync && |
1021 | i2c->op != I2C_MASTER_WRRD && num > 1) { |
1022 | mtk_i2c_writew(i2c, val: 0x00, reg: OFFSET_DEBUGCTRL); |
1023 | writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST, |
1024 | addr: i2c->pdmabase + OFFSET_RST); |
1025 | |
1026 | ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST, |
1027 | reg_dma_reset, |
1028 | !(reg_dma_reset & I2C_DMA_WARM_RST), |
1029 | 0, 100); |
1030 | if (ret) { |
1031 | dev_err(i2c->dev, "DMA warm reset timeout\n" ); |
1032 | return -ETIMEDOUT; |
1033 | } |
1034 | |
1035 | writel(I2C_DMA_CLR_FLAG, addr: i2c->pdmabase + OFFSET_RST); |
1036 | mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, reg: OFFSET_SOFTRESET); |
1037 | mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, reg: OFFSET_SOFTRESET); |
1038 | mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE, |
1039 | reg: OFFSET_DEBUGCTRL); |
1040 | } |
1041 | |
1042 | control_reg = mtk_i2c_readw(i2c, reg: OFFSET_CONTROL) & |
1043 | ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); |
1044 | if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1)) |
1045 | control_reg |= I2C_CONTROL_RS; |
1046 | |
1047 | if (i2c->op == I2C_MASTER_WRRD) |
1048 | control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; |
1049 | |
1050 | mtk_i2c_writew(i2c, val: control_reg, reg: OFFSET_CONTROL); |
1051 | |
1052 | addr_reg = i2c_8bit_addr_from_msg(msg: msgs); |
1053 | mtk_i2c_writew(i2c, val: addr_reg, reg: OFFSET_SLAVE_ADDR); |
1054 | |
1055 | /* Clear interrupt status */ |
1056 | mtk_i2c_writew(i2c, val: restart_flag | I2C_HS_NACKERR | I2C_ACKERR | |
1057 | I2C_ARB_LOST | I2C_TRANSAC_COMP, reg: OFFSET_INTR_STAT); |
1058 | |
1059 | mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, reg: OFFSET_FIFO_ADDR_CLR); |
1060 | |
1061 | /* Enable interrupt */ |
1062 | mtk_i2c_writew(i2c, val: restart_flag | I2C_HS_NACKERR | I2C_ACKERR | |
1063 | I2C_ARB_LOST | I2C_TRANSAC_COMP, reg: OFFSET_INTR_MASK); |
1064 | |
1065 | /* Set transfer and transaction len */ |
1066 | if (i2c->op == I2C_MASTER_WRRD) { |
1067 | if (i2c->dev_comp->aux_len_reg) { |
1068 | mtk_i2c_writew(i2c, val: msgs->len, reg: OFFSET_TRANSFER_LEN); |
1069 | mtk_i2c_writew(i2c, val: (msgs + 1)->len, |
1070 | reg: OFFSET_TRANSFER_LEN_AUX); |
1071 | } else { |
1072 | mtk_i2c_writew(i2c, val: msgs->len | ((msgs + 1)->len) << 8, |
1073 | reg: OFFSET_TRANSFER_LEN); |
1074 | } |
1075 | mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, reg: OFFSET_TRANSAC_LEN); |
1076 | } else { |
1077 | mtk_i2c_writew(i2c, val: msgs->len, reg: OFFSET_TRANSFER_LEN); |
1078 | mtk_i2c_writew(i2c, val: num, reg: OFFSET_TRANSAC_LEN); |
1079 | } |
1080 | |
1081 | if (i2c->dev_comp->apdma_sync) { |
1082 | dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE; |
1083 | if (i2c->op == I2C_MASTER_WRRD) |
1084 | dma_sync |= I2C_DMA_DIR_CHANGE; |
1085 | } |
1086 | |
1087 | /* Prepare buffer data to start transfer */ |
1088 | if (i2c->op == I2C_MASTER_RD) { |
1089 | writel(I2C_DMA_INT_FLAG_NONE, addr: i2c->pdmabase + OFFSET_INT_FLAG); |
1090 | writel(I2C_DMA_CON_RX | dma_sync, addr: i2c->pdmabase + OFFSET_CON); |
1091 | |
1092 | dma_rd_buf = i2c_get_dma_safe_msg_buf(msg: msgs, threshold: 1); |
1093 | if (!dma_rd_buf) |
1094 | return -ENOMEM; |
1095 | |
1096 | rpaddr = dma_map_single(i2c->dev, dma_rd_buf, |
1097 | msgs->len, DMA_FROM_DEVICE); |
1098 | if (dma_mapping_error(dev: i2c->dev, dma_addr: rpaddr)) { |
1099 | i2c_put_dma_safe_msg_buf(buf: dma_rd_buf, msg: msgs, xferred: false); |
1100 | |
1101 | return -ENOMEM; |
1102 | } |
1103 | |
1104 | if (i2c->dev_comp->max_dma_support > 32) { |
1105 | reg_4g_mode = upper_32_bits(rpaddr); |
1106 | writel(val: reg_4g_mode, addr: i2c->pdmabase + OFFSET_RX_4G_MODE); |
1107 | } |
1108 | |
1109 | writel(val: (u32)rpaddr, addr: i2c->pdmabase + OFFSET_RX_MEM_ADDR); |
1110 | writel(val: msgs->len, addr: i2c->pdmabase + OFFSET_RX_LEN); |
1111 | } else if (i2c->op == I2C_MASTER_WR) { |
1112 | writel(I2C_DMA_INT_FLAG_NONE, addr: i2c->pdmabase + OFFSET_INT_FLAG); |
1113 | writel(I2C_DMA_CON_TX | dma_sync, addr: i2c->pdmabase + OFFSET_CON); |
1114 | |
1115 | dma_wr_buf = i2c_get_dma_safe_msg_buf(msg: msgs, threshold: 1); |
1116 | if (!dma_wr_buf) |
1117 | return -ENOMEM; |
1118 | |
1119 | wpaddr = dma_map_single(i2c->dev, dma_wr_buf, |
1120 | msgs->len, DMA_TO_DEVICE); |
1121 | if (dma_mapping_error(dev: i2c->dev, dma_addr: wpaddr)) { |
1122 | i2c_put_dma_safe_msg_buf(buf: dma_wr_buf, msg: msgs, xferred: false); |
1123 | |
1124 | return -ENOMEM; |
1125 | } |
1126 | |
1127 | if (i2c->dev_comp->max_dma_support > 32) { |
1128 | reg_4g_mode = upper_32_bits(wpaddr); |
1129 | writel(val: reg_4g_mode, addr: i2c->pdmabase + OFFSET_TX_4G_MODE); |
1130 | } |
1131 | |
1132 | writel(val: (u32)wpaddr, addr: i2c->pdmabase + OFFSET_TX_MEM_ADDR); |
1133 | writel(val: msgs->len, addr: i2c->pdmabase + OFFSET_TX_LEN); |
1134 | } else { |
1135 | writel(I2C_DMA_CLR_FLAG, addr: i2c->pdmabase + OFFSET_INT_FLAG); |
1136 | writel(I2C_DMA_CLR_FLAG | dma_sync, addr: i2c->pdmabase + OFFSET_CON); |
1137 | |
1138 | dma_wr_buf = i2c_get_dma_safe_msg_buf(msg: msgs, threshold: 1); |
1139 | if (!dma_wr_buf) |
1140 | return -ENOMEM; |
1141 | |
1142 | wpaddr = dma_map_single(i2c->dev, dma_wr_buf, |
1143 | msgs->len, DMA_TO_DEVICE); |
1144 | if (dma_mapping_error(dev: i2c->dev, dma_addr: wpaddr)) { |
1145 | i2c_put_dma_safe_msg_buf(buf: dma_wr_buf, msg: msgs, xferred: false); |
1146 | |
1147 | return -ENOMEM; |
1148 | } |
1149 | |
1150 | dma_rd_buf = i2c_get_dma_safe_msg_buf(msg: (msgs + 1), threshold: 1); |
1151 | if (!dma_rd_buf) { |
1152 | dma_unmap_single(i2c->dev, wpaddr, |
1153 | msgs->len, DMA_TO_DEVICE); |
1154 | |
1155 | i2c_put_dma_safe_msg_buf(buf: dma_wr_buf, msg: msgs, xferred: false); |
1156 | |
1157 | return -ENOMEM; |
1158 | } |
1159 | |
1160 | rpaddr = dma_map_single(i2c->dev, dma_rd_buf, |
1161 | (msgs + 1)->len, |
1162 | DMA_FROM_DEVICE); |
1163 | if (dma_mapping_error(dev: i2c->dev, dma_addr: rpaddr)) { |
1164 | dma_unmap_single(i2c->dev, wpaddr, |
1165 | msgs->len, DMA_TO_DEVICE); |
1166 | |
1167 | i2c_put_dma_safe_msg_buf(buf: dma_wr_buf, msg: msgs, xferred: false); |
1168 | i2c_put_dma_safe_msg_buf(buf: dma_rd_buf, msg: (msgs + 1), xferred: false); |
1169 | |
1170 | return -ENOMEM; |
1171 | } |
1172 | |
1173 | if (i2c->dev_comp->max_dma_support > 32) { |
1174 | reg_4g_mode = upper_32_bits(wpaddr); |
1175 | writel(val: reg_4g_mode, addr: i2c->pdmabase + OFFSET_TX_4G_MODE); |
1176 | |
1177 | reg_4g_mode = upper_32_bits(rpaddr); |
1178 | writel(val: reg_4g_mode, addr: i2c->pdmabase + OFFSET_RX_4G_MODE); |
1179 | } |
1180 | |
1181 | writel(val: (u32)wpaddr, addr: i2c->pdmabase + OFFSET_TX_MEM_ADDR); |
1182 | writel(val: (u32)rpaddr, addr: i2c->pdmabase + OFFSET_RX_MEM_ADDR); |
1183 | writel(val: msgs->len, addr: i2c->pdmabase + OFFSET_TX_LEN); |
1184 | writel(val: (msgs + 1)->len, addr: i2c->pdmabase + OFFSET_RX_LEN); |
1185 | } |
1186 | |
1187 | writel(I2C_DMA_START_EN, addr: i2c->pdmabase + OFFSET_EN); |
1188 | |
1189 | if (!i2c->auto_restart) { |
1190 | start_reg = I2C_TRANSAC_START; |
1191 | } else { |
1192 | start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG; |
1193 | if (left_num >= 1) |
1194 | start_reg |= I2C_RS_MUL_CNFG; |
1195 | } |
1196 | mtk_i2c_writew(i2c, val: start_reg, reg: OFFSET_START); |
1197 | |
1198 | ret = wait_for_completion_timeout(x: &i2c->msg_complete, |
1199 | timeout: i2c->adap.timeout); |
1200 | |
1201 | /* Clear interrupt mask */ |
1202 | mtk_i2c_writew(i2c, val: ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR | |
1203 | I2C_ARB_LOST | I2C_TRANSAC_COMP), reg: OFFSET_INTR_MASK); |
1204 | |
1205 | if (i2c->op == I2C_MASTER_WR) { |
1206 | dma_unmap_single(i2c->dev, wpaddr, |
1207 | msgs->len, DMA_TO_DEVICE); |
1208 | |
1209 | i2c_put_dma_safe_msg_buf(buf: dma_wr_buf, msg: msgs, xferred: true); |
1210 | } else if (i2c->op == I2C_MASTER_RD) { |
1211 | dma_unmap_single(i2c->dev, rpaddr, |
1212 | msgs->len, DMA_FROM_DEVICE); |
1213 | |
1214 | i2c_put_dma_safe_msg_buf(buf: dma_rd_buf, msg: msgs, xferred: true); |
1215 | } else { |
1216 | dma_unmap_single(i2c->dev, wpaddr, msgs->len, |
1217 | DMA_TO_DEVICE); |
1218 | dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len, |
1219 | DMA_FROM_DEVICE); |
1220 | |
1221 | i2c_put_dma_safe_msg_buf(buf: dma_wr_buf, msg: msgs, xferred: true); |
1222 | i2c_put_dma_safe_msg_buf(buf: dma_rd_buf, msg: (msgs + 1), xferred: true); |
1223 | } |
1224 | |
1225 | if (ret == 0) { |
1226 | dev_dbg(i2c->dev, "addr: %x, transfer timeout\n" , msgs->addr); |
1227 | i2c_dump_register(i2c); |
1228 | mtk_i2c_init_hw(i2c); |
1229 | return -ETIMEDOUT; |
1230 | } |
1231 | |
1232 | if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { |
1233 | dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n" , msgs->addr); |
1234 | mtk_i2c_init_hw(i2c); |
1235 | return -ENXIO; |
1236 | } |
1237 | |
1238 | return 0; |
1239 | } |
1240 | |
1241 | static int mtk_i2c_transfer(struct i2c_adapter *adap, |
1242 | struct i2c_msg msgs[], int num) |
1243 | { |
1244 | int ret; |
1245 | int left_num = num; |
1246 | struct mtk_i2c *i2c = i2c_get_adapdata(adap); |
1247 | |
1248 | ret = clk_bulk_enable(num_clks: I2C_MT65XX_CLK_MAX, clks: i2c->clocks); |
1249 | if (ret) |
1250 | return ret; |
1251 | |
1252 | i2c->auto_restart = i2c->dev_comp->auto_restart; |
1253 | |
1254 | /* checking if we can skip restart and optimize using WRRD mode */ |
1255 | if (i2c->auto_restart && num == 2) { |
1256 | if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) && |
1257 | msgs[0].addr == msgs[1].addr) { |
1258 | i2c->auto_restart = 0; |
1259 | } |
1260 | } |
1261 | |
1262 | if (i2c->auto_restart && num >= 2 && |
1263 | i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) |
1264 | /* ignore the first restart irq after the master code, |
1265 | * otherwise the first transfer will be discarded. |
1266 | */ |
1267 | i2c->ignore_restart_irq = true; |
1268 | else |
1269 | i2c->ignore_restart_irq = false; |
1270 | |
1271 | while (left_num--) { |
1272 | if (!msgs->buf) { |
1273 | dev_dbg(i2c->dev, "data buffer is NULL.\n" ); |
1274 | ret = -EINVAL; |
1275 | goto err_exit; |
1276 | } |
1277 | |
1278 | if (msgs->flags & I2C_M_RD) |
1279 | i2c->op = I2C_MASTER_RD; |
1280 | else |
1281 | i2c->op = I2C_MASTER_WR; |
1282 | |
1283 | if (!i2c->auto_restart) { |
1284 | if (num > 1) { |
1285 | /* combined two messages into one transaction */ |
1286 | i2c->op = I2C_MASTER_WRRD; |
1287 | left_num--; |
1288 | } |
1289 | } |
1290 | |
1291 | /* always use DMA mode. */ |
1292 | ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); |
1293 | if (ret < 0) |
1294 | goto err_exit; |
1295 | |
1296 | msgs++; |
1297 | } |
1298 | /* the return value is number of executed messages */ |
1299 | ret = num; |
1300 | |
1301 | err_exit: |
1302 | clk_bulk_disable(num_clks: I2C_MT65XX_CLK_MAX, clks: i2c->clocks); |
1303 | return ret; |
1304 | } |
1305 | |
1306 | static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) |
1307 | { |
1308 | struct mtk_i2c *i2c = dev_id; |
1309 | u16 restart_flag = 0; |
1310 | u16 intr_stat; |
1311 | |
1312 | if (i2c->auto_restart) |
1313 | restart_flag = I2C_RS_TRANSFER; |
1314 | |
1315 | intr_stat = mtk_i2c_readw(i2c, reg: OFFSET_INTR_STAT); |
1316 | mtk_i2c_writew(i2c, val: intr_stat, reg: OFFSET_INTR_STAT); |
1317 | |
1318 | /* |
1319 | * when occurs ack error, i2c controller generate two interrupts |
1320 | * first is the ack error interrupt, then the complete interrupt |
1321 | * i2c->irq_stat need keep the two interrupt value. |
1322 | */ |
1323 | i2c->irq_stat |= intr_stat; |
1324 | |
1325 | if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) { |
1326 | i2c->ignore_restart_irq = false; |
1327 | i2c->irq_stat = 0; |
1328 | mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | |
1329 | I2C_TRANSAC_START, reg: OFFSET_START); |
1330 | } else { |
1331 | if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag)) |
1332 | complete(&i2c->msg_complete); |
1333 | } |
1334 | |
1335 | return IRQ_HANDLED; |
1336 | } |
1337 | |
1338 | static u32 mtk_i2c_functionality(struct i2c_adapter *adap) |
1339 | { |
1340 | if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN)) |
1341 | return I2C_FUNC_I2C | |
1342 | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); |
1343 | else |
1344 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
1345 | } |
1346 | |
1347 | static const struct i2c_algorithm mtk_i2c_algorithm = { |
1348 | .master_xfer = mtk_i2c_transfer, |
1349 | .functionality = mtk_i2c_functionality, |
1350 | }; |
1351 | |
1352 | static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c) |
1353 | { |
1354 | int ret; |
1355 | |
1356 | ret = of_property_read_u32(np, propname: "clock-frequency" , out_value: &i2c->speed_hz); |
1357 | if (ret < 0) |
1358 | i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ; |
1359 | |
1360 | ret = of_property_read_u32(np, propname: "clock-div" , out_value: &i2c->clk_src_div); |
1361 | if (ret < 0) |
1362 | return ret; |
1363 | |
1364 | if (i2c->clk_src_div == 0) |
1365 | return -EINVAL; |
1366 | |
1367 | i2c->have_pmic = of_property_read_bool(np, propname: "mediatek,have-pmic" ); |
1368 | i2c->use_push_pull = |
1369 | of_property_read_bool(np, propname: "mediatek,use-push-pull" ); |
1370 | |
1371 | i2c_parse_fw_timings(dev: i2c->dev, t: &i2c->timing_info, use_defaults: true); |
1372 | |
1373 | return 0; |
1374 | } |
1375 | |
1376 | static int mtk_i2c_probe(struct platform_device *pdev) |
1377 | { |
1378 | int ret = 0; |
1379 | struct mtk_i2c *i2c; |
1380 | int i, irq, speed_clk; |
1381 | |
1382 | i2c = devm_kzalloc(dev: &pdev->dev, size: sizeof(*i2c), GFP_KERNEL); |
1383 | if (!i2c) |
1384 | return -ENOMEM; |
1385 | |
1386 | i2c->base = devm_platform_get_and_ioremap_resource(pdev, index: 0, NULL); |
1387 | if (IS_ERR(ptr: i2c->base)) |
1388 | return PTR_ERR(ptr: i2c->base); |
1389 | |
1390 | i2c->pdmabase = devm_platform_get_and_ioremap_resource(pdev, index: 1, NULL); |
1391 | if (IS_ERR(ptr: i2c->pdmabase)) |
1392 | return PTR_ERR(ptr: i2c->pdmabase); |
1393 | |
1394 | irq = platform_get_irq(pdev, 0); |
1395 | if (irq < 0) |
1396 | return irq; |
1397 | |
1398 | init_completion(x: &i2c->msg_complete); |
1399 | |
1400 | i2c->dev_comp = of_device_get_match_data(dev: &pdev->dev); |
1401 | i2c->adap.dev.of_node = pdev->dev.of_node; |
1402 | i2c->dev = &pdev->dev; |
1403 | i2c->adap.dev.parent = &pdev->dev; |
1404 | i2c->adap.owner = THIS_MODULE; |
1405 | i2c->adap.algo = &mtk_i2c_algorithm; |
1406 | i2c->adap.quirks = i2c->dev_comp->quirks; |
1407 | i2c->adap.timeout = 2 * HZ; |
1408 | i2c->adap.retries = 1; |
1409 | i2c->adap.bus_regulator = devm_regulator_get_optional(dev: &pdev->dev, id: "vbus" ); |
1410 | if (IS_ERR(ptr: i2c->adap.bus_regulator)) { |
1411 | if (PTR_ERR(ptr: i2c->adap.bus_regulator) == -ENODEV) |
1412 | i2c->adap.bus_regulator = NULL; |
1413 | else |
1414 | return PTR_ERR(ptr: i2c->adap.bus_regulator); |
1415 | } |
1416 | |
1417 | ret = mtk_i2c_parse_dt(np: pdev->dev.of_node, i2c); |
1418 | if (ret) |
1419 | return -EINVAL; |
1420 | |
1421 | if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) |
1422 | return -EINVAL; |
1423 | |
1424 | /* Fill in clk-bulk IDs */ |
1425 | for (i = 0; i < I2C_MT65XX_CLK_MAX; i++) |
1426 | i2c->clocks[i].id = i2c_mt65xx_clk_ids[i]; |
1427 | |
1428 | /* Get clocks one by one, some may be optional */ |
1429 | i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(dev: &pdev->dev, id: "main" ); |
1430 | if (IS_ERR(ptr: i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) { |
1431 | dev_err(&pdev->dev, "cannot get main clock\n" ); |
1432 | return PTR_ERR(ptr: i2c->clocks[I2C_MT65XX_CLK_MAIN].clk); |
1433 | } |
1434 | |
1435 | i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(dev: &pdev->dev, id: "dma" ); |
1436 | if (IS_ERR(ptr: i2c->clocks[I2C_MT65XX_CLK_DMA].clk)) { |
1437 | dev_err(&pdev->dev, "cannot get dma clock\n" ); |
1438 | return PTR_ERR(ptr: i2c->clocks[I2C_MT65XX_CLK_DMA].clk); |
1439 | } |
1440 | |
1441 | i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(dev: &pdev->dev, id: "arb" ); |
1442 | if (IS_ERR(ptr: i2c->clocks[I2C_MT65XX_CLK_ARB].clk)) |
1443 | return PTR_ERR(ptr: i2c->clocks[I2C_MT65XX_CLK_ARB].clk); |
1444 | |
1445 | i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get_optional(dev: &pdev->dev, id: "pmic" ); |
1446 | if (IS_ERR(ptr: i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) { |
1447 | dev_err(&pdev->dev, "cannot get pmic clock\n" ); |
1448 | return PTR_ERR(ptr: i2c->clocks[I2C_MT65XX_CLK_PMIC].clk); |
1449 | } |
1450 | |
1451 | if (i2c->have_pmic) { |
1452 | if (!i2c->clocks[I2C_MT65XX_CLK_PMIC].clk) { |
1453 | dev_err(&pdev->dev, "cannot get pmic clock\n" ); |
1454 | return -ENODEV; |
1455 | } |
1456 | speed_clk = I2C_MT65XX_CLK_PMIC; |
1457 | } else { |
1458 | speed_clk = I2C_MT65XX_CLK_MAIN; |
1459 | } |
1460 | |
1461 | strscpy(p: i2c->adap.name, I2C_DRV_NAME, size: sizeof(i2c->adap.name)); |
1462 | |
1463 | ret = mtk_i2c_set_speed(i2c, parent_clk: clk_get_rate(clk: i2c->clocks[speed_clk].clk)); |
1464 | if (ret) { |
1465 | dev_err(&pdev->dev, "Failed to set the speed.\n" ); |
1466 | return -EINVAL; |
1467 | } |
1468 | |
1469 | if (i2c->dev_comp->max_dma_support > 32) { |
1470 | ret = dma_set_mask(dev: &pdev->dev, |
1471 | DMA_BIT_MASK(i2c->dev_comp->max_dma_support)); |
1472 | if (ret) { |
1473 | dev_err(&pdev->dev, "dma_set_mask return error.\n" ); |
1474 | return ret; |
1475 | } |
1476 | } |
1477 | |
1478 | ret = clk_bulk_prepare_enable(num_clks: I2C_MT65XX_CLK_MAX, clks: i2c->clocks); |
1479 | if (ret) { |
1480 | dev_err(&pdev->dev, "clock enable failed!\n" ); |
1481 | return ret; |
1482 | } |
1483 | mtk_i2c_init_hw(i2c); |
1484 | clk_bulk_disable(num_clks: I2C_MT65XX_CLK_MAX, clks: i2c->clocks); |
1485 | |
1486 | ret = devm_request_irq(dev: &pdev->dev, irq, handler: mtk_i2c_irq, |
1487 | IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE, |
1488 | devname: dev_name(dev: &pdev->dev), dev_id: i2c); |
1489 | if (ret < 0) { |
1490 | dev_err(&pdev->dev, |
1491 | "Request I2C IRQ %d fail\n" , irq); |
1492 | goto err_bulk_unprepare; |
1493 | } |
1494 | |
1495 | i2c_set_adapdata(adap: &i2c->adap, data: i2c); |
1496 | ret = i2c_add_adapter(adap: &i2c->adap); |
1497 | if (ret) |
1498 | goto err_bulk_unprepare; |
1499 | |
1500 | platform_set_drvdata(pdev, data: i2c); |
1501 | |
1502 | return 0; |
1503 | |
1504 | err_bulk_unprepare: |
1505 | clk_bulk_unprepare(num_clks: I2C_MT65XX_CLK_MAX, clks: i2c->clocks); |
1506 | |
1507 | return ret; |
1508 | } |
1509 | |
1510 | static void mtk_i2c_remove(struct platform_device *pdev) |
1511 | { |
1512 | struct mtk_i2c *i2c = platform_get_drvdata(pdev); |
1513 | |
1514 | i2c_del_adapter(adap: &i2c->adap); |
1515 | |
1516 | clk_bulk_unprepare(num_clks: I2C_MT65XX_CLK_MAX, clks: i2c->clocks); |
1517 | } |
1518 | |
1519 | static int mtk_i2c_suspend_noirq(struct device *dev) |
1520 | { |
1521 | struct mtk_i2c *i2c = dev_get_drvdata(dev); |
1522 | |
1523 | i2c_mark_adapter_suspended(adap: &i2c->adap); |
1524 | clk_bulk_unprepare(num_clks: I2C_MT65XX_CLK_MAX, clks: i2c->clocks); |
1525 | |
1526 | return 0; |
1527 | } |
1528 | |
1529 | static int mtk_i2c_resume_noirq(struct device *dev) |
1530 | { |
1531 | int ret; |
1532 | struct mtk_i2c *i2c = dev_get_drvdata(dev); |
1533 | |
1534 | ret = clk_bulk_prepare_enable(num_clks: I2C_MT65XX_CLK_MAX, clks: i2c->clocks); |
1535 | if (ret) { |
1536 | dev_err(dev, "clock enable failed!\n" ); |
1537 | return ret; |
1538 | } |
1539 | |
1540 | mtk_i2c_init_hw(i2c); |
1541 | |
1542 | clk_bulk_disable(num_clks: I2C_MT65XX_CLK_MAX, clks: i2c->clocks); |
1543 | |
1544 | i2c_mark_adapter_resumed(adap: &i2c->adap); |
1545 | |
1546 | return 0; |
1547 | } |
1548 | |
1549 | static const struct dev_pm_ops mtk_i2c_pm = { |
1550 | NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend_noirq, |
1551 | mtk_i2c_resume_noirq) |
1552 | }; |
1553 | |
1554 | static struct platform_driver mtk_i2c_driver = { |
1555 | .probe = mtk_i2c_probe, |
1556 | .remove_new = mtk_i2c_remove, |
1557 | .driver = { |
1558 | .name = I2C_DRV_NAME, |
1559 | .pm = pm_sleep_ptr(&mtk_i2c_pm), |
1560 | .of_match_table = mtk_i2c_of_match, |
1561 | }, |
1562 | }; |
1563 | |
1564 | module_platform_driver(mtk_i2c_driver); |
1565 | |
1566 | MODULE_LICENSE("GPL v2" ); |
1567 | MODULE_DESCRIPTION("MediaTek I2C Bus Driver" ); |
1568 | MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>" ); |
1569 | |