1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * i2c_adap_pxa.c
4 *
5 * I2C adapter for the PXA I2C bus access.
6 *
7 * Copyright (C) 2002 Intrinsyc Software Inc.
8 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
9 *
10 * History:
11 * Apr 2002: Initial version [CS]
12 * Jun 2002: Properly separated algo/adap [FB]
13 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
14 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
15 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
16 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
17 * Feb 2005: Rework slave mode handling [RMK]
18 */
19#include <linux/clk.h>
20#include <linux/delay.h>
21#include <linux/err.h>
22#include <linux/errno.h>
23#include <linux/gpio/consumer.h>
24#include <linux/i2c.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32#include <linux/pinctrl/consumer.h>
33#include <linux/platform_device.h>
34#include <linux/platform_data/i2c-pxa.h>
35#include <linux/property.h>
36#include <linux/slab.h>
37
38/* I2C register field definitions */
39#define IBMR_SDAS (1 << 0)
40#define IBMR_SCLS (1 << 1)
41
42#define ICR_START (1 << 0) /* start bit */
43#define ICR_STOP (1 << 1) /* stop bit */
44#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
45#define ICR_TB (1 << 3) /* transfer byte bit */
46#define ICR_MA (1 << 4) /* master abort */
47#define ICR_SCLE (1 << 5) /* master clock enable */
48#define ICR_IUE (1 << 6) /* unit enable */
49#define ICR_GCD (1 << 7) /* general call disable */
50#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
51#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
52#define ICR_BEIE (1 << 10) /* enable bus error ints */
53#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
54#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
55#define ICR_SADIE (1 << 13) /* slave address detected int enable */
56#define ICR_UR (1 << 14) /* unit reset */
57#define ICR_FM (1 << 15) /* fast mode */
58#define ICR_HS (1 << 16) /* High Speed mode */
59#define ICR_A3700_FM (1 << 16) /* fast mode for armada-3700 */
60#define ICR_A3700_HS (1 << 17) /* high speed mode for armada-3700 */
61#define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
62
63#define ISR_RWM (1 << 0) /* read/write mode */
64#define ISR_ACKNAK (1 << 1) /* ack/nak status */
65#define ISR_UB (1 << 2) /* unit busy */
66#define ISR_IBB (1 << 3) /* bus busy */
67#define ISR_SSD (1 << 4) /* slave stop detected */
68#define ISR_ALD (1 << 5) /* arbitration loss detected */
69#define ISR_ITE (1 << 6) /* tx buffer empty */
70#define ISR_IRF (1 << 7) /* rx buffer full */
71#define ISR_GCAD (1 << 8) /* general call address detected */
72#define ISR_SAD (1 << 9) /* slave address detected */
73#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
74
75#define ILCR_SLV_SHIFT 0
76#define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT)
77#define ILCR_FLV_SHIFT 9
78#define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT)
79#define ILCR_HLVL_SHIFT 18
80#define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT)
81#define ILCR_HLVH_SHIFT 27
82#define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT)
83
84#define IWCR_CNT_SHIFT 0
85#define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT)
86#define IWCR_HS_CNT1_SHIFT 5
87#define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT)
88#define IWCR_HS_CNT2_SHIFT 10
89#define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT)
90
91/* need a longer timeout if we're dealing with the fact we may well be
92 * looking at a multi-master environment
93 */
94#define DEF_TIMEOUT 32
95
96#define NO_SLAVE (-ENXIO)
97#define BUS_ERROR (-EREMOTEIO)
98#define XFER_NAKED (-ECONNREFUSED)
99#define I2C_RETRY (-2000) /* an error has occurred retry transmit */
100
101/* ICR initialize bit values
102 *
103 * 15 FM 0 (100 kHz operation)
104 * 14 UR 0 (No unit reset)
105 * 13 SADIE 0 (Disables the unit from interrupting on slave addresses
106 * matching its slave address)
107 * 12 ALDIE 0 (Disables the unit from interrupt when it loses arbitration
108 * in master mode)
109 * 11 SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode)
110 * 10 BEIE 1 (Enable interrupts from detected bus errors, no ACK sent)
111 * 9 IRFIE 1 (Enable interrupts from full buffer received)
112 * 8 ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty)
113 * 7 GCD 1 (Disables i2c unit response to general call messages as a slave)
114 * 6 IUE 0 (Disable unit until we change settings)
115 * 5 SCLE 1 (Enables the i2c clock output for master mode (drives SCL)
116 * 4 MA 0 (Only send stop with the ICR stop bit)
117 * 3 TB 0 (We are not transmitting a byte initially)
118 * 2 ACKNAK 0 (Send an ACK after the unit receives a byte)
119 * 1 STOP 0 (Do not send a STOP)
120 * 0 START 0 (Do not send a START)
121 */
122#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
123
124/* I2C status register init values
125 *
126 * 10 BED 1 (Clear bus error detected)
127 * 9 SAD 1 (Clear slave address detected)
128 * 7 IRF 1 (Clear IDBR Receive Full)
129 * 6 ITE 1 (Clear IDBR Transmit Empty)
130 * 5 ALD 1 (Clear Arbitration Loss Detected)
131 * 4 SSD 1 (Clear Slave Stop Detected)
132 */
133#define I2C_ISR_INIT 0x7FF /* status register init */
134
135struct pxa_reg_layout {
136 u32 ibmr;
137 u32 idbr;
138 u32 icr;
139 u32 isr;
140 u32 isar;
141 u32 ilcr;
142 u32 iwcr;
143 u32 fm;
144 u32 hs;
145};
146
147enum pxa_i2c_types {
148 REGS_PXA2XX,
149 REGS_PXA3XX,
150 REGS_CE4100,
151 REGS_PXA910,
152 REGS_A3700,
153};
154
155/* I2C register layout definitions */
156static struct pxa_reg_layout pxa_reg_layout[] = {
157 [REGS_PXA2XX] = {
158 .ibmr = 0x00,
159 .idbr = 0x08,
160 .icr = 0x10,
161 .isr = 0x18,
162 .isar = 0x20,
163 .fm = ICR_FM,
164 .hs = ICR_HS,
165 },
166 [REGS_PXA3XX] = {
167 .ibmr = 0x00,
168 .idbr = 0x04,
169 .icr = 0x08,
170 .isr = 0x0c,
171 .isar = 0x10,
172 .fm = ICR_FM,
173 .hs = ICR_HS,
174 },
175 [REGS_CE4100] = {
176 .ibmr = 0x14,
177 .idbr = 0x0c,
178 .icr = 0x00,
179 .isr = 0x04,
180 /* no isar register */
181 .fm = ICR_FM,
182 .hs = ICR_HS,
183 },
184 [REGS_PXA910] = {
185 .ibmr = 0x00,
186 .idbr = 0x08,
187 .icr = 0x10,
188 .isr = 0x18,
189 .isar = 0x20,
190 .ilcr = 0x28,
191 .iwcr = 0x30,
192 .fm = ICR_FM,
193 .hs = ICR_HS,
194 },
195 [REGS_A3700] = {
196 .ibmr = 0x00,
197 .idbr = 0x04,
198 .icr = 0x08,
199 .isr = 0x0c,
200 .isar = 0x10,
201 .fm = ICR_A3700_FM,
202 .hs = ICR_A3700_HS,
203 },
204};
205
206static const struct of_device_id i2c_pxa_dt_ids[] = {
207 { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
208 { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
209 { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
210 { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
211 {}
212};
213MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
214
215static const struct platform_device_id i2c_pxa_id_table[] = {
216 { "pxa2xx-i2c", REGS_PXA2XX },
217 { "pxa3xx-pwri2c", REGS_PXA3XX },
218 { "ce4100-i2c", REGS_CE4100 },
219 { "pxa910-i2c", REGS_PXA910 },
220 { "armada-3700-i2c", REGS_A3700 },
221 { },
222};
223MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
224
225struct pxa_i2c {
226 spinlock_t lock;
227 wait_queue_head_t wait;
228 struct i2c_msg *msg;
229 unsigned int msg_num;
230 unsigned int msg_idx;
231 unsigned int msg_ptr;
232 unsigned int slave_addr;
233 unsigned int req_slave_addr;
234
235 struct i2c_adapter adap;
236 struct clk *clk;
237#ifdef CONFIG_I2C_PXA_SLAVE
238 struct i2c_client *slave;
239#endif
240
241 unsigned int irqlogidx;
242 u32 isrlog[32];
243 u32 icrlog[32];
244
245 void __iomem *reg_base;
246 void __iomem *reg_ibmr;
247 void __iomem *reg_idbr;
248 void __iomem *reg_icr;
249 void __iomem *reg_isr;
250 void __iomem *reg_isar;
251 void __iomem *reg_ilcr;
252 void __iomem *reg_iwcr;
253
254 unsigned long iobase;
255 unsigned long iosize;
256
257 int irq;
258 unsigned int use_pio :1;
259 unsigned int fast_mode :1;
260 unsigned int high_mode:1;
261 unsigned char master_code;
262 unsigned long rate;
263 bool highmode_enter;
264 u32 fm_mask;
265 u32 hs_mask;
266
267 struct i2c_bus_recovery_info recovery;
268};
269
270#define _IBMR(i2c) ((i2c)->reg_ibmr)
271#define _IDBR(i2c) ((i2c)->reg_idbr)
272#define _ICR(i2c) ((i2c)->reg_icr)
273#define _ISR(i2c) ((i2c)->reg_isr)
274#define _ISAR(i2c) ((i2c)->reg_isar)
275#define _ILCR(i2c) ((i2c)->reg_ilcr)
276#define _IWCR(i2c) ((i2c)->reg_iwcr)
277
278/*
279 * I2C Slave mode address
280 */
281#define I2C_PXA_SLAVE_ADDR 0x1
282
283#ifdef DEBUG
284
285struct bits {
286 u32 mask;
287 const char *set;
288 const char *unset;
289};
290#define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u }
291
292static inline void
293decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
294{
295 printk("%s %08x:", prefix, val);
296 while (num--) {
297 const char *str = val & bits->mask ? bits->set : bits->unset;
298 if (str)
299 pr_cont(" %s", str);
300 bits++;
301 }
302 pr_cont("\n");
303}
304
305static const struct bits isr_bits[] = {
306 PXA_BIT(ISR_RWM, "RX", "TX"),
307 PXA_BIT(ISR_ACKNAK, "NAK", "ACK"),
308 PXA_BIT(ISR_UB, "Bsy", "Rdy"),
309 PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"),
310 PXA_BIT(ISR_SSD, "SlaveStop", NULL),
311 PXA_BIT(ISR_ALD, "ALD", NULL),
312 PXA_BIT(ISR_ITE, "TxEmpty", NULL),
313 PXA_BIT(ISR_IRF, "RxFull", NULL),
314 PXA_BIT(ISR_GCAD, "GenCall", NULL),
315 PXA_BIT(ISR_SAD, "SlaveAddr", NULL),
316 PXA_BIT(ISR_BED, "BusErr", NULL),
317};
318
319static void decode_ISR(unsigned int val)
320{
321 decode_bits(KERN_DEBUG "ISR", bits: isr_bits, ARRAY_SIZE(isr_bits), val);
322}
323
324static const struct bits icr_bits[] = {
325 PXA_BIT(ICR_START, "START", NULL),
326 PXA_BIT(ICR_STOP, "STOP", NULL),
327 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL),
328 PXA_BIT(ICR_TB, "TB", NULL),
329 PXA_BIT(ICR_MA, "MA", NULL),
330 PXA_BIT(ICR_SCLE, "SCLE", "scle"),
331 PXA_BIT(ICR_IUE, "IUE", "iue"),
332 PXA_BIT(ICR_GCD, "GCD", NULL),
333 PXA_BIT(ICR_ITEIE, "ITEIE", NULL),
334 PXA_BIT(ICR_IRFIE, "IRFIE", NULL),
335 PXA_BIT(ICR_BEIE, "BEIE", NULL),
336 PXA_BIT(ICR_SSDIE, "SSDIE", NULL),
337 PXA_BIT(ICR_ALDIE, "ALDIE", NULL),
338 PXA_BIT(ICR_SADIE, "SADIE", NULL),
339 PXA_BIT(ICR_UR, "UR", "ur"),
340};
341
342#ifdef CONFIG_I2C_PXA_SLAVE
343static void decode_ICR(unsigned int val)
344{
345 decode_bits(KERN_DEBUG "ICR", bits: icr_bits, ARRAY_SIZE(icr_bits), val);
346}
347#endif
348
349static unsigned int i2c_debug = DEBUG;
350
351static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
352{
353 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
354 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
355}
356
357#define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
358
359static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
360{
361 unsigned int i;
362 struct device *dev = &i2c->adap.dev;
363
364 dev_err(dev, "slave_0x%x error: %s\n",
365 i2c->req_slave_addr >> 1, why);
366 dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n",
367 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
368 dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n",
369 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
370 readl(_ISR(i2c)));
371 dev_err(dev, "log:");
372 for (i = 0; i < i2c->irqlogidx; i++)
373 pr_cont(" [%03x:%05x]", i2c->isrlog[i], i2c->icrlog[i]);
374 pr_cont("\n");
375}
376
377#else /* ifdef DEBUG */
378
379#define i2c_debug 0
380
381#define show_state(i2c) do { } while (0)
382#define decode_ISR(val) do { } while (0)
383#define decode_ICR(val) do { } while (0)
384#define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
385
386#endif /* ifdef DEBUG / else */
387
388static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
389
390static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
391{
392 return !(readl(_ICR(i2c)) & ICR_SCLE);
393}
394
395static void i2c_pxa_abort(struct pxa_i2c *i2c)
396{
397 int i = 250;
398
399 if (i2c_pxa_is_slavemode(i2c)) {
400 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
401 return;
402 }
403
404 while ((i > 0) && (readl(_IBMR(i2c)) & IBMR_SDAS) == 0) {
405 unsigned long icr = readl(_ICR(i2c));
406
407 icr &= ~ICR_START;
408 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
409
410 writel(val: icr, _ICR(i2c));
411
412 show_state(i2c);
413
414 mdelay(1);
415 i --;
416 }
417
418 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
419 _ICR(i2c));
420}
421
422static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
423{
424 int timeout = DEF_TIMEOUT;
425 u32 isr;
426
427 while (1) {
428 isr = readl(_ISR(i2c));
429 if (!(isr & (ISR_IBB | ISR_UB)))
430 return 0;
431
432 if (isr & ISR_SAD)
433 timeout += 4;
434
435 if (!timeout--)
436 break;
437
438 msleep(msecs: 2);
439 show_state(i2c);
440 }
441
442 show_state(i2c);
443
444 return I2C_RETRY;
445}
446
447static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
448{
449 unsigned long timeout = jiffies + HZ*4;
450
451 while (time_before(jiffies, timeout)) {
452 if (i2c_debug > 1)
453 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
454 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
455
456 if (readl(_ISR(i2c)) & ISR_SAD) {
457 if (i2c_debug > 0)
458 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
459 goto out;
460 }
461
462 /* wait for unit and bus being not busy, and we also do a
463 * quick check of the i2c lines themselves to ensure they've
464 * gone high...
465 */
466 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 &&
467 readl(_IBMR(i2c)) == (IBMR_SCLS | IBMR_SDAS)) {
468 if (i2c_debug > 0)
469 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
470 return 1;
471 }
472
473 msleep(msecs: 1);
474 }
475
476 if (i2c_debug > 0)
477 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
478 out:
479 return 0;
480}
481
482static int i2c_pxa_set_master(struct pxa_i2c *i2c)
483{
484 if (i2c_debug)
485 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
486
487 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
488 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
489 if (!i2c_pxa_wait_master(i2c)) {
490 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
491 return I2C_RETRY;
492 }
493 }
494
495 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
496 return 0;
497}
498
499#ifdef CONFIG_I2C_PXA_SLAVE
500static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
501{
502 unsigned long timeout = jiffies + HZ*1;
503
504 /* wait for stop */
505
506 show_state(i2c);
507
508 while (time_before(jiffies, timeout)) {
509 if (i2c_debug > 1)
510 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
511 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
512
513 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
514 (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
515 (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
516 if (i2c_debug > 1)
517 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
518 return 1;
519 }
520
521 msleep(msecs: 1);
522 }
523
524 if (i2c_debug > 0)
525 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
526 return 0;
527}
528
529/*
530 * clear the hold on the bus, and take of anything else
531 * that has been configured
532 */
533static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
534{
535 show_state(i2c);
536
537 if (errcode < 0) {
538 udelay(100); /* simple delay */
539 } else {
540 /* we need to wait for the stop condition to end */
541
542 /* if we where in stop, then clear... */
543 if (readl(_ICR(i2c)) & ICR_STOP) {
544 udelay(100);
545 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
546 }
547
548 if (!i2c_pxa_wait_slave(i2c)) {
549 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
550 __func__);
551 return;
552 }
553 }
554
555 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
556 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
557
558 if (i2c_debug) {
559 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
560 decode_ICR(readl(_ICR(i2c)));
561 }
562}
563#else
564#define i2c_pxa_set_slave(i2c, err) do { } while (0)
565#endif
566
567static void i2c_pxa_do_reset(struct pxa_i2c *i2c)
568{
569 /* reset according to 9.8 */
570 writel(ICR_UR, _ICR(i2c));
571 writel(I2C_ISR_INIT, _ISR(i2c));
572 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
573
574 if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
575 writel(val: i2c->slave_addr, _ISAR(i2c));
576
577 /* set control register values */
578 writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
579 writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
580
581#ifdef CONFIG_I2C_PXA_SLAVE
582 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
583 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
584#endif
585
586 i2c_pxa_set_slave(i2c, errcode: 0);
587}
588
589static void i2c_pxa_enable(struct pxa_i2c *i2c)
590{
591 /* enable unit */
592 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
593 udelay(100);
594}
595
596static void i2c_pxa_reset(struct pxa_i2c *i2c)
597{
598 pr_debug("Resetting I2C Controller Unit\n");
599
600 /* abort any transfer currently under way */
601 i2c_pxa_abort(i2c);
602 i2c_pxa_do_reset(i2c);
603 i2c_pxa_enable(i2c);
604}
605
606
607#ifdef CONFIG_I2C_PXA_SLAVE
608/*
609 * PXA I2C Slave mode
610 */
611
612static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
613{
614 if (isr & ISR_BED) {
615 /* what should we do here? */
616 } else {
617 u8 byte = 0;
618
619 if (i2c->slave != NULL)
620 i2c_slave_event(client: i2c->slave, event: I2C_SLAVE_READ_PROCESSED,
621 val: &byte);
622
623 writel(val: byte, _IDBR(i2c));
624 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */
625 }
626}
627
628static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
629{
630 u8 byte = readl(_IDBR(i2c));
631
632 if (i2c->slave != NULL)
633 i2c_slave_event(client: i2c->slave, event: I2C_SLAVE_WRITE_RECEIVED, val: &byte);
634
635 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
636}
637
638static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
639{
640 int timeout;
641
642 if (i2c_debug > 0)
643 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
644 (isr & ISR_RWM) ? 'r' : 't');
645
646 if (i2c->slave != NULL) {
647 if (isr & ISR_RWM) {
648 u8 byte = 0;
649
650 i2c_slave_event(client: i2c->slave, event: I2C_SLAVE_READ_REQUESTED,
651 val: &byte);
652 writel(val: byte, _IDBR(i2c));
653 } else {
654 i2c_slave_event(client: i2c->slave, event: I2C_SLAVE_WRITE_REQUESTED,
655 NULL);
656 }
657 }
658
659 /*
660 * slave could interrupt in the middle of us generating a
661 * start condition... if this happens, we'd better back off
662 * and stop holding the poor thing up
663 */
664 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
665 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
666
667 timeout = 0x10000;
668
669 while (1) {
670 if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
671 break;
672
673 timeout--;
674
675 if (timeout <= 0) {
676 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
677 break;
678 }
679 }
680
681 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
682}
683
684static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
685{
686 if (i2c_debug > 2)
687 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
688
689 if (i2c->slave != NULL)
690 i2c_slave_event(client: i2c->slave, event: I2C_SLAVE_STOP, NULL);
691
692 if (i2c_debug > 2)
693 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
694
695 /*
696 * If we have a master-mode message waiting,
697 * kick it off now that the slave has completed.
698 */
699 if (i2c->msg)
700 i2c_pxa_master_complete(i2c, I2C_RETRY);
701}
702
703static int i2c_pxa_slave_reg(struct i2c_client *slave)
704{
705 struct pxa_i2c *i2c = slave->adapter->algo_data;
706
707 if (i2c->slave)
708 return -EBUSY;
709
710 if (!i2c->reg_isar)
711 return -EAFNOSUPPORT;
712
713 i2c->slave = slave;
714 i2c->slave_addr = slave->addr;
715
716 writel(val: i2c->slave_addr, _ISAR(i2c));
717
718 return 0;
719}
720
721static int i2c_pxa_slave_unreg(struct i2c_client *slave)
722{
723 struct pxa_i2c *i2c = slave->adapter->algo_data;
724
725 WARN_ON(!i2c->slave);
726
727 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
728 writel(val: i2c->slave_addr, _ISAR(i2c));
729
730 i2c->slave = NULL;
731
732 return 0;
733}
734#else
735static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
736{
737 if (isr & ISR_BED) {
738 /* what should we do here? */
739 } else {
740 writel(0, _IDBR(i2c));
741 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
742 }
743}
744
745static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
746{
747 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
748}
749
750static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
751{
752 int timeout;
753
754 /*
755 * slave could interrupt in the middle of us generating a
756 * start condition... if this happens, we'd better back off
757 * and stop holding the poor thing up
758 */
759 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
760 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
761
762 timeout = 0x10000;
763
764 while (1) {
765 if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
766 break;
767
768 timeout--;
769
770 if (timeout <= 0) {
771 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
772 break;
773 }
774 }
775
776 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
777}
778
779static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
780{
781 if (i2c->msg)
782 i2c_pxa_master_complete(i2c, I2C_RETRY);
783}
784#endif
785
786/*
787 * PXA I2C Master mode
788 */
789
790static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
791{
792 u32 icr;
793
794 /*
795 * Step 1: target slave address into IDBR
796 */
797 i2c->req_slave_addr = i2c_8bit_addr_from_msg(msg: i2c->msg);
798 writel(val: i2c->req_slave_addr, _IDBR(i2c));
799
800 /*
801 * Step 2: initiate the write.
802 */
803 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
804 writel(val: icr | ICR_START | ICR_TB, _ICR(i2c));
805}
806
807static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
808{
809 u32 icr;
810
811 /* Clear the START, STOP, ACK, TB and MA flags */
812 icr = readl(_ICR(i2c));
813 icr &= ~(ICR_START | ICR_STOP | ICR_ACKNAK | ICR_TB | ICR_MA);
814 writel(val: icr, _ICR(i2c));
815}
816
817/*
818 * PXA I2C send master code
819 * 1. Load master code to IDBR and send it.
820 * Note for HS mode, set ICR [GPIOEN].
821 * 2. Wait until win arbitration.
822 */
823static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c)
824{
825 u32 icr;
826 long timeout;
827
828 spin_lock_irq(lock: &i2c->lock);
829 i2c->highmode_enter = true;
830 writel(val: i2c->master_code, _IDBR(i2c));
831
832 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
833 icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE;
834 writel(val: icr, _ICR(i2c));
835
836 spin_unlock_irq(lock: &i2c->lock);
837 timeout = wait_event_timeout(i2c->wait,
838 i2c->highmode_enter == false, HZ * 1);
839
840 i2c->highmode_enter = false;
841
842 return (timeout == 0) ? I2C_RETRY : 0;
843}
844
845/*
846 * i2c_pxa_master_complete - complete the message and wake up.
847 */
848static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
849{
850 i2c->msg_ptr = 0;
851 i2c->msg = NULL;
852 i2c->msg_idx ++;
853 i2c->msg_num = 0;
854 if (ret)
855 i2c->msg_idx = ret;
856 if (!i2c->use_pio)
857 wake_up(&i2c->wait);
858}
859
860static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
861{
862 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
863
864 again:
865 /*
866 * If ISR_ALD is set, we lost arbitration.
867 */
868 if (isr & ISR_ALD) {
869 /*
870 * Do we need to do anything here? The PXA docs
871 * are vague about what happens.
872 */
873 i2c_pxa_scream_blue_murder(i2c, why: "ALD set");
874
875 /*
876 * We ignore this error. We seem to see spurious ALDs
877 * for seemingly no reason. If we handle them as I think
878 * they should, we end up causing an I2C error, which
879 * is painful for some systems.
880 */
881 return; /* ignore */
882 }
883
884 if ((isr & ISR_BED) &&
885 (!((i2c->msg->flags & I2C_M_IGNORE_NAK) &&
886 (isr & ISR_ACKNAK)))) {
887 int ret = BUS_ERROR;
888
889 /*
890 * I2C bus error - either the device NAK'd us, or
891 * something more serious happened. If we were NAK'd
892 * on the initial address phase, we can retry.
893 */
894 if (isr & ISR_ACKNAK) {
895 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
896 ret = NO_SLAVE;
897 else
898 ret = XFER_NAKED;
899 }
900 i2c_pxa_master_complete(i2c, ret);
901 } else if (isr & ISR_RWM) {
902 /*
903 * Read mode. We have just sent the address byte, and
904 * now we must initiate the transfer.
905 */
906 if (i2c->msg_ptr == i2c->msg->len - 1 &&
907 i2c->msg_idx == i2c->msg_num - 1)
908 icr |= ICR_STOP | ICR_ACKNAK;
909
910 icr |= ICR_ALDIE | ICR_TB;
911 } else if (i2c->msg_ptr < i2c->msg->len) {
912 /*
913 * Write mode. Write the next data byte.
914 */
915 writel(val: i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
916
917 icr |= ICR_ALDIE | ICR_TB;
918
919 /*
920 * If this is the last byte of the last message or last byte
921 * of any message with I2C_M_STOP (e.g. SCCB), send a STOP.
922 */
923 if ((i2c->msg_ptr == i2c->msg->len) &&
924 ((i2c->msg->flags & I2C_M_STOP) ||
925 (i2c->msg_idx == i2c->msg_num - 1)))
926 icr |= ICR_STOP;
927
928 } else if (i2c->msg_idx < i2c->msg_num - 1) {
929 /*
930 * Next segment of the message.
931 */
932 i2c->msg_ptr = 0;
933 i2c->msg_idx ++;
934 i2c->msg++;
935
936 /*
937 * If we aren't doing a repeated start and address,
938 * go back and try to send the next byte. Note that
939 * we do not support switching the R/W direction here.
940 */
941 if (i2c->msg->flags & I2C_M_NOSTART)
942 goto again;
943
944 /*
945 * Write the next address.
946 */
947 i2c->req_slave_addr = i2c_8bit_addr_from_msg(msg: i2c->msg);
948 writel(val: i2c->req_slave_addr, _IDBR(i2c));
949
950 /*
951 * And trigger a repeated start, and send the byte.
952 */
953 icr &= ~ICR_ALDIE;
954 icr |= ICR_START | ICR_TB;
955 } else {
956 if (i2c->msg->len == 0)
957 icr |= ICR_MA;
958 i2c_pxa_master_complete(i2c, ret: 0);
959 }
960
961 i2c->icrlog[i2c->irqlogidx-1] = icr;
962
963 writel(val: icr, _ICR(i2c));
964 show_state(i2c);
965}
966
967static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
968{
969 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
970
971 /*
972 * Read the byte.
973 */
974 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
975
976 if (i2c->msg_ptr < i2c->msg->len) {
977 /*
978 * If this is the last byte of the last
979 * message, send a STOP.
980 */
981 if (i2c->msg_ptr == i2c->msg->len - 1)
982 icr |= ICR_STOP | ICR_ACKNAK;
983
984 icr |= ICR_ALDIE | ICR_TB;
985 } else {
986 i2c_pxa_master_complete(i2c, ret: 0);
987 }
988
989 i2c->icrlog[i2c->irqlogidx-1] = icr;
990
991 writel(val: icr, _ICR(i2c));
992}
993
994#define VALID_INT_SOURCE (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \
995 ISR_SAD | ISR_BED)
996static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
997{
998 struct pxa_i2c *i2c = dev_id;
999 u32 isr = readl(_ISR(i2c));
1000
1001 if (!(isr & VALID_INT_SOURCE))
1002 return IRQ_NONE;
1003
1004 if (i2c_debug > 2 && 0) {
1005 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
1006 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
1007 decode_ISR(val: isr);
1008 }
1009
1010 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
1011 i2c->isrlog[i2c->irqlogidx++] = isr;
1012
1013 show_state(i2c);
1014
1015 /*
1016 * Always clear all pending IRQs.
1017 */
1018 writel(val: isr & VALID_INT_SOURCE, _ISR(i2c));
1019
1020 if (isr & ISR_SAD)
1021 i2c_pxa_slave_start(i2c, isr);
1022 if (isr & ISR_SSD)
1023 i2c_pxa_slave_stop(i2c);
1024
1025 if (i2c_pxa_is_slavemode(i2c)) {
1026 if (isr & ISR_ITE)
1027 i2c_pxa_slave_txempty(i2c, isr);
1028 if (isr & ISR_IRF)
1029 i2c_pxa_slave_rxfull(i2c, isr);
1030 } else if (i2c->msg && (!i2c->highmode_enter)) {
1031 if (isr & ISR_ITE)
1032 i2c_pxa_irq_txempty(i2c, isr);
1033 if (isr & ISR_IRF)
1034 i2c_pxa_irq_rxfull(i2c, isr);
1035 } else if ((isr & ISR_ITE) && i2c->highmode_enter) {
1036 i2c->highmode_enter = false;
1037 wake_up(&i2c->wait);
1038 } else {
1039 i2c_pxa_scream_blue_murder(i2c, why: "spurious irq");
1040 }
1041
1042 return IRQ_HANDLED;
1043}
1044
1045/*
1046 * We are protected by the adapter bus mutex.
1047 */
1048static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
1049{
1050 long timeout;
1051 int ret;
1052
1053 /*
1054 * Wait for the bus to become free.
1055 */
1056 ret = i2c_pxa_wait_bus_not_busy(i2c);
1057 if (ret) {
1058 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
1059 i2c_recover_bus(adap: &i2c->adap);
1060 goto out;
1061 }
1062
1063 /*
1064 * Set master mode.
1065 */
1066 ret = i2c_pxa_set_master(i2c);
1067 if (ret) {
1068 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
1069 goto out;
1070 }
1071
1072 if (i2c->high_mode) {
1073 ret = i2c_pxa_send_mastercode(i2c);
1074 if (ret) {
1075 dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
1076 goto out;
1077 }
1078 }
1079
1080 spin_lock_irq(lock: &i2c->lock);
1081
1082 i2c->msg = msg;
1083 i2c->msg_num = num;
1084 i2c->msg_idx = 0;
1085 i2c->msg_ptr = 0;
1086 i2c->irqlogidx = 0;
1087
1088 i2c_pxa_start_message(i2c);
1089
1090 spin_unlock_irq(lock: &i2c->lock);
1091
1092 /*
1093 * The rest of the processing occurs in the interrupt handler.
1094 */
1095 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
1096 i2c_pxa_stop_message(i2c);
1097
1098 /*
1099 * We place the return code in i2c->msg_idx.
1100 */
1101 ret = i2c->msg_idx;
1102
1103 if (!timeout && i2c->msg_num) {
1104 i2c_pxa_scream_blue_murder(i2c, why: "timeout with active message");
1105 i2c_recover_bus(adap: &i2c->adap);
1106 ret = I2C_RETRY;
1107 }
1108
1109 out:
1110 return ret;
1111}
1112
1113static int i2c_pxa_internal_xfer(struct pxa_i2c *i2c,
1114 struct i2c_msg *msgs, int num,
1115 int (*xfer)(struct pxa_i2c *,
1116 struct i2c_msg *, int num))
1117{
1118 int ret, i;
1119
1120 for (i = 0; ; ) {
1121 ret = xfer(i2c, msgs, num);
1122 if (ret != I2C_RETRY && ret != NO_SLAVE)
1123 goto out;
1124 if (++i >= i2c->adap.retries)
1125 break;
1126
1127 if (i2c_debug)
1128 dev_dbg(&i2c->adap.dev, "Retrying transmission\n");
1129 udelay(100);
1130 }
1131 if (ret != NO_SLAVE)
1132 i2c_pxa_scream_blue_murder(i2c, why: "exhausted retries");
1133 ret = -EREMOTEIO;
1134 out:
1135 i2c_pxa_set_slave(i2c, errcode: ret);
1136 return ret;
1137}
1138
1139static int i2c_pxa_xfer(struct i2c_adapter *adap,
1140 struct i2c_msg msgs[], int num)
1141{
1142 struct pxa_i2c *i2c = adap->algo_data;
1143
1144 return i2c_pxa_internal_xfer(i2c, msgs, num, xfer: i2c_pxa_do_xfer);
1145}
1146
1147static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
1148{
1149 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1150 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
1151}
1152
1153static const struct i2c_algorithm i2c_pxa_algorithm = {
1154 .master_xfer = i2c_pxa_xfer,
1155 .functionality = i2c_pxa_functionality,
1156#ifdef CONFIG_I2C_PXA_SLAVE
1157 .reg_slave = i2c_pxa_slave_reg,
1158 .unreg_slave = i2c_pxa_slave_unreg,
1159#endif
1160};
1161
1162/* Non-interrupt mode support */
1163static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
1164{
1165 /* make timeout the same as for interrupt based functions */
1166 long timeout = 2 * DEF_TIMEOUT;
1167
1168 /*
1169 * Wait for the bus to become free.
1170 */
1171 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB))
1172 udelay(1000);
1173
1174 if (timeout < 0) {
1175 show_state(i2c);
1176 dev_err(&i2c->adap.dev,
1177 "i2c_pxa: timeout waiting for bus free (set_master)\n");
1178 return I2C_RETRY;
1179 }
1180
1181 /*
1182 * Set master mode.
1183 */
1184 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
1185
1186 return 0;
1187}
1188
1189static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
1190 struct i2c_msg *msg, int num)
1191{
1192 unsigned long timeout = 500000; /* 5 seconds */
1193 int ret = 0;
1194
1195 ret = i2c_pxa_pio_set_master(i2c);
1196 if (ret)
1197 goto out;
1198
1199 i2c->msg = msg;
1200 i2c->msg_num = num;
1201 i2c->msg_idx = 0;
1202 i2c->msg_ptr = 0;
1203 i2c->irqlogidx = 0;
1204
1205 i2c_pxa_start_message(i2c);
1206
1207 while (i2c->msg_num > 0 && --timeout) {
1208 i2c_pxa_handler(this_irq: 0, dev_id: i2c);
1209 udelay(10);
1210 }
1211
1212 i2c_pxa_stop_message(i2c);
1213
1214 /*
1215 * We place the return code in i2c->msg_idx.
1216 */
1217 ret = i2c->msg_idx;
1218
1219out:
1220 if (timeout == 0) {
1221 i2c_pxa_scream_blue_murder(i2c, why: "timeout (do_pio_xfer)");
1222 ret = I2C_RETRY;
1223 }
1224
1225 return ret;
1226}
1227
1228static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
1229 struct i2c_msg msgs[], int num)
1230{
1231 struct pxa_i2c *i2c = adap->algo_data;
1232
1233 /* If the I2C controller is disabled we need to reset it
1234 (probably due to a suspend/resume destroying state). We do
1235 this here as we can then avoid worrying about resuming the
1236 controller before its users. */
1237 if (!(readl(_ICR(i2c)) & ICR_IUE))
1238 i2c_pxa_reset(i2c);
1239
1240 return i2c_pxa_internal_xfer(i2c, msgs, num, xfer: i2c_pxa_do_pio_xfer);
1241}
1242
1243static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1244 .master_xfer = i2c_pxa_pio_xfer,
1245 .functionality = i2c_pxa_functionality,
1246#ifdef CONFIG_I2C_PXA_SLAVE
1247 .reg_slave = i2c_pxa_slave_reg,
1248 .unreg_slave = i2c_pxa_slave_unreg,
1249#endif
1250};
1251
1252static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
1253 enum pxa_i2c_types *i2c_types)
1254{
1255 struct device_node *np = pdev->dev.of_node;
1256
1257 if (!pdev->dev.of_node)
1258 return 1;
1259
1260 /* For device tree we always use the dynamic or alias-assigned ID */
1261 i2c->adap.nr = -1;
1262
1263 i2c->use_pio = of_property_read_bool(np, propname: "mrvl,i2c-polling");
1264 i2c->fast_mode = of_property_read_bool(np, propname: "mrvl,i2c-fast-mode");
1265
1266 *i2c_types = (enum pxa_i2c_types)device_get_match_data(dev: &pdev->dev);
1267
1268 return 0;
1269}
1270
1271static int i2c_pxa_probe_pdata(struct platform_device *pdev,
1272 struct pxa_i2c *i2c,
1273 enum pxa_i2c_types *i2c_types)
1274{
1275 struct i2c_pxa_platform_data *plat = dev_get_platdata(dev: &pdev->dev);
1276 const struct platform_device_id *id = platform_get_device_id(pdev);
1277
1278 *i2c_types = id->driver_data;
1279 if (plat) {
1280 i2c->use_pio = plat->use_pio;
1281 i2c->fast_mode = plat->fast_mode;
1282 i2c->high_mode = plat->high_mode;
1283 i2c->master_code = plat->master_code;
1284 if (!i2c->master_code)
1285 i2c->master_code = 0xe;
1286 i2c->rate = plat->rate;
1287 }
1288 return 0;
1289}
1290
1291static void i2c_pxa_prepare_recovery(struct i2c_adapter *adap)
1292{
1293 struct pxa_i2c *i2c = adap->algo_data;
1294 u32 ibmr = readl(_IBMR(i2c));
1295
1296 /*
1297 * Program the GPIOs to reflect the current I2C bus state while
1298 * we transition to recovery; this avoids glitching the bus.
1299 */
1300 gpiod_set_value(desc: i2c->recovery.scl_gpiod, value: ibmr & IBMR_SCLS);
1301 gpiod_set_value(desc: i2c->recovery.sda_gpiod, value: ibmr & IBMR_SDAS);
1302}
1303
1304static void i2c_pxa_unprepare_recovery(struct i2c_adapter *adap)
1305{
1306 struct pxa_i2c *i2c = adap->algo_data;
1307 struct i2c_bus_recovery_info *bri = adap->bus_recovery_info;
1308 u32 isr;
1309
1310 /*
1311 * The bus should now be free. Clear up the I2C controller before
1312 * handing control of the bus back to avoid the bus changing state.
1313 */
1314 isr = readl(_ISR(i2c));
1315 if (isr & (ISR_UB | ISR_IBB)) {
1316 dev_dbg(&i2c->adap.dev,
1317 "recovery: resetting controller, ISR=0x%08x\n", isr);
1318 i2c_pxa_do_reset(i2c);
1319 }
1320
1321 WARN_ON(pinctrl_select_state(bri->pinctrl, bri->pins_default));
1322
1323 dev_dbg(&i2c->adap.dev, "recovery: IBMR 0x%08x ISR 0x%08x\n",
1324 readl(_IBMR(i2c)), readl(_ISR(i2c)));
1325
1326 i2c_pxa_enable(i2c);
1327}
1328
1329static int i2c_pxa_init_recovery(struct pxa_i2c *i2c)
1330{
1331 struct i2c_bus_recovery_info *bri = &i2c->recovery;
1332 struct device *dev = i2c->adap.dev.parent;
1333
1334 /*
1335 * When slave mode is enabled, we are not the only master on the bus.
1336 * Bus recovery can only be performed when we are the master, which
1337 * we can't be certain of. Therefore, when slave mode is enabled, do
1338 * not configure bus recovery.
1339 */
1340 if (IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
1341 return 0;
1342
1343 bri->pinctrl = devm_pinctrl_get(dev);
1344 if (PTR_ERR(ptr: bri->pinctrl) == -ENODEV) {
1345 bri->pinctrl = NULL;
1346 return 0;
1347 }
1348 if (IS_ERR(ptr: bri->pinctrl))
1349 return PTR_ERR(ptr: bri->pinctrl);
1350
1351 bri->prepare_recovery = i2c_pxa_prepare_recovery;
1352 bri->unprepare_recovery = i2c_pxa_unprepare_recovery;
1353
1354 i2c->adap.bus_recovery_info = bri;
1355
1356 return 0;
1357}
1358
1359static int i2c_pxa_probe(struct platform_device *dev)
1360{
1361 struct i2c_pxa_platform_data *plat = dev_get_platdata(dev: &dev->dev);
1362 enum pxa_i2c_types i2c_type;
1363 struct pxa_i2c *i2c;
1364 struct resource *res;
1365 int ret, irq;
1366
1367 i2c = devm_kzalloc(dev: &dev->dev, size: sizeof(struct pxa_i2c), GFP_KERNEL);
1368 if (!i2c)
1369 return -ENOMEM;
1370
1371 /* Default adapter num to device id; i2c_pxa_probe_dt can override. */
1372 i2c->adap.nr = dev->id;
1373 i2c->adap.owner = THIS_MODULE;
1374 i2c->adap.retries = 5;
1375 i2c->adap.algo_data = i2c;
1376 i2c->adap.dev.parent = &dev->dev;
1377#ifdef CONFIG_OF
1378 i2c->adap.dev.of_node = dev->dev.of_node;
1379#endif
1380
1381 i2c->reg_base = devm_platform_get_and_ioremap_resource(pdev: dev, index: 0, res: &res);
1382 if (IS_ERR(ptr: i2c->reg_base))
1383 return PTR_ERR(ptr: i2c->reg_base);
1384
1385 irq = platform_get_irq(dev, 0);
1386 if (irq < 0)
1387 return irq;
1388
1389 ret = i2c_pxa_init_recovery(i2c);
1390 if (ret)
1391 return ret;
1392
1393 ret = i2c_pxa_probe_dt(pdev: dev, i2c, i2c_types: &i2c_type);
1394 if (ret > 0)
1395 ret = i2c_pxa_probe_pdata(pdev: dev, i2c, i2c_types: &i2c_type);
1396 if (ret < 0)
1397 return ret;
1398
1399 spin_lock_init(&i2c->lock);
1400 init_waitqueue_head(&i2c->wait);
1401
1402 strscpy(p: i2c->adap.name, q: "pxa_i2c-i2c", size: sizeof(i2c->adap.name));
1403
1404 i2c->clk = devm_clk_get(dev: &dev->dev, NULL);
1405 if (IS_ERR(ptr: i2c->clk))
1406 return dev_err_probe(dev: &dev->dev, err: PTR_ERR(ptr: i2c->clk),
1407 fmt: "failed to get the clk\n");
1408
1409 i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1410 i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1411 i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1412 i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1413 i2c->fm_mask = pxa_reg_layout[i2c_type].fm;
1414 i2c->hs_mask = pxa_reg_layout[i2c_type].hs;
1415
1416 if (i2c_type != REGS_CE4100)
1417 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1418
1419 if (i2c_type == REGS_PXA910) {
1420 i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr;
1421 i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr;
1422 }
1423
1424 i2c->iobase = res->start;
1425 i2c->iosize = resource_size(res);
1426
1427 i2c->irq = irq;
1428
1429 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1430 i2c->highmode_enter = false;
1431
1432 if (plat) {
1433 i2c->adap.class = plat->class;
1434 }
1435
1436 if (i2c->high_mode) {
1437 if (i2c->rate) {
1438 clk_set_rate(clk: i2c->clk, rate: i2c->rate);
1439 pr_info("i2c: <%s> set rate to %ld\n",
1440 i2c->adap.name, clk_get_rate(i2c->clk));
1441 } else
1442 pr_warn("i2c: <%s> clock rate not set\n",
1443 i2c->adap.name);
1444 }
1445
1446 clk_prepare_enable(clk: i2c->clk);
1447
1448 if (i2c->use_pio) {
1449 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1450 } else {
1451 i2c->adap.algo = &i2c_pxa_algorithm;
1452 ret = devm_request_irq(dev: &dev->dev, irq, handler: i2c_pxa_handler,
1453 IRQF_SHARED | IRQF_NO_SUSPEND,
1454 devname: dev_name(dev: &dev->dev), dev_id: i2c);
1455 if (ret) {
1456 dev_err(&dev->dev, "failed to request irq: %d\n", ret);
1457 goto ereqirq;
1458 }
1459 }
1460
1461 i2c_pxa_reset(i2c);
1462
1463 ret = i2c_add_numbered_adapter(adap: &i2c->adap);
1464 if (ret < 0)
1465 goto ereqirq;
1466
1467 platform_set_drvdata(pdev: dev, data: i2c);
1468
1469#ifdef CONFIG_I2C_PXA_SLAVE
1470 dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n",
1471 i2c->slave_addr);
1472#else
1473 dev_info(&i2c->adap.dev, " PXA I2C adapter\n");
1474#endif
1475 return 0;
1476
1477ereqirq:
1478 clk_disable_unprepare(clk: i2c->clk);
1479 return ret;
1480}
1481
1482static void i2c_pxa_remove(struct platform_device *dev)
1483{
1484 struct pxa_i2c *i2c = platform_get_drvdata(pdev: dev);
1485
1486 i2c_del_adapter(adap: &i2c->adap);
1487
1488 clk_disable_unprepare(clk: i2c->clk);
1489}
1490
1491static int i2c_pxa_suspend_noirq(struct device *dev)
1492{
1493 struct pxa_i2c *i2c = dev_get_drvdata(dev);
1494
1495 clk_disable(clk: i2c->clk);
1496
1497 return 0;
1498}
1499
1500static int i2c_pxa_resume_noirq(struct device *dev)
1501{
1502 struct pxa_i2c *i2c = dev_get_drvdata(dev);
1503
1504 clk_enable(clk: i2c->clk);
1505 i2c_pxa_reset(i2c);
1506
1507 return 0;
1508}
1509
1510static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1511 .suspend_noirq = i2c_pxa_suspend_noirq,
1512 .resume_noirq = i2c_pxa_resume_noirq,
1513};
1514
1515static struct platform_driver i2c_pxa_driver = {
1516 .probe = i2c_pxa_probe,
1517 .remove_new = i2c_pxa_remove,
1518 .driver = {
1519 .name = "pxa2xx-i2c",
1520 .pm = pm_sleep_ptr(&i2c_pxa_dev_pm_ops),
1521 .of_match_table = i2c_pxa_dt_ids,
1522 },
1523 .id_table = i2c_pxa_id_table,
1524};
1525
1526static int __init i2c_adap_pxa_init(void)
1527{
1528 return platform_driver_register(&i2c_pxa_driver);
1529}
1530
1531static void __exit i2c_adap_pxa_exit(void)
1532{
1533 platform_driver_unregister(&i2c_pxa_driver);
1534}
1535
1536MODULE_LICENSE("GPL");
1537
1538subsys_initcall(i2c_adap_pxa_init);
1539module_exit(i2c_adap_pxa_exit);
1540

source code of linux/drivers/i2c/busses/i2c-pxa.c