1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Driver for STMicroelectronics STM32 I2C controller |
4 | * |
5 | * This I2C controller is described in the STM32F429/439 Soc reference manual. |
6 | * Please see below a link to the documentation: |
7 | * http://www.st.com/resource/en/reference_manual/DM00031020.pdf |
8 | * |
9 | * Copyright (C) M'boumba Cedric Madianga 2016 |
10 | * Copyright (C) STMicroelectronics 2017 |
11 | * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> |
12 | * |
13 | * This driver is based on i2c-st.c |
14 | * |
15 | */ |
16 | |
17 | #include <linux/clk.h> |
18 | #include <linux/delay.h> |
19 | #include <linux/err.h> |
20 | #include <linux/i2c.h> |
21 | #include <linux/interrupt.h> |
22 | #include <linux/io.h> |
23 | #include <linux/iopoll.h> |
24 | #include <linux/module.h> |
25 | #include <linux/of_address.h> |
26 | #include <linux/of_irq.h> |
27 | #include <linux/of.h> |
28 | #include <linux/platform_device.h> |
29 | #include <linux/reset.h> |
30 | |
31 | #include "i2c-stm32.h" |
32 | |
33 | /* STM32F4 I2C offset registers */ |
34 | #define STM32F4_I2C_CR1 0x00 |
35 | #define STM32F4_I2C_CR2 0x04 |
36 | #define STM32F4_I2C_DR 0x10 |
37 | #define STM32F4_I2C_SR1 0x14 |
38 | #define STM32F4_I2C_SR2 0x18 |
39 | #define STM32F4_I2C_CCR 0x1C |
40 | #define STM32F4_I2C_TRISE 0x20 |
41 | #define STM32F4_I2C_FLTR 0x24 |
42 | |
43 | /* STM32F4 I2C control 1*/ |
44 | #define STM32F4_I2C_CR1_POS BIT(11) |
45 | #define STM32F4_I2C_CR1_ACK BIT(10) |
46 | #define STM32F4_I2C_CR1_STOP BIT(9) |
47 | #define STM32F4_I2C_CR1_START BIT(8) |
48 | #define STM32F4_I2C_CR1_PE BIT(0) |
49 | |
50 | /* STM32F4 I2C control 2 */ |
51 | #define STM32F4_I2C_CR2_FREQ_MASK GENMASK(5, 0) |
52 | #define STM32F4_I2C_CR2_FREQ(n) ((n) & STM32F4_I2C_CR2_FREQ_MASK) |
53 | #define STM32F4_I2C_CR2_ITBUFEN BIT(10) |
54 | #define STM32F4_I2C_CR2_ITEVTEN BIT(9) |
55 | #define STM32F4_I2C_CR2_ITERREN BIT(8) |
56 | #define STM32F4_I2C_CR2_IRQ_MASK (STM32F4_I2C_CR2_ITBUFEN | \ |
57 | STM32F4_I2C_CR2_ITEVTEN | \ |
58 | STM32F4_I2C_CR2_ITERREN) |
59 | |
60 | /* STM32F4 I2C Status 1 */ |
61 | #define STM32F4_I2C_SR1_AF BIT(10) |
62 | #define STM32F4_I2C_SR1_ARLO BIT(9) |
63 | #define STM32F4_I2C_SR1_BERR BIT(8) |
64 | #define STM32F4_I2C_SR1_TXE BIT(7) |
65 | #define STM32F4_I2C_SR1_RXNE BIT(6) |
66 | #define STM32F4_I2C_SR1_BTF BIT(2) |
67 | #define STM32F4_I2C_SR1_ADDR BIT(1) |
68 | #define STM32F4_I2C_SR1_SB BIT(0) |
69 | #define STM32F4_I2C_SR1_ITEVTEN_MASK (STM32F4_I2C_SR1_BTF | \ |
70 | STM32F4_I2C_SR1_ADDR | \ |
71 | STM32F4_I2C_SR1_SB) |
72 | #define STM32F4_I2C_SR1_ITBUFEN_MASK (STM32F4_I2C_SR1_TXE | \ |
73 | STM32F4_I2C_SR1_RXNE) |
74 | #define STM32F4_I2C_SR1_ITERREN_MASK (STM32F4_I2C_SR1_AF | \ |
75 | STM32F4_I2C_SR1_ARLO | \ |
76 | STM32F4_I2C_SR1_BERR) |
77 | |
78 | /* STM32F4 I2C Status 2 */ |
79 | #define STM32F4_I2C_SR2_BUSY BIT(1) |
80 | |
81 | /* STM32F4 I2C Control Clock */ |
82 | #define STM32F4_I2C_CCR_CCR_MASK GENMASK(11, 0) |
83 | #define STM32F4_I2C_CCR_CCR(n) ((n) & STM32F4_I2C_CCR_CCR_MASK) |
84 | #define STM32F4_I2C_CCR_FS BIT(15) |
85 | #define STM32F4_I2C_CCR_DUTY BIT(14) |
86 | |
87 | /* STM32F4 I2C Trise */ |
88 | #define STM32F4_I2C_TRISE_VALUE_MASK GENMASK(5, 0) |
89 | #define STM32F4_I2C_TRISE_VALUE(n) ((n) & STM32F4_I2C_TRISE_VALUE_MASK) |
90 | |
91 | #define STM32F4_I2C_MIN_STANDARD_FREQ 2U |
92 | #define STM32F4_I2C_MIN_FAST_FREQ 6U |
93 | #define STM32F4_I2C_MAX_FREQ 46U |
94 | #define HZ_TO_MHZ 1000000 |
95 | |
96 | /** |
97 | * struct stm32f4_i2c_msg - client specific data |
98 | * @addr: 8-bit slave addr, including r/w bit |
99 | * @count: number of bytes to be transferred |
100 | * @buf: data buffer |
101 | * @result: result of the transfer |
102 | * @stop: last I2C msg to be sent, i.e. STOP to be generated |
103 | */ |
104 | struct stm32f4_i2c_msg { |
105 | u8 addr; |
106 | u32 count; |
107 | u8 *buf; |
108 | int result; |
109 | bool stop; |
110 | }; |
111 | |
112 | /** |
113 | * struct stm32f4_i2c_dev - private data of the controller |
114 | * @adap: I2C adapter for this controller |
115 | * @dev: device for this controller |
116 | * @base: virtual memory area |
117 | * @complete: completion of I2C message |
118 | * @clk: hw i2c clock |
119 | * @speed: I2C clock frequency of the controller. Standard or Fast are supported |
120 | * @parent_rate: I2C clock parent rate in MHz |
121 | * @msg: I2C transfer information |
122 | */ |
123 | struct stm32f4_i2c_dev { |
124 | struct i2c_adapter adap; |
125 | struct device *dev; |
126 | void __iomem *base; |
127 | struct completion complete; |
128 | struct clk *clk; |
129 | int speed; |
130 | int parent_rate; |
131 | struct stm32f4_i2c_msg msg; |
132 | }; |
133 | |
134 | static inline void stm32f4_i2c_set_bits(void __iomem *reg, u32 mask) |
135 | { |
136 | writel_relaxed(readl_relaxed(reg) | mask, reg); |
137 | } |
138 | |
139 | static inline void stm32f4_i2c_clr_bits(void __iomem *reg, u32 mask) |
140 | { |
141 | writel_relaxed(readl_relaxed(reg) & ~mask, reg); |
142 | } |
143 | |
144 | static void stm32f4_i2c_disable_irq(struct stm32f4_i2c_dev *i2c_dev) |
145 | { |
146 | void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; |
147 | |
148 | stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_IRQ_MASK); |
149 | } |
150 | |
151 | static int stm32f4_i2c_set_periph_clk_freq(struct stm32f4_i2c_dev *i2c_dev) |
152 | { |
153 | u32 freq; |
154 | u32 cr2 = 0; |
155 | |
156 | i2c_dev->parent_rate = clk_get_rate(clk: i2c_dev->clk); |
157 | freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ); |
158 | |
159 | if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) { |
160 | /* |
161 | * To reach 100 kHz, the parent clk frequency should be between |
162 | * a minimum value of 2 MHz and a maximum value of 46 MHz due |
163 | * to hardware limitation |
164 | */ |
165 | if (freq < STM32F4_I2C_MIN_STANDARD_FREQ || |
166 | freq > STM32F4_I2C_MAX_FREQ) { |
167 | dev_err(i2c_dev->dev, |
168 | "bad parent clk freq for standard mode\n" ); |
169 | return -EINVAL; |
170 | } |
171 | } else { |
172 | /* |
173 | * To be as close as possible to 400 kHz, the parent clk |
174 | * frequency should be between a minimum value of 6 MHz and a |
175 | * maximum value of 46 MHz due to hardware limitation |
176 | */ |
177 | if (freq < STM32F4_I2C_MIN_FAST_FREQ || |
178 | freq > STM32F4_I2C_MAX_FREQ) { |
179 | dev_err(i2c_dev->dev, |
180 | "bad parent clk freq for fast mode\n" ); |
181 | return -EINVAL; |
182 | } |
183 | } |
184 | |
185 | cr2 |= STM32F4_I2C_CR2_FREQ(freq); |
186 | writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2); |
187 | |
188 | return 0; |
189 | } |
190 | |
191 | static void stm32f4_i2c_set_rise_time(struct stm32f4_i2c_dev *i2c_dev) |
192 | { |
193 | u32 freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ); |
194 | u32 trise; |
195 | |
196 | /* |
197 | * These bits must be programmed with the maximum SCL rise time given in |
198 | * the I2C bus specification, incremented by 1. |
199 | * |
200 | * In standard mode, the maximum allowed SCL rise time is 1000 ns. |
201 | * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to |
202 | * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be |
203 | * programmed with 0x9. (1000 ns / 125 ns + 1) |
204 | * So, for I2C standard mode TRISE = FREQ[5:0] + 1 |
205 | * |
206 | * In fast mode, the maximum allowed SCL rise time is 300 ns. |
207 | * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to |
208 | * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be |
209 | * programmed with 0x3. (300 ns / 125 ns + 1) |
210 | * So, for I2C fast mode TRISE = FREQ[5:0] * 300 / 1000 + 1 |
211 | * |
212 | * Function stm32f4_i2c_set_periph_clk_freq made sure that parent rate |
213 | * is not higher than 46 MHz . As a result trise is at most 4 bits wide |
214 | * and so fits into the TRISE bits [5:0]. |
215 | */ |
216 | if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) |
217 | trise = freq + 1; |
218 | else |
219 | trise = freq * 3 / 10 + 1; |
220 | |
221 | writel_relaxed(STM32F4_I2C_TRISE_VALUE(trise), |
222 | i2c_dev->base + STM32F4_I2C_TRISE); |
223 | } |
224 | |
225 | static void stm32f4_i2c_set_speed_mode(struct stm32f4_i2c_dev *i2c_dev) |
226 | { |
227 | u32 val; |
228 | u32 ccr = 0; |
229 | |
230 | if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) { |
231 | /* |
232 | * In standard mode: |
233 | * t_scl_high = t_scl_low = CCR * I2C parent clk period |
234 | * So to reach 100 kHz, we have: |
235 | * CCR = I2C parent rate / (100 kHz * 2) |
236 | * |
237 | * For example with parent rate = 2 MHz: |
238 | * CCR = 2000000 / (100000 * 2) = 10 |
239 | * t_scl_high = t_scl_low = 10 * (1 / 2000000) = 5000 ns |
240 | * t_scl_high + t_scl_low = 10000 ns so 100 kHz is reached |
241 | * |
242 | * Function stm32f4_i2c_set_periph_clk_freq made sure that |
243 | * parent rate is not higher than 46 MHz . As a result val |
244 | * is at most 8 bits wide and so fits into the CCR bits [11:0]. |
245 | */ |
246 | val = i2c_dev->parent_rate / (I2C_MAX_STANDARD_MODE_FREQ * 2); |
247 | } else { |
248 | /* |
249 | * In fast mode, we compute CCR with duty = 0 as with low |
250 | * frequencies we are not able to reach 400 kHz. |
251 | * In that case: |
252 | * t_scl_high = CCR * I2C parent clk period |
253 | * t_scl_low = 2 * CCR * I2C parent clk period |
254 | * So, CCR = I2C parent rate / (400 kHz * 3) |
255 | * |
256 | * For example with parent rate = 6 MHz: |
257 | * CCR = 6000000 / (400000 * 3) = 5 |
258 | * t_scl_high = 5 * (1 / 6000000) = 833 ns > 600 ns |
259 | * t_scl_low = 2 * 5 * (1 / 6000000) = 1667 ns > 1300 ns |
260 | * t_scl_high + t_scl_low = 2500 ns so 400 kHz is reached |
261 | * |
262 | * Function stm32f4_i2c_set_periph_clk_freq made sure that |
263 | * parent rate is not higher than 46 MHz . As a result val |
264 | * is at most 6 bits wide and so fits into the CCR bits [11:0]. |
265 | */ |
266 | val = DIV_ROUND_UP(i2c_dev->parent_rate, I2C_MAX_FAST_MODE_FREQ * 3); |
267 | |
268 | /* Select Fast mode */ |
269 | ccr |= STM32F4_I2C_CCR_FS; |
270 | } |
271 | |
272 | ccr |= STM32F4_I2C_CCR_CCR(val); |
273 | writel_relaxed(ccr, i2c_dev->base + STM32F4_I2C_CCR); |
274 | } |
275 | |
276 | /** |
277 | * stm32f4_i2c_hw_config() - Prepare I2C block |
278 | * @i2c_dev: Controller's private data |
279 | */ |
280 | static int stm32f4_i2c_hw_config(struct stm32f4_i2c_dev *i2c_dev) |
281 | { |
282 | int ret; |
283 | |
284 | ret = stm32f4_i2c_set_periph_clk_freq(i2c_dev); |
285 | if (ret) |
286 | return ret; |
287 | |
288 | stm32f4_i2c_set_rise_time(i2c_dev); |
289 | |
290 | stm32f4_i2c_set_speed_mode(i2c_dev); |
291 | |
292 | /* Enable I2C */ |
293 | writel_relaxed(STM32F4_I2C_CR1_PE, i2c_dev->base + STM32F4_I2C_CR1); |
294 | |
295 | return 0; |
296 | } |
297 | |
298 | static int stm32f4_i2c_wait_free_bus(struct stm32f4_i2c_dev *i2c_dev) |
299 | { |
300 | u32 status; |
301 | int ret; |
302 | |
303 | ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F4_I2C_SR2, |
304 | status, |
305 | !(status & STM32F4_I2C_SR2_BUSY), |
306 | 10, 1000); |
307 | if (ret) { |
308 | dev_dbg(i2c_dev->dev, "bus not free\n" ); |
309 | ret = -EBUSY; |
310 | } |
311 | |
312 | return ret; |
313 | } |
314 | |
315 | /** |
316 | * stm32f4_i2c_write_byte() - Write a byte in the data register |
317 | * @i2c_dev: Controller's private data |
318 | * @byte: Data to write in the register |
319 | */ |
320 | static void stm32f4_i2c_write_byte(struct stm32f4_i2c_dev *i2c_dev, u8 byte) |
321 | { |
322 | writel_relaxed(byte, i2c_dev->base + STM32F4_I2C_DR); |
323 | } |
324 | |
325 | /** |
326 | * stm32f4_i2c_write_msg() - Fill the data register in write mode |
327 | * @i2c_dev: Controller's private data |
328 | * |
329 | * This function fills the data register with I2C transfer buffer |
330 | */ |
331 | static void stm32f4_i2c_write_msg(struct stm32f4_i2c_dev *i2c_dev) |
332 | { |
333 | struct stm32f4_i2c_msg *msg = &i2c_dev->msg; |
334 | |
335 | stm32f4_i2c_write_byte(i2c_dev, byte: *msg->buf++); |
336 | msg->count--; |
337 | } |
338 | |
339 | static void stm32f4_i2c_read_msg(struct stm32f4_i2c_dev *i2c_dev) |
340 | { |
341 | struct stm32f4_i2c_msg *msg = &i2c_dev->msg; |
342 | u32 rbuf; |
343 | |
344 | rbuf = readl_relaxed(i2c_dev->base + STM32F4_I2C_DR); |
345 | *msg->buf++ = rbuf; |
346 | msg->count--; |
347 | } |
348 | |
349 | static void stm32f4_i2c_terminate_xfer(struct stm32f4_i2c_dev *i2c_dev) |
350 | { |
351 | struct stm32f4_i2c_msg *msg = &i2c_dev->msg; |
352 | void __iomem *reg; |
353 | |
354 | stm32f4_i2c_disable_irq(i2c_dev); |
355 | |
356 | reg = i2c_dev->base + STM32F4_I2C_CR1; |
357 | if (msg->stop) |
358 | stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); |
359 | else |
360 | stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); |
361 | |
362 | complete(&i2c_dev->complete); |
363 | } |
364 | |
365 | /** |
366 | * stm32f4_i2c_handle_write() - Handle FIFO empty interrupt in case of write |
367 | * @i2c_dev: Controller's private data |
368 | */ |
369 | static void stm32f4_i2c_handle_write(struct stm32f4_i2c_dev *i2c_dev) |
370 | { |
371 | struct stm32f4_i2c_msg *msg = &i2c_dev->msg; |
372 | void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; |
373 | |
374 | if (msg->count) { |
375 | stm32f4_i2c_write_msg(i2c_dev); |
376 | if (!msg->count) { |
377 | /* |
378 | * Disable buffer interrupts for RX not empty and TX |
379 | * empty events |
380 | */ |
381 | stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN); |
382 | } |
383 | } else { |
384 | stm32f4_i2c_terminate_xfer(i2c_dev); |
385 | } |
386 | } |
387 | |
388 | /** |
389 | * stm32f4_i2c_handle_read() - Handle FIFO empty interrupt in case of read |
390 | * @i2c_dev: Controller's private data |
391 | * |
392 | * This function is called when a new data is received in data register |
393 | */ |
394 | static void stm32f4_i2c_handle_read(struct stm32f4_i2c_dev *i2c_dev) |
395 | { |
396 | struct stm32f4_i2c_msg *msg = &i2c_dev->msg; |
397 | void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; |
398 | |
399 | switch (msg->count) { |
400 | case 1: |
401 | stm32f4_i2c_disable_irq(i2c_dev); |
402 | stm32f4_i2c_read_msg(i2c_dev); |
403 | complete(&i2c_dev->complete); |
404 | break; |
405 | /* |
406 | * For 2-byte reception, 3-byte reception and for Data N-2, N-1 and N |
407 | * for N-byte reception with N > 3, we do not have to read the data |
408 | * register when RX not empty event occurs as we have to wait for byte |
409 | * transferred finished event before reading data. |
410 | * So, here we just disable buffer interrupt in order to avoid another |
411 | * system preemption due to RX not empty event. |
412 | */ |
413 | case 2: |
414 | case 3: |
415 | stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN); |
416 | break; |
417 | /* |
418 | * For N byte reception with N > 3 we directly read data register |
419 | * until N-2 data. |
420 | */ |
421 | default: |
422 | stm32f4_i2c_read_msg(i2c_dev); |
423 | } |
424 | } |
425 | |
426 | /** |
427 | * stm32f4_i2c_handle_rx_done() - Handle byte transfer finished interrupt |
428 | * in case of read |
429 | * @i2c_dev: Controller's private data |
430 | * |
431 | * This function is called when a new data is received in the shift register |
432 | * but data register has not been read yet. |
433 | */ |
434 | static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev) |
435 | { |
436 | struct stm32f4_i2c_msg *msg = &i2c_dev->msg; |
437 | void __iomem *reg; |
438 | u32 mask; |
439 | int i; |
440 | |
441 | switch (msg->count) { |
442 | case 2: |
443 | /* |
444 | * In order to correctly send the Stop or Repeated Start |
445 | * condition on the I2C bus, the STOP/START bit has to be set |
446 | * before reading the last two bytes (data N-1 and N). |
447 | * After that, we could read the last two bytes, disable |
448 | * remaining interrupts and notify the end of xfer to the |
449 | * client |
450 | */ |
451 | reg = i2c_dev->base + STM32F4_I2C_CR1; |
452 | if (msg->stop) |
453 | stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); |
454 | else |
455 | stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); |
456 | |
457 | for (i = 2; i > 0; i--) |
458 | stm32f4_i2c_read_msg(i2c_dev); |
459 | |
460 | reg = i2c_dev->base + STM32F4_I2C_CR2; |
461 | mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN; |
462 | stm32f4_i2c_clr_bits(reg, mask); |
463 | |
464 | complete(&i2c_dev->complete); |
465 | break; |
466 | case 3: |
467 | /* |
468 | * In order to correctly generate the NACK pulse after the last |
469 | * received data byte, we have to enable NACK before reading N-2 |
470 | * data |
471 | */ |
472 | reg = i2c_dev->base + STM32F4_I2C_CR1; |
473 | stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR1_ACK); |
474 | stm32f4_i2c_read_msg(i2c_dev); |
475 | break; |
476 | default: |
477 | stm32f4_i2c_read_msg(i2c_dev); |
478 | } |
479 | } |
480 | |
481 | /** |
482 | * stm32f4_i2c_handle_rx_addr() - Handle address matched interrupt in case of |
483 | * master receiver |
484 | * @i2c_dev: Controller's private data |
485 | */ |
486 | static void stm32f4_i2c_handle_rx_addr(struct stm32f4_i2c_dev *i2c_dev) |
487 | { |
488 | struct stm32f4_i2c_msg *msg = &i2c_dev->msg; |
489 | u32 cr1; |
490 | |
491 | switch (msg->count) { |
492 | case 0: |
493 | stm32f4_i2c_terminate_xfer(i2c_dev); |
494 | |
495 | /* Clear ADDR flag */ |
496 | readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); |
497 | break; |
498 | case 1: |
499 | /* |
500 | * Single byte reception: |
501 | * Enable NACK and reset POS (Acknowledge position). |
502 | * Then, clear ADDR flag and set STOP or RepSTART. |
503 | * In that way, the NACK and STOP or RepStart pulses will be |
504 | * sent as soon as the byte will be received in shift register |
505 | */ |
506 | cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); |
507 | cr1 &= ~(STM32F4_I2C_CR1_ACK | STM32F4_I2C_CR1_POS); |
508 | writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); |
509 | |
510 | readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); |
511 | |
512 | if (msg->stop) |
513 | cr1 |= STM32F4_I2C_CR1_STOP; |
514 | else |
515 | cr1 |= STM32F4_I2C_CR1_START; |
516 | writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); |
517 | break; |
518 | case 2: |
519 | /* |
520 | * 2-byte reception: |
521 | * Enable NACK, set POS (NACK position) and clear ADDR flag. |
522 | * In that way, NACK will be sent for the next byte which will |
523 | * be received in the shift register instead of the current |
524 | * one. |
525 | */ |
526 | cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); |
527 | cr1 &= ~STM32F4_I2C_CR1_ACK; |
528 | cr1 |= STM32F4_I2C_CR1_POS; |
529 | writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); |
530 | |
531 | readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); |
532 | break; |
533 | |
534 | default: |
535 | /* |
536 | * N-byte reception: |
537 | * Enable ACK, reset POS (ACK position) and clear ADDR flag. |
538 | * In that way, ACK will be sent as soon as the current byte |
539 | * will be received in the shift register |
540 | */ |
541 | cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); |
542 | cr1 |= STM32F4_I2C_CR1_ACK; |
543 | cr1 &= ~STM32F4_I2C_CR1_POS; |
544 | writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); |
545 | |
546 | readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); |
547 | break; |
548 | } |
549 | } |
550 | |
551 | /** |
552 | * stm32f4_i2c_isr_event() - Interrupt routine for I2C bus event |
553 | * @irq: interrupt number |
554 | * @data: Controller's private data |
555 | */ |
556 | static irqreturn_t stm32f4_i2c_isr_event(int irq, void *data) |
557 | { |
558 | struct stm32f4_i2c_dev *i2c_dev = data; |
559 | struct stm32f4_i2c_msg *msg = &i2c_dev->msg; |
560 | u32 possible_status = STM32F4_I2C_SR1_ITEVTEN_MASK; |
561 | u32 status, ien, event, cr2; |
562 | |
563 | cr2 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR2); |
564 | ien = cr2 & STM32F4_I2C_CR2_IRQ_MASK; |
565 | |
566 | /* Update possible_status if buffer interrupt is enabled */ |
567 | if (ien & STM32F4_I2C_CR2_ITBUFEN) |
568 | possible_status |= STM32F4_I2C_SR1_ITBUFEN_MASK; |
569 | |
570 | status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1); |
571 | event = status & possible_status; |
572 | if (!event) { |
573 | dev_dbg(i2c_dev->dev, |
574 | "spurious evt irq (status=0x%08x, ien=0x%08x)\n" , |
575 | status, ien); |
576 | return IRQ_NONE; |
577 | } |
578 | |
579 | /* Start condition generated */ |
580 | if (event & STM32F4_I2C_SR1_SB) |
581 | stm32f4_i2c_write_byte(i2c_dev, byte: msg->addr); |
582 | |
583 | /* I2C Address sent */ |
584 | if (event & STM32F4_I2C_SR1_ADDR) { |
585 | if (msg->addr & I2C_M_RD) |
586 | stm32f4_i2c_handle_rx_addr(i2c_dev); |
587 | else |
588 | readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2); |
589 | |
590 | /* |
591 | * Enable buffer interrupts for RX not empty and TX empty |
592 | * events |
593 | */ |
594 | cr2 |= STM32F4_I2C_CR2_ITBUFEN; |
595 | writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2); |
596 | } |
597 | |
598 | /* TX empty */ |
599 | if ((event & STM32F4_I2C_SR1_TXE) && !(msg->addr & I2C_M_RD)) |
600 | stm32f4_i2c_handle_write(i2c_dev); |
601 | |
602 | /* RX not empty */ |
603 | if ((event & STM32F4_I2C_SR1_RXNE) && (msg->addr & I2C_M_RD)) |
604 | stm32f4_i2c_handle_read(i2c_dev); |
605 | |
606 | /* |
607 | * The BTF (Byte Transfer finished) event occurs when: |
608 | * - in reception : a new byte is received in the shift register |
609 | * but the previous byte has not been read yet from data register |
610 | * - in transmission: a new byte should be sent but the data register |
611 | * has not been written yet |
612 | */ |
613 | if (event & STM32F4_I2C_SR1_BTF) { |
614 | if (msg->addr & I2C_M_RD) |
615 | stm32f4_i2c_handle_rx_done(i2c_dev); |
616 | else |
617 | stm32f4_i2c_handle_write(i2c_dev); |
618 | } |
619 | |
620 | return IRQ_HANDLED; |
621 | } |
622 | |
623 | /** |
624 | * stm32f4_i2c_isr_error() - Interrupt routine for I2C bus error |
625 | * @irq: interrupt number |
626 | * @data: Controller's private data |
627 | */ |
628 | static irqreturn_t stm32f4_i2c_isr_error(int irq, void *data) |
629 | { |
630 | struct stm32f4_i2c_dev *i2c_dev = data; |
631 | struct stm32f4_i2c_msg *msg = &i2c_dev->msg; |
632 | void __iomem *reg; |
633 | u32 status; |
634 | |
635 | status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1); |
636 | |
637 | /* Arbitration lost */ |
638 | if (status & STM32F4_I2C_SR1_ARLO) { |
639 | status &= ~STM32F4_I2C_SR1_ARLO; |
640 | writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); |
641 | msg->result = -EAGAIN; |
642 | } |
643 | |
644 | /* |
645 | * Acknowledge failure: |
646 | * In master transmitter mode a Stop must be generated by software |
647 | */ |
648 | if (status & STM32F4_I2C_SR1_AF) { |
649 | if (!(msg->addr & I2C_M_RD)) { |
650 | reg = i2c_dev->base + STM32F4_I2C_CR1; |
651 | stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); |
652 | } |
653 | status &= ~STM32F4_I2C_SR1_AF; |
654 | writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); |
655 | msg->result = -EIO; |
656 | } |
657 | |
658 | /* Bus error */ |
659 | if (status & STM32F4_I2C_SR1_BERR) { |
660 | status &= ~STM32F4_I2C_SR1_BERR; |
661 | writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1); |
662 | msg->result = -EIO; |
663 | } |
664 | |
665 | stm32f4_i2c_disable_irq(i2c_dev); |
666 | complete(&i2c_dev->complete); |
667 | |
668 | return IRQ_HANDLED; |
669 | } |
670 | |
671 | /** |
672 | * stm32f4_i2c_xfer_msg() - Transfer a single I2C message |
673 | * @i2c_dev: Controller's private data |
674 | * @msg: I2C message to transfer |
675 | * @is_first: first message of the sequence |
676 | * @is_last: last message of the sequence |
677 | */ |
678 | static int stm32f4_i2c_xfer_msg(struct stm32f4_i2c_dev *i2c_dev, |
679 | struct i2c_msg *msg, bool is_first, |
680 | bool is_last) |
681 | { |
682 | struct stm32f4_i2c_msg *f4_msg = &i2c_dev->msg; |
683 | void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR1; |
684 | unsigned long timeout; |
685 | u32 mask; |
686 | int ret; |
687 | |
688 | f4_msg->addr = i2c_8bit_addr_from_msg(msg); |
689 | f4_msg->buf = msg->buf; |
690 | f4_msg->count = msg->len; |
691 | f4_msg->result = 0; |
692 | f4_msg->stop = is_last; |
693 | |
694 | reinit_completion(x: &i2c_dev->complete); |
695 | |
696 | /* Enable events and errors interrupts */ |
697 | mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN; |
698 | stm32f4_i2c_set_bits(reg: i2c_dev->base + STM32F4_I2C_CR2, mask); |
699 | |
700 | if (is_first) { |
701 | ret = stm32f4_i2c_wait_free_bus(i2c_dev); |
702 | if (ret) |
703 | return ret; |
704 | |
705 | /* START generation */ |
706 | stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); |
707 | } |
708 | |
709 | timeout = wait_for_completion_timeout(x: &i2c_dev->complete, |
710 | timeout: i2c_dev->adap.timeout); |
711 | ret = f4_msg->result; |
712 | |
713 | if (!timeout) |
714 | ret = -ETIMEDOUT; |
715 | |
716 | return ret; |
717 | } |
718 | |
719 | /** |
720 | * stm32f4_i2c_xfer() - Transfer combined I2C message |
721 | * @i2c_adap: Adapter pointer to the controller |
722 | * @msgs: Pointer to data to be written. |
723 | * @num: Number of messages to be executed |
724 | */ |
725 | static int stm32f4_i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], |
726 | int num) |
727 | { |
728 | struct stm32f4_i2c_dev *i2c_dev = i2c_get_adapdata(adap: i2c_adap); |
729 | int ret, i; |
730 | |
731 | ret = clk_enable(clk: i2c_dev->clk); |
732 | if (ret) { |
733 | dev_err(i2c_dev->dev, "Failed to enable clock\n" ); |
734 | return ret; |
735 | } |
736 | |
737 | for (i = 0; i < num && !ret; i++) |
738 | ret = stm32f4_i2c_xfer_msg(i2c_dev, msg: &msgs[i], is_first: i == 0, |
739 | is_last: i == num - 1); |
740 | |
741 | clk_disable(clk: i2c_dev->clk); |
742 | |
743 | return (ret < 0) ? ret : num; |
744 | } |
745 | |
746 | static u32 stm32f4_i2c_func(struct i2c_adapter *adap) |
747 | { |
748 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
749 | } |
750 | |
751 | static const struct i2c_algorithm stm32f4_i2c_algo = { |
752 | .master_xfer = stm32f4_i2c_xfer, |
753 | .functionality = stm32f4_i2c_func, |
754 | }; |
755 | |
756 | static int stm32f4_i2c_probe(struct platform_device *pdev) |
757 | { |
758 | struct device_node *np = pdev->dev.of_node; |
759 | struct stm32f4_i2c_dev *i2c_dev; |
760 | struct resource *res; |
761 | u32 irq_event, irq_error, clk_rate; |
762 | struct i2c_adapter *adap; |
763 | struct reset_control *rst; |
764 | int ret; |
765 | |
766 | i2c_dev = devm_kzalloc(dev: &pdev->dev, size: sizeof(*i2c_dev), GFP_KERNEL); |
767 | if (!i2c_dev) |
768 | return -ENOMEM; |
769 | |
770 | i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, index: 0, res: &res); |
771 | if (IS_ERR(ptr: i2c_dev->base)) |
772 | return PTR_ERR(ptr: i2c_dev->base); |
773 | |
774 | irq_event = irq_of_parse_and_map(node: np, index: 0); |
775 | if (!irq_event) { |
776 | dev_err(&pdev->dev, "IRQ event missing or invalid\n" ); |
777 | return -EINVAL; |
778 | } |
779 | |
780 | irq_error = irq_of_parse_and_map(node: np, index: 1); |
781 | if (!irq_error) { |
782 | dev_err(&pdev->dev, "IRQ error missing or invalid\n" ); |
783 | return -EINVAL; |
784 | } |
785 | |
786 | i2c_dev->clk = devm_clk_get_enabled(dev: &pdev->dev, NULL); |
787 | if (IS_ERR(ptr: i2c_dev->clk)) { |
788 | dev_err(&pdev->dev, "Failed to enable clock\n" ); |
789 | return PTR_ERR(ptr: i2c_dev->clk); |
790 | } |
791 | |
792 | rst = devm_reset_control_get_exclusive(dev: &pdev->dev, NULL); |
793 | if (IS_ERR(ptr: rst)) |
794 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: rst), |
795 | fmt: "Error: Missing reset ctrl\n" ); |
796 | |
797 | reset_control_assert(rstc: rst); |
798 | udelay(2); |
799 | reset_control_deassert(rstc: rst); |
800 | |
801 | i2c_dev->speed = STM32_I2C_SPEED_STANDARD; |
802 | ret = of_property_read_u32(np, propname: "clock-frequency" , out_value: &clk_rate); |
803 | if (!ret && clk_rate >= I2C_MAX_FAST_MODE_FREQ) |
804 | i2c_dev->speed = STM32_I2C_SPEED_FAST; |
805 | |
806 | i2c_dev->dev = &pdev->dev; |
807 | |
808 | ret = devm_request_irq(dev: &pdev->dev, irq: irq_event, handler: stm32f4_i2c_isr_event, irqflags: 0, |
809 | devname: pdev->name, dev_id: i2c_dev); |
810 | if (ret) { |
811 | dev_err(&pdev->dev, "Failed to request irq event %i\n" , |
812 | irq_event); |
813 | return ret; |
814 | } |
815 | |
816 | ret = devm_request_irq(dev: &pdev->dev, irq: irq_error, handler: stm32f4_i2c_isr_error, irqflags: 0, |
817 | devname: pdev->name, dev_id: i2c_dev); |
818 | if (ret) { |
819 | dev_err(&pdev->dev, "Failed to request irq error %i\n" , |
820 | irq_error); |
821 | return ret; |
822 | } |
823 | |
824 | ret = stm32f4_i2c_hw_config(i2c_dev); |
825 | if (ret) |
826 | return ret; |
827 | |
828 | adap = &i2c_dev->adap; |
829 | i2c_set_adapdata(adap, data: i2c_dev); |
830 | snprintf(buf: adap->name, size: sizeof(adap->name), fmt: "STM32 I2C(%pa)" , &res->start); |
831 | adap->owner = THIS_MODULE; |
832 | adap->timeout = 2 * HZ; |
833 | adap->retries = 0; |
834 | adap->algo = &stm32f4_i2c_algo; |
835 | adap->dev.parent = &pdev->dev; |
836 | adap->dev.of_node = pdev->dev.of_node; |
837 | |
838 | init_completion(x: &i2c_dev->complete); |
839 | |
840 | ret = i2c_add_adapter(adap); |
841 | if (ret) |
842 | return ret; |
843 | |
844 | platform_set_drvdata(pdev, data: i2c_dev); |
845 | |
846 | clk_disable(clk: i2c_dev->clk); |
847 | |
848 | dev_info(i2c_dev->dev, "STM32F4 I2C driver registered\n" ); |
849 | |
850 | return 0; |
851 | } |
852 | |
853 | static void stm32f4_i2c_remove(struct platform_device *pdev) |
854 | { |
855 | struct stm32f4_i2c_dev *i2c_dev = platform_get_drvdata(pdev); |
856 | |
857 | i2c_del_adapter(adap: &i2c_dev->adap); |
858 | } |
859 | |
860 | static const struct of_device_id stm32f4_i2c_match[] = { |
861 | { .compatible = "st,stm32f4-i2c" , }, |
862 | {}, |
863 | }; |
864 | MODULE_DEVICE_TABLE(of, stm32f4_i2c_match); |
865 | |
866 | static struct platform_driver stm32f4_i2c_driver = { |
867 | .driver = { |
868 | .name = "stm32f4-i2c" , |
869 | .of_match_table = stm32f4_i2c_match, |
870 | }, |
871 | .probe = stm32f4_i2c_probe, |
872 | .remove_new = stm32f4_i2c_remove, |
873 | }; |
874 | |
875 | module_platform_driver(stm32f4_i2c_driver); |
876 | |
877 | MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>" ); |
878 | MODULE_DESCRIPTION("STMicroelectronics STM32F4 I2C driver" ); |
879 | MODULE_LICENSE("GPL v2" ); |
880 | |