1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* Driver for STMicroelectronics STM32F7 I2C controller
4	*
5	* This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
6	* reference manual.
7	* Please see below a link to the documentation:
8	* http://www.st.com/resource/en/reference_manual/dm00124865.pdf
9	*
10	* Copyright (C) M'boumba Cedric Madianga 2017
11	* Copyright (C) STMicroelectronics 2017
12	* Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
13	*
14	* This driver is based on i2c-stm32f4.c
15	*
16	*/
17	#include <linux/clk.h>
18	#include <linux/delay.h>
19	#include <linux/err.h>
20	#include <linux/i2c.h>
21	#include <linux/i2c-smbus.h>
22	#include <linux/interrupt.h>
23	#include <linux/io.h>
24	#include <linux/iopoll.h>
25	#include <linux/mfd/syscon.h>
26	#include <linux/module.h>
27	#include <linux/of.h>
28	#include <linux/of_address.h>
29	#include <linux/of_platform.h>
30	#include <linux/platform_device.h>
31	#include <linux/pinctrl/consumer.h>
32	#include <linux/pm_runtime.h>
33	#include <linux/pm_wakeirq.h>
34	#include <linux/regmap.h>
35	#include <linux/reset.h>
36	#include <linux/slab.h>
37
38	#include "i2c-stm32.h"
39
40	/* STM32F7 I2C registers */
41	#define STM32F7_I2C_CR1 0x00
42	#define STM32F7_I2C_CR2 0x04
43	#define STM32F7_I2C_OAR1 0x08
44	#define STM32F7_I2C_OAR2 0x0C
45	#define STM32F7_I2C_PECR 0x20
46	#define STM32F7_I2C_TIMINGR 0x10
47	#define STM32F7_I2C_ISR 0x18
48	#define STM32F7_I2C_ICR 0x1C
49	#define STM32F7_I2C_RXDR 0x24
50	#define STM32F7_I2C_TXDR 0x28
51
52	/* STM32F7 I2C control 1 */
53	#define STM32F7_I2C_CR1_PECEN BIT(23)
54	#define STM32F7_I2C_CR1_ALERTEN BIT(22)
55	#define STM32F7_I2C_CR1_SMBHEN BIT(20)
56	#define STM32F7_I2C_CR1_WUPEN BIT(18)
57	#define STM32F7_I2C_CR1_SBC BIT(16)
58	#define STM32F7_I2C_CR1_RXDMAEN BIT(15)
59	#define STM32F7_I2C_CR1_TXDMAEN BIT(14)
60	#define STM32F7_I2C_CR1_ANFOFF BIT(12)
61	#define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8)
62	#define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
63	#define STM32F7_I2C_CR1_ERRIE BIT(7)
64	#define STM32F7_I2C_CR1_TCIE BIT(6)
65	#define STM32F7_I2C_CR1_STOPIE BIT(5)
66	#define STM32F7_I2C_CR1_NACKIE BIT(4)
67	#define STM32F7_I2C_CR1_ADDRIE BIT(3)
68	#define STM32F7_I2C_CR1_RXIE BIT(2)
69	#define STM32F7_I2C_CR1_TXIE BIT(1)
70	#define STM32F7_I2C_CR1_PE BIT(0)
71	#define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
72	| STM32F7_I2C_CR1_TCIE \
73	| STM32F7_I2C_CR1_STOPIE \
74	| STM32F7_I2C_CR1_NACKIE \
75	| STM32F7_I2C_CR1_RXIE \
76	| STM32F7_I2C_CR1_TXIE)
77	#define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
78	| STM32F7_I2C_CR1_STOPIE \
79	| STM32F7_I2C_CR1_NACKIE \
80	| STM32F7_I2C_CR1_RXIE \
81	| STM32F7_I2C_CR1_TXIE)
82
83	/* STM32F7 I2C control 2 */
84	#define STM32F7_I2C_CR2_PECBYTE BIT(26)
85	#define STM32F7_I2C_CR2_RELOAD BIT(24)
86	#define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
87	#define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
88	#define STM32F7_I2C_CR2_NACK BIT(15)
89	#define STM32F7_I2C_CR2_STOP BIT(14)
90	#define STM32F7_I2C_CR2_START BIT(13)
91	#define STM32F7_I2C_CR2_HEAD10R BIT(12)
92	#define STM32F7_I2C_CR2_ADD10 BIT(11)
93	#define STM32F7_I2C_CR2_RD_WRN BIT(10)
94	#define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
95	#define STM32F7_I2C_CR2_SADD10(n) (((n) & \
96	STM32F7_I2C_CR2_SADD10_MASK))
97	#define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
98	#define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
99
100	/* STM32F7 I2C Own Address 1 */
101	#define STM32F7_I2C_OAR1_OA1EN BIT(15)
102	#define STM32F7_I2C_OAR1_OA1MODE BIT(10)
103	#define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
104	#define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
105	STM32F7_I2C_OAR1_OA1_10_MASK))
106	#define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
107	#define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
108	#define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
109	| STM32F7_I2C_OAR1_OA1_10_MASK \
110	| STM32F7_I2C_OAR1_OA1EN \
111	| STM32F7_I2C_OAR1_OA1MODE)
112
113	/* STM32F7 I2C Own Address 2 */
114	#define STM32F7_I2C_OAR2_OA2EN BIT(15)
115	#define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
116	#define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
117	#define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
118	#define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
119	#define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
120	| STM32F7_I2C_OAR2_OA2_7_MASK \
121	| STM32F7_I2C_OAR2_OA2EN)
122
123	/* STM32F7 I2C Interrupt Status */
124	#define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
125	#define STM32F7_I2C_ISR_ADDCODE_GET(n) \
126	(((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
127	#define STM32F7_I2C_ISR_DIR BIT(16)
128	#define STM32F7_I2C_ISR_BUSY BIT(15)
129	#define STM32F7_I2C_ISR_ALERT BIT(13)
130	#define STM32F7_I2C_ISR_PECERR BIT(11)
131	#define STM32F7_I2C_ISR_ARLO BIT(9)
132	#define STM32F7_I2C_ISR_BERR BIT(8)
133	#define STM32F7_I2C_ISR_TCR BIT(7)
134	#define STM32F7_I2C_ISR_TC BIT(6)
135	#define STM32F7_I2C_ISR_STOPF BIT(5)
136	#define STM32F7_I2C_ISR_NACKF BIT(4)
137	#define STM32F7_I2C_ISR_ADDR BIT(3)
138	#define STM32F7_I2C_ISR_RXNE BIT(2)
139	#define STM32F7_I2C_ISR_TXIS BIT(1)
140	#define STM32F7_I2C_ISR_TXE BIT(0)
141
142	/* STM32F7 I2C Interrupt Clear */
143	#define STM32F7_I2C_ICR_ALERTCF BIT(13)
144	#define STM32F7_I2C_ICR_PECCF BIT(11)
145	#define STM32F7_I2C_ICR_ARLOCF BIT(9)
146	#define STM32F7_I2C_ICR_BERRCF BIT(8)
147	#define STM32F7_I2C_ICR_STOPCF BIT(5)
148	#define STM32F7_I2C_ICR_NACKCF BIT(4)
149	#define STM32F7_I2C_ICR_ADDRCF BIT(3)
150
151	/* STM32F7 I2C Timing */
152	#define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
153	#define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
154	#define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
155	#define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
156	#define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
157
158	#define STM32F7_I2C_MAX_LEN 0xff
159	#define STM32F7_I2C_DMA_LEN_MIN 0x16
160	enum {
161	STM32F7_SLAVE_HOSTNOTIFY,
162	STM32F7_SLAVE_7_10_BITS_ADDR,
163	STM32F7_SLAVE_7_BITS_ADDR,
164	STM32F7_I2C_MAX_SLAVE
165	};
166
167	#define STM32F7_I2C_DNF_DEFAULT 0
168	#define STM32F7_I2C_DNF_MAX 15
169
170	#define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
171	#define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
172
173	#define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
174	#define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
175
176	#define STM32F7_PRESC_MAX BIT(4)
177	#define STM32F7_SCLDEL_MAX BIT(4)
178	#define STM32F7_SDADEL_MAX BIT(4)
179	#define STM32F7_SCLH_MAX BIT(8)
180	#define STM32F7_SCLL_MAX BIT(8)
181
182	#define STM32F7_AUTOSUSPEND_DELAY (HZ / 100)
183
184	/**
185	* struct stm32f7_i2c_regs - i2c f7 registers backup
186	* @cr1: Control register 1
187	* @cr2: Control register 2
188	* @oar1: Own address 1 register
189	* @oar2: Own address 2 register
190	* @tmgr: Timing register
191	*/
192	struct stm32f7_i2c_regs {
193	u32 cr1;
194	u32 cr2;
195	u32 oar1;
196	u32 oar2;
197	u32 tmgr;
198	};
199
200	/**
201	* struct stm32f7_i2c_spec - private i2c specification timing
202	* @rate: I2C bus speed (Hz)
203	* @fall_max: Max fall time of both SDA and SCL signals (ns)
204	* @rise_max: Max rise time of both SDA and SCL signals (ns)
205	* @hddat_min: Min data hold time (ns)
206	* @vddat_max: Max data valid time (ns)
207	* @sudat_min: Min data setup time (ns)
208	* @l_min: Min low period of the SCL clock (ns)
209	* @h_min: Min high period of the SCL clock (ns)
210	*/
211	struct stm32f7_i2c_spec {
212	u32 rate;
213	u32 fall_max;
214	u32 rise_max;
215	u32 hddat_min;
216	u32 vddat_max;
217	u32 sudat_min;
218	u32 l_min;
219	u32 h_min;
220	};
221
222	/**
223	* struct stm32f7_i2c_setup - private I2C timing setup parameters
224	* @speed_freq: I2C speed frequency (Hz)
225	* @clock_src: I2C clock source frequency (Hz)
226	* @rise_time: Rise time (ns)
227	* @fall_time: Fall time (ns)
228	* @fmp_clr_offset: Fast Mode Plus clear register offset from set register
229	*/
230	struct stm32f7_i2c_setup {
231	u32 speed_freq;
232	u32 clock_src;
233	u32 rise_time;
234	u32 fall_time;
235	u32 fmp_clr_offset;
236	};
237
238	/**
239	* struct stm32f7_i2c_timings - private I2C output parameters
240	* @node: List entry
241	* @presc: Prescaler value
242	* @scldel: Data setup time
243	* @sdadel: Data hold time
244	* @sclh: SCL high period (master mode)
245	* @scll: SCL low period (master mode)
246	*/
247	struct stm32f7_i2c_timings {
248	struct list_head node;
249	u8 presc;
250	u8 scldel;
251	u8 sdadel;
252	u8 sclh;
253	u8 scll;
254	};
255
256	/**
257	* struct stm32f7_i2c_msg - client specific data
258	* @addr: 8-bit or 10-bit slave addr, including r/w bit
259	* @count: number of bytes to be transferred
260	* @buf: data buffer
261	* @result: result of the transfer
262	* @stop: last I2C msg to be sent, i.e. STOP to be generated
263	* @smbus: boolean to know if the I2C IP is used in SMBus mode
264	* @size: type of SMBus protocol
265	* @read_write: direction of SMBus protocol
266	* SMBus block read and SMBus block write - block read process call protocols
267	* @smbus_buf: buffer to be used for SMBus protocol transfer. It will
268	* contain a maximum of 32 bytes of data + byte command + byte count + PEC
269	* This buffer has to be 32-bit aligned to be compliant with memory address
270	* register in DMA mode.
271	*/
272	struct stm32f7_i2c_msg {
273	u16 addr;
274	u32 count;
275	u8 *buf;
276	int result;
277	bool stop;
278	bool smbus;
279	int size;
280	char read_write;
281	u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
282	};
283
284	/**
285	* struct stm32f7_i2c_alert - SMBus alert specific data
286	* @setup: platform data for the smbus_alert i2c client
287	* @ara: I2C slave device used to respond to the SMBus Alert with Alert
288	* Response Address
289	*/
290	struct stm32f7_i2c_alert {
291	struct i2c_smbus_alert_setup setup;
292	struct i2c_client *ara;
293	};
294
295	/**
296	* struct stm32f7_i2c_dev - private data of the controller
297	* @adap: I2C adapter for this controller
298	* @dev: device for this controller
299	* @base: virtual memory area
300	* @complete: completion of I2C message
301	* @clk: hw i2c clock
302	* @bus_rate: I2C clock frequency of the controller
303	* @msg: Pointer to data to be written
304	* @msg_num: number of I2C messages to be executed
305	* @msg_id: message identifiant
306	* @f7_msg: customized i2c msg for driver usage
307	* @setup: I2C timing input setup
308	* @timing: I2C computed timings
309	* @slave: list of slave devices registered on the I2C bus
310	* @slave_running: slave device currently used
311	* @backup_regs: backup of i2c controller registers (for suspend/resume)
312	* @slave_dir: transfer direction for the current slave device
313	* @master_mode: boolean to know in which mode the I2C is running (master or
314	* slave)
315	* @dma: dma data
316	* @use_dma: boolean to know if dma is used in the current transfer
317	* @regmap: holds SYSCFG phandle for Fast Mode Plus bits
318	* @fmp_sreg: register address for setting Fast Mode Plus bits
319	* @fmp_creg: register address for clearing Fast Mode Plus bits
320	* @fmp_mask: mask for Fast Mode Plus bits in set register
321	* @wakeup_src: boolean to know if the device is a wakeup source
322	* @smbus_mode: states that the controller is configured in SMBus mode
323	* @host_notify_client: SMBus host-notify client
324	* @analog_filter: boolean to indicate enabling of the analog filter
325	* @dnf_dt: value of digital filter requested via dt
326	* @dnf: value of digital filter to apply
327	* @alert: SMBus alert specific data
328	* @atomic: boolean indicating that current transfer is atomic
329	*/
330	struct stm32f7_i2c_dev {
331	struct i2c_adapter adap;
332	struct device *dev;
333	void __iomem *base;
334	struct completion complete;
335	struct clk *clk;
336	unsigned int bus_rate;
337	struct i2c_msg *msg;
338	unsigned int msg_num;
339	unsigned int msg_id;
340	struct stm32f7_i2c_msg f7_msg;
341	struct stm32f7_i2c_setup setup;
342	struct stm32f7_i2c_timings timing;
343	struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
344	struct i2c_client *slave_running;
345	struct stm32f7_i2c_regs backup_regs;
346	u32 slave_dir;
347	bool master_mode;
348	struct stm32_i2c_dma *dma;
349	bool use_dma;
350	struct regmap *regmap;
351	u32 fmp_sreg;
352	u32 fmp_creg;
353	u32 fmp_mask;
354	bool wakeup_src;
355	bool smbus_mode;
356	struct i2c_client *host_notify_client;
357	bool analog_filter;
358	u32 dnf_dt;
359	u32 dnf;
360	struct stm32f7_i2c_alert *alert;
361	bool atomic;
362	};
363
364	/*
365	* All these values are coming from I2C Specification, Version 6.0, 4th of
366	* April 2014.
367	*
368	* Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
369	* and Fast-mode Plus I2C-bus devices
370	*/
371	static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
372	{
373	.rate = I2C_MAX_STANDARD_MODE_FREQ,
374	.fall_max = 300,
375	.rise_max = 1000,
376	.hddat_min = 0,
377	.vddat_max = 3450,
378	.sudat_min = 250,
379	.l_min = 4700,
380	.h_min = 4000,
381	},
382	{
383	.rate = I2C_MAX_FAST_MODE_FREQ,
384	.fall_max = 300,
385	.rise_max = 300,
386	.hddat_min = 0,
387	.vddat_max = 900,
388	.sudat_min = 100,
389	.l_min = 1300,
390	.h_min = 600,
391	},
392	{
393	.rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
394	.fall_max = 100,
395	.rise_max = 120,
396	.hddat_min = 0,
397	.vddat_max = 450,
398	.sudat_min = 50,
399	.l_min = 500,
400	.h_min = 260,
401	},
402	};
403
404	static const struct stm32f7_i2c_setup stm32f7_setup = {
405	.rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
406	.fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
407	};
408
409	static const struct stm32f7_i2c_setup stm32mp15_setup = {
410	.rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
411	.fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
412	.fmp_clr_offset = 0x40,
413	};
414
415	static const struct stm32f7_i2c_setup stm32mp13_setup = {
416	.rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
417	.fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
418	.fmp_clr_offset = 0x4,
419	};
420
421	static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
422	{
423	writel_relaxed(readl_relaxed(reg) | mask, reg);
424	}
425
426	static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
427	{
428	writel_relaxed(readl_relaxed(reg) & ~mask, reg);
429	}
430
431	static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
432	{
433	stm32f7_i2c_clr_bits(reg: i2c_dev->base + STM32F7_I2C_CR1, mask);
434	}
435
436	static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate)
437	{
438	int i;
439
440	for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++)
441	if (rate <= stm32f7_i2c_specs[i].rate)
442	return &stm32f7_i2c_specs[i];
443
444	return ERR_PTR(error: -EINVAL);
445	}
446
447	#define RATE_MIN(rate) ((rate) * 8 / 10)
448	static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
449	struct stm32f7_i2c_setup *setup,
450	struct stm32f7_i2c_timings *output)
451	{
452	struct stm32f7_i2c_spec *specs;
453	u32 p_prev = STM32F7_PRESC_MAX;
454	u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
455	setup->clock_src);
456	u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
457	setup->speed_freq);
458	u32 clk_error_prev = i2cbus;
459	u32 tsync;
460	u32 af_delay_min, af_delay_max;
461	u32 dnf_delay;
462	u32 clk_min, clk_max;
463	int sdadel_min, sdadel_max;
464	int scldel_min;
465	struct stm32f7_i2c_timings *v, *_v, *s;
466	struct list_head solutions;
467	u16 p, l, a, h;
468	int ret = 0;
469
470	specs = stm32f7_get_specs(rate: setup->speed_freq);
471	if (specs == ERR_PTR(error: -EINVAL)) {
472	dev_err(i2c_dev->dev, "speed out of bound {%d}\n",
473	setup->speed_freq);
474	return -EINVAL;
475	}
476
477	if ((setup->rise_time > specs->rise_max) ||
478	(setup->fall_time > specs->fall_max)) {
479	dev_err(i2c_dev->dev,
480	"timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
481	setup->rise_time, specs->rise_max,
482	setup->fall_time, specs->fall_max);
483	return -EINVAL;
484	}
485
486	i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk);
487	if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) {
488	dev_err(i2c_dev->dev,
489	"DNF out of bound %d/%d\n",
490	i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk);
491	return -EINVAL;
492	}
493
494	/* Analog and Digital Filters */
495	af_delay_min =
496	(i2c_dev->analog_filter ?
497	STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
498	af_delay_max =
499	(i2c_dev->analog_filter ?
500	STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
501	dnf_delay = i2c_dev->dnf * i2cclk;
502
503	sdadel_min = specs->hddat_min + setup->fall_time -
504	af_delay_min - (i2c_dev->dnf + 3) * i2cclk;
505
506	sdadel_max = specs->vddat_max - setup->rise_time -
507	af_delay_max - (i2c_dev->dnf + 4) * i2cclk;
508
509	scldel_min = setup->rise_time + specs->sudat_min;
510
511	if (sdadel_min < 0)
512	sdadel_min = 0;
513	if (sdadel_max < 0)
514	sdadel_max = 0;
515
516	dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
517	sdadel_min, sdadel_max, scldel_min);
518
519	INIT_LIST_HEAD(list: &solutions);
520	/* Compute possible values for PRESC, SCLDEL and SDADEL */
521	for (p = 0; p < STM32F7_PRESC_MAX; p++) {
522	for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
523	u32 scldel = (l + 1) * (p + 1) * i2cclk;
524
525	if (scldel < scldel_min)
526	continue;
527
528	for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
529	u32 sdadel = (a * (p + 1) + 1) * i2cclk;
530
531	if (((sdadel >= sdadel_min) &&
532	(sdadel <= sdadel_max)) &&
533	(p != p_prev)) {
534	v = kmalloc(size: sizeof(*v), GFP_KERNEL);
535	if (!v) {
536	ret = -ENOMEM;
537	goto exit;
538	}
539
540	v->presc = p;
541	v->scldel = l;
542	v->sdadel = a;
543	p_prev = p;
544
545	list_add_tail(new: &v->node,
546	head: &solutions);
547	break;
548	}
549	}
550
551	if (p_prev == p)
552	break;
553	}
554	}
555
556	if (list_empty(head: &solutions)) {
557	dev_err(i2c_dev->dev, "no Prescaler solution\n");
558	ret = -EPERM;
559	goto exit;
560	}
561
562	tsync = af_delay_min + dnf_delay + (2 * i2cclk);
563	s = NULL;
564	clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq);
565	clk_min = NSEC_PER_SEC / setup->speed_freq;
566
567	/*
568	* Among Prescaler possibilities discovered above figures out SCL Low
569	* and High Period. Provided:
570	* - SCL Low Period has to be higher than SCL Clock Low Period
571	* defined by I2C Specification. I2C Clock has to be lower than
572	* (SCL Low Period - Analog/Digital filters) / 4.
573	* - SCL High Period has to be lower than SCL Clock High Period
574	* defined by I2C Specification
575	* - I2C Clock has to be lower than SCL High Period
576	*/
577	list_for_each_entry(v, &solutions, node) {
578	u32 prescaler = (v->presc + 1) * i2cclk;
579
580	for (l = 0; l < STM32F7_SCLL_MAX; l++) {
581	u32 tscl_l = (l + 1) * prescaler + tsync;
582
583	if ((tscl_l < specs->l_min) ||
584	(i2cclk >=
585	((tscl_l - af_delay_min - dnf_delay) / 4))) {
586	continue;
587	}
588
589	for (h = 0; h < STM32F7_SCLH_MAX; h++) {
590	u32 tscl_h = (h + 1) * prescaler + tsync;
591	u32 tscl = tscl_l + tscl_h +
592	setup->rise_time + setup->fall_time;
593
594	if ((tscl >= clk_min) && (tscl <= clk_max) &&
595	(tscl_h >= specs->h_min) &&
596	(i2cclk < tscl_h)) {
597	int clk_error = tscl - i2cbus;
598
599	if (clk_error < 0)
600	clk_error = -clk_error;
601
602	if (clk_error < clk_error_prev) {
603	clk_error_prev = clk_error;
604	v->scll = l;
605	v->sclh = h;
606	s = v;
607	}
608	}
609	}
610	}
611	}
612
613	if (!s) {
614	dev_err(i2c_dev->dev, "no solution at all\n");
615	ret = -EPERM;
616	goto exit;
617	}
618
619	output->presc = s->presc;
620	output->scldel = s->scldel;
621	output->sdadel = s->sdadel;
622	output->scll = s->scll;
623	output->sclh = s->sclh;
624
625	dev_dbg(i2c_dev->dev,
626	"Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
627	output->presc,
628	output->scldel, output->sdadel,
629	output->scll, output->sclh);
630
631	exit:
632	/* Release list and memory */
633	list_for_each_entry_safe(v, _v, &solutions, node) {
634	list_del(entry: &v->node);
635	kfree(objp: v);
636	}
637
638	return ret;
639	}
640
641	static u32 stm32f7_get_lower_rate(u32 rate)
642	{
643	int i = ARRAY_SIZE(stm32f7_i2c_specs);
644
645	while (--i)
646	if (stm32f7_i2c_specs[i].rate < rate)
647	break;
648
649	return stm32f7_i2c_specs[i].rate;
650	}
651
652	static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
653	struct stm32f7_i2c_setup *setup)
654	{
655	struct i2c_timings timings, *t = &timings;
656	int ret = 0;
657
658	t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
659	t->scl_rise_ns = i2c_dev->setup.rise_time;
660	t->scl_fall_ns = i2c_dev->setup.fall_time;
661
662	i2c_parse_fw_timings(dev: i2c_dev->dev, t, use_defaults: false);
663
664	if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) {
665	dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n",
666	t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ);
667	return -EINVAL;
668	}
669
670	setup->speed_freq = t->bus_freq_hz;
671	i2c_dev->setup.rise_time = t->scl_rise_ns;
672	i2c_dev->setup.fall_time = t->scl_fall_ns;
673	i2c_dev->dnf_dt = t->digital_filter_width_ns;
674	setup->clock_src = clk_get_rate(clk: i2c_dev->clk);
675
676	if (!setup->clock_src) {
677	dev_err(i2c_dev->dev, "clock rate is 0\n");
678	return -EINVAL;
679	}
680
681	if (!of_property_read_bool(np: i2c_dev->dev->of_node, propname: "i2c-digital-filter"))
682	i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT;
683
684	do {
685	ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
686	output: &i2c_dev->timing);
687	if (ret) {
688	dev_err(i2c_dev->dev,
689	"failed to compute I2C timings.\n");
690	if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ)
691	break;
692	setup->speed_freq =
693	stm32f7_get_lower_rate(rate: setup->speed_freq);
694	dev_warn(i2c_dev->dev,
695	"downgrade I2C Speed Freq to (%i)\n",
696	setup->speed_freq);
697	}
698	} while (ret);
699
700	if (ret) {
701	dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
702	return ret;
703	}
704
705	i2c_dev->analog_filter = of_property_read_bool(np: i2c_dev->dev->of_node,
706	propname: "i2c-analog-filter");
707
708	dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
709	setup->speed_freq, setup->clock_src);
710	dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
711	setup->rise_time, setup->fall_time);
712	dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
713	(i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf);
714
715	i2c_dev->bus_rate = setup->speed_freq;
716
717	return 0;
718	}
719
720	static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
721	{
722	void __iomem *base = i2c_dev->base;
723	u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
724
725	stm32f7_i2c_clr_bits(reg: base + STM32F7_I2C_CR1, mask);
726	}
727
728	static void stm32f7_i2c_dma_callback(void *arg)
729	{
730	struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
731	struct stm32_i2c_dma *dma = i2c_dev->dma;
732	struct device *dev = dma->chan_using->device->dev;
733
734	stm32f7_i2c_disable_dma_req(i2c_dev);
735	dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
736	complete(&dma->dma_complete);
737	}
738
739	static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
740	{
741	struct stm32f7_i2c_timings *t = &i2c_dev->timing;
742	u32 timing = 0;
743
744	/* Timing settings */
745	timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
746	timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
747	timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
748	timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
749	timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
750	writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
751
752	/* Configure the Analog Filter */
753	if (i2c_dev->analog_filter)
754	stm32f7_i2c_clr_bits(reg: i2c_dev->base + STM32F7_I2C_CR1,
755	STM32F7_I2C_CR1_ANFOFF);
756	else
757	stm32f7_i2c_set_bits(reg: i2c_dev->base + STM32F7_I2C_CR1,
758	STM32F7_I2C_CR1_ANFOFF);
759
760	/* Program the Digital Filter */
761	stm32f7_i2c_clr_bits(reg: i2c_dev->base + STM32F7_I2C_CR1,
762	STM32F7_I2C_CR1_DNF_MASK);
763	stm32f7_i2c_set_bits(reg: i2c_dev->base + STM32F7_I2C_CR1,
764	STM32F7_I2C_CR1_DNF(i2c_dev->dnf));
765
766	stm32f7_i2c_set_bits(reg: i2c_dev->base + STM32F7_I2C_CR1,
767	STM32F7_I2C_CR1_PE);
768	}
769
770	static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
771	{
772	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
773	void __iomem *base = i2c_dev->base;
774
775	if (f7_msg->count) {
776	writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
777	f7_msg->count--;
778	}
779	}
780
781	static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
782	{
783	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
784	void __iomem *base = i2c_dev->base;
785
786	if (f7_msg->count) {
787	*f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
788	f7_msg->count--;
789	} else {
790	/* Flush RX buffer has no data is expected */
791	readb_relaxed(base + STM32F7_I2C_RXDR);
792	}
793	}
794
795	static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
796	{
797	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
798	u32 cr2;
799
800	if (i2c_dev->use_dma)
801	f7_msg->count -= STM32F7_I2C_MAX_LEN;
802
803	cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
804
805	cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
806	if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
807	cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
808	} else {
809	cr2 &= ~STM32F7_I2C_CR2_RELOAD;
810	cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
811	}
812
813	writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
814	}
815
816	static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
817	{
818	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
819	u32 cr2;
820	u8 *val;
821
822	/*
823	* For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
824	* data received inform us how many data will follow.
825	*/
826	stm32f7_i2c_read_rx_data(i2c_dev);
827
828	/*
829	* Update NBYTES with the value read to continue the transfer
830	*/
831	val = f7_msg->buf - sizeof(u8);
832	f7_msg->count = *val;
833	cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
834	cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
835	cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
836	writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
837	}
838
839	static void stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
840	{
841	struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap: i2c_adap);
842
843	stm32f7_i2c_clr_bits(reg: i2c_dev->base + STM32F7_I2C_CR1,
844	STM32F7_I2C_CR1_PE);
845
846	stm32f7_i2c_hw_config(i2c_dev);
847	}
848
849	static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
850	{
851	u32 status;
852	int ret;
853
854	ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
855	status,
856	!(status & STM32F7_I2C_ISR_BUSY),
857	10, 1000);
858	if (!ret)
859	return 0;
860
861	stm32f7_i2c_release_bus(i2c_adap: &i2c_dev->adap);
862
863	return -EBUSY;
864	}
865
866	static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
867	struct i2c_msg *msg)
868	{
869	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
870	void __iomem *base = i2c_dev->base;
871	u32 cr1, cr2;
872	int ret;
873
874	f7_msg->addr = msg->addr;
875	f7_msg->buf = msg->buf;
876	f7_msg->count = msg->len;
877	f7_msg->result = 0;
878	f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
879
880	reinit_completion(x: &i2c_dev->complete);
881
882	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
883	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
884
885	/* Set transfer direction */
886	cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
887	if (msg->flags & I2C_M_RD)
888	cr2 |= STM32F7_I2C_CR2_RD_WRN;
889
890	/* Set slave address */
891	cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
892	if (msg->flags & I2C_M_TEN) {
893	cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
894	cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
895	cr2 |= STM32F7_I2C_CR2_ADD10;
896	} else {
897	cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
898	cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
899	}
900
901	/* Set nb bytes to transfer and reload if needed */
902	cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
903	if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
904	cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
905	cr2 |= STM32F7_I2C_CR2_RELOAD;
906	} else {
907	cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
908	}
909
910	/* Enable NACK, STOP, error and transfer complete interrupts */
911	cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
912	STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
913
914	/* Clear DMA req and TX/RX interrupt */
915	cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
916	STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
917
918	/* Configure DMA or enable RX/TX interrupt */
919	i2c_dev->use_dma = false;
920	if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN
921	&& !i2c_dev->atomic) {
922	ret = stm32_i2c_prep_dma_xfer(dev: i2c_dev->dev, dma: i2c_dev->dma,
923	rd_wr: msg->flags & I2C_M_RD,
924	len: f7_msg->count, buf: f7_msg->buf,
925	callback: stm32f7_i2c_dma_callback,
926	dma_async_param: i2c_dev);
927	if (!ret)
928	i2c_dev->use_dma = true;
929	else
930	dev_warn(i2c_dev->dev, "can't use DMA\n");
931	}
932
933	if (!i2c_dev->use_dma) {
934	if (msg->flags & I2C_M_RD)
935	cr1 |= STM32F7_I2C_CR1_RXIE;
936	else
937	cr1 |= STM32F7_I2C_CR1_TXIE;
938	} else {
939	if (msg->flags & I2C_M_RD)
940	cr1 |= STM32F7_I2C_CR1_RXDMAEN;
941	else
942	cr1 |= STM32F7_I2C_CR1_TXDMAEN;
943	}
944
945	if (i2c_dev->atomic)
946	cr1 &= ~STM32F7_I2C_ALL_IRQ_MASK; /* Disable all interrupts */
947
948	/* Configure Start/Repeated Start */
949	cr2 |= STM32F7_I2C_CR2_START;
950
951	i2c_dev->master_mode = true;
952
953	/* Write configurations registers */
954	writel_relaxed(cr1, base + STM32F7_I2C_CR1);
955	writel_relaxed(cr2, base + STM32F7_I2C_CR2);
956	}
957
958	static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
959	unsigned short flags, u8 command,
960	union i2c_smbus_data *data)
961	{
962	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
963	struct device *dev = i2c_dev->dev;
964	void __iomem *base = i2c_dev->base;
965	u32 cr1, cr2;
966	int i, ret;
967
968	f7_msg->result = 0;
969	reinit_completion(x: &i2c_dev->complete);
970
971	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
972	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
973
974	/* Set transfer direction */
975	cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
976	if (f7_msg->read_write)
977	cr2 |= STM32F7_I2C_CR2_RD_WRN;
978
979	/* Set slave address */
980	cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
981	cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
982
983	f7_msg->smbus_buf[0] = command;
984	switch (f7_msg->size) {
985	case I2C_SMBUS_QUICK:
986	f7_msg->stop = true;
987	f7_msg->count = 0;
988	break;
989	case I2C_SMBUS_BYTE:
990	f7_msg->stop = true;
991	f7_msg->count = 1;
992	break;
993	case I2C_SMBUS_BYTE_DATA:
994	if (f7_msg->read_write) {
995	f7_msg->stop = false;
996	f7_msg->count = 1;
997	cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
998	} else {
999	f7_msg->stop = true;
1000	f7_msg->count = 2;
1001	f7_msg->smbus_buf[1] = data->byte;
1002	}
1003	break;
1004	case I2C_SMBUS_WORD_DATA:
1005	if (f7_msg->read_write) {
1006	f7_msg->stop = false;
1007	f7_msg->count = 1;
1008	cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1009	} else {
1010	f7_msg->stop = true;
1011	f7_msg->count = 3;
1012	f7_msg->smbus_buf[1] = data->word & 0xff;
1013	f7_msg->smbus_buf[2] = data->word >> 8;
1014	}
1015	break;
1016	case I2C_SMBUS_BLOCK_DATA:
1017	if (f7_msg->read_write) {
1018	f7_msg->stop = false;
1019	f7_msg->count = 1;
1020	cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1021	} else {
1022	f7_msg->stop = true;
1023	if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
1024	!data->block[0]) {
1025	dev_err(dev, "Invalid block write size %d\n",
1026	data->block[0]);
1027	return -EINVAL;
1028	}
1029	f7_msg->count = data->block[0] + 2;
1030	for (i = 1; i < f7_msg->count; i++)
1031	f7_msg->smbus_buf[i] = data->block[i - 1];
1032	}
1033	break;
1034	case I2C_SMBUS_PROC_CALL:
1035	f7_msg->stop = false;
1036	f7_msg->count = 3;
1037	f7_msg->smbus_buf[1] = data->word & 0xff;
1038	f7_msg->smbus_buf[2] = data->word >> 8;
1039	cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1040	f7_msg->read_write = I2C_SMBUS_READ;
1041	break;
1042	case I2C_SMBUS_BLOCK_PROC_CALL:
1043	f7_msg->stop = false;
1044	if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
1045	dev_err(dev, "Invalid block write size %d\n",
1046	data->block[0]);
1047	return -EINVAL;
1048	}
1049	f7_msg->count = data->block[0] + 2;
1050	for (i = 1; i < f7_msg->count; i++)
1051	f7_msg->smbus_buf[i] = data->block[i - 1];
1052	cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1053	f7_msg->read_write = I2C_SMBUS_READ;
1054	break;
1055	case I2C_SMBUS_I2C_BLOCK_DATA:
1056	/* Rely on emulated i2c transfer (through master_xfer) */
1057	return -EOPNOTSUPP;
1058	default:
1059	dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
1060	return -EOPNOTSUPP;
1061	}
1062
1063	f7_msg->buf = f7_msg->smbus_buf;
1064
1065	/* Configure PEC */
1066	if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
1067	cr1 |= STM32F7_I2C_CR1_PECEN;
1068	if (!f7_msg->read_write) {
1069	cr2 |= STM32F7_I2C_CR2_PECBYTE;
1070	f7_msg->count++;
1071	}
1072	} else {
1073	cr1 &= ~STM32F7_I2C_CR1_PECEN;
1074	cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1075	}
1076
1077	/* Set number of bytes to be transferred */
1078	cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1079	cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1080
1081	/* Enable NACK, STOP, error and transfer complete interrupts */
1082	cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1083	STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1084
1085	/* Clear DMA req and TX/RX interrupt */
1086	cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1087	STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1088
1089	/* Configure DMA or enable RX/TX interrupt */
1090	i2c_dev->use_dma = false;
1091	if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1092	ret = stm32_i2c_prep_dma_xfer(dev: i2c_dev->dev, dma: i2c_dev->dma,
1093	rd_wr: cr2 & STM32F7_I2C_CR2_RD_WRN,
1094	len: f7_msg->count, buf: f7_msg->buf,
1095	callback: stm32f7_i2c_dma_callback,
1096	dma_async_param: i2c_dev);
1097	if (!ret)
1098	i2c_dev->use_dma = true;
1099	else
1100	dev_warn(i2c_dev->dev, "can't use DMA\n");
1101	}
1102
1103	if (!i2c_dev->use_dma) {
1104	if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1105	cr1 |= STM32F7_I2C_CR1_RXIE;
1106	else
1107	cr1 |= STM32F7_I2C_CR1_TXIE;
1108	} else {
1109	if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1110	cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1111	else
1112	cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1113	}
1114
1115	/* Set Start bit */
1116	cr2 |= STM32F7_I2C_CR2_START;
1117
1118	i2c_dev->master_mode = true;
1119
1120	/* Write configurations registers */
1121	writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1122	writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1123
1124	return 0;
1125	}
1126
1127	static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1128	{
1129	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1130	void __iomem *base = i2c_dev->base;
1131	u32 cr1, cr2;
1132	int ret;
1133
1134	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1135	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1136
1137	/* Set transfer direction */
1138	cr2 |= STM32F7_I2C_CR2_RD_WRN;
1139
1140	switch (f7_msg->size) {
1141	case I2C_SMBUS_BYTE_DATA:
1142	f7_msg->count = 1;
1143	break;
1144	case I2C_SMBUS_WORD_DATA:
1145	case I2C_SMBUS_PROC_CALL:
1146	f7_msg->count = 2;
1147	break;
1148	case I2C_SMBUS_BLOCK_DATA:
1149	case I2C_SMBUS_BLOCK_PROC_CALL:
1150	f7_msg->count = 1;
1151	cr2 |= STM32F7_I2C_CR2_RELOAD;
1152	break;
1153	}
1154
1155	f7_msg->buf = f7_msg->smbus_buf;
1156	f7_msg->stop = true;
1157
1158	/* Add one byte for PEC if needed */
1159	if (cr1 & STM32F7_I2C_CR1_PECEN) {
1160	cr2 |= STM32F7_I2C_CR2_PECBYTE;
1161	f7_msg->count++;
1162	}
1163
1164	/* Set number of bytes to be transferred */
1165	cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1166	cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1167
1168	/*
1169	* Configure RX/TX interrupt:
1170	*/
1171	cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1172	cr1 |= STM32F7_I2C_CR1_RXIE;
1173
1174	/*
1175	* Configure DMA or enable RX/TX interrupt:
1176	* For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1177	* dma as we don't know in advance how many data will be received
1178	*/
1179	cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1180	STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1181
1182	i2c_dev->use_dma = false;
1183	if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1184	f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1185	f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1186	ret = stm32_i2c_prep_dma_xfer(dev: i2c_dev->dev, dma: i2c_dev->dma,
1187	rd_wr: cr2 & STM32F7_I2C_CR2_RD_WRN,
1188	len: f7_msg->count, buf: f7_msg->buf,
1189	callback: stm32f7_i2c_dma_callback,
1190	dma_async_param: i2c_dev);
1191
1192	if (!ret)
1193	i2c_dev->use_dma = true;
1194	else
1195	dev_warn(i2c_dev->dev, "can't use DMA\n");
1196	}
1197
1198	if (!i2c_dev->use_dma)
1199	cr1 |= STM32F7_I2C_CR1_RXIE;
1200	else
1201	cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1202
1203	/* Configure Repeated Start */
1204	cr2 |= STM32F7_I2C_CR2_START;
1205
1206	/* Write configurations registers */
1207	writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1208	writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1209	}
1210
1211	static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1212	{
1213	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1214	u8 count, internal_pec, received_pec;
1215
1216	internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1217
1218	switch (f7_msg->size) {
1219	case I2C_SMBUS_BYTE:
1220	case I2C_SMBUS_BYTE_DATA:
1221	received_pec = f7_msg->smbus_buf[1];
1222	break;
1223	case I2C_SMBUS_WORD_DATA:
1224	case I2C_SMBUS_PROC_CALL:
1225	received_pec = f7_msg->smbus_buf[2];
1226	break;
1227	case I2C_SMBUS_BLOCK_DATA:
1228	case I2C_SMBUS_BLOCK_PROC_CALL:
1229	count = f7_msg->smbus_buf[0];
1230	received_pec = f7_msg->smbus_buf[count];
1231	break;
1232	default:
1233	dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1234	return -EINVAL;
1235	}
1236
1237	if (internal_pec != received_pec) {
1238	dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1239	internal_pec, received_pec);
1240	return -EBADMSG;
1241	}
1242
1243	return 0;
1244	}
1245
1246	static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1247	{
1248	u32 addr;
1249
1250	if (!slave)
1251	return false;
1252
1253	if (slave->flags & I2C_CLIENT_TEN) {
1254	/*
1255	* For 10-bit addr, addcode = 11110XY with
1256	* X = Bit 9 of slave address
1257	* Y = Bit 8 of slave address
1258	*/
1259	addr = slave->addr >> 8;
1260	addr |= 0x78;
1261	if (addr == addcode)
1262	return true;
1263	} else {
1264	addr = slave->addr & 0x7f;
1265	if (addr == addcode)
1266	return true;
1267	}
1268
1269	return false;
1270	}
1271
1272	static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1273	{
1274	struct i2c_client *slave = i2c_dev->slave_running;
1275	void __iomem *base = i2c_dev->base;
1276	u32 mask;
1277	u8 value = 0;
1278
1279	if (i2c_dev->slave_dir) {
1280	/* Notify i2c slave that new read transfer is starting */
1281	i2c_slave_event(client: slave, event: I2C_SLAVE_READ_REQUESTED, val: &value);
1282
1283	/*
1284	* Disable slave TX config in case of I2C combined message
1285	* (I2C Write followed by I2C Read)
1286	*/
1287	mask = STM32F7_I2C_CR2_RELOAD;
1288	stm32f7_i2c_clr_bits(reg: base + STM32F7_I2C_CR2, mask);
1289	mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1290	STM32F7_I2C_CR1_TCIE;
1291	stm32f7_i2c_clr_bits(reg: base + STM32F7_I2C_CR1, mask);
1292
1293	/* Enable TX empty, STOP, NACK interrupts */
1294	mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1295	STM32F7_I2C_CR1_TXIE;
1296	stm32f7_i2c_set_bits(reg: base + STM32F7_I2C_CR1, mask);
1297
1298	/* Write 1st data byte */
1299	writel_relaxed(value, base + STM32F7_I2C_TXDR);
1300	} else {
1301	/* Notify i2c slave that new write transfer is starting */
1302	i2c_slave_event(client: slave, event: I2C_SLAVE_WRITE_REQUESTED, val: &value);
1303
1304	/* Set reload mode to be able to ACK/NACK each received byte */
1305	mask = STM32F7_I2C_CR2_RELOAD;
1306	stm32f7_i2c_set_bits(reg: base + STM32F7_I2C_CR2, mask);
1307
1308	/*
1309	* Set STOP, NACK, RX empty and transfer complete interrupts.*
1310	* Set Slave Byte Control to be able to ACK/NACK each data
1311	* byte received
1312	*/
1313	mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1314	STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1315	STM32F7_I2C_CR1_TCIE;
1316	stm32f7_i2c_set_bits(reg: base + STM32F7_I2C_CR1, mask);
1317	}
1318	}
1319
1320	static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1321	{
1322	void __iomem *base = i2c_dev->base;
1323	u32 isr, addcode, dir, mask;
1324	int i;
1325
1326	isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1327	addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1328	dir = isr & STM32F7_I2C_ISR_DIR;
1329
1330	for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1331	if (stm32f7_i2c_is_addr_match(slave: i2c_dev->slave[i], addcode)) {
1332	i2c_dev->slave_running = i2c_dev->slave[i];
1333	i2c_dev->slave_dir = dir;
1334
1335	/* Start I2C slave processing */
1336	stm32f7_i2c_slave_start(i2c_dev);
1337
1338	/* Clear ADDR flag */
1339	mask = STM32F7_I2C_ICR_ADDRCF;
1340	writel_relaxed(mask, base + STM32F7_I2C_ICR);
1341	break;
1342	}
1343	}
1344	}
1345
1346	static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1347	struct i2c_client *slave, int *id)
1348	{
1349	int i;
1350
1351	for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1352	if (i2c_dev->slave[i] == slave) {
1353	*id = i;
1354	return 0;
1355	}
1356	}
1357
1358	dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1359
1360	return -ENODEV;
1361	}
1362
1363	static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1364	struct i2c_client *slave, int *id)
1365	{
1366	struct device *dev = i2c_dev->dev;
1367	int i;
1368
1369	/*
1370	* slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8)
1371	* slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address
1372	* slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only
1373	*/
1374	if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
1375	if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY])
1376	goto fail;
1377	*id = STM32F7_SLAVE_HOSTNOTIFY;
1378	return 0;
1379	}
1380
1381	for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) {
1382	if ((i == STM32F7_SLAVE_7_BITS_ADDR) &&
1383	(slave->flags & I2C_CLIENT_TEN))
1384	continue;
1385	if (!i2c_dev->slave[i]) {
1386	*id = i;
1387	return 0;
1388	}
1389	}
1390
1391	fail:
1392	dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1393
1394	return -EINVAL;
1395	}
1396
1397	static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1398	{
1399	int i;
1400
1401	for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1402	if (i2c_dev->slave[i])
1403	return true;
1404	}
1405
1406	return false;
1407	}
1408
1409	static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1410	{
1411	int i, busy;
1412
1413	busy = 0;
1414	for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1415	if (i2c_dev->slave[i])
1416	busy++;
1417	}
1418
1419	return i == busy;
1420	}
1421
1422	static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1423	{
1424	void __iomem *base = i2c_dev->base;
1425	u32 cr2, status, mask;
1426	u8 val;
1427	int ret;
1428
1429	status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1430
1431	/* Slave transmitter mode */
1432	if (status & STM32F7_I2C_ISR_TXIS) {
1433	i2c_slave_event(client: i2c_dev->slave_running,
1434	event: I2C_SLAVE_READ_PROCESSED,
1435	val: &val);
1436
1437	/* Write data byte */
1438	writel_relaxed(val, base + STM32F7_I2C_TXDR);
1439	}
1440
1441	/* Transfer Complete Reload for Slave receiver mode */
1442	if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1443	/*
1444	* Read data byte then set NBYTES to receive next byte or NACK
1445	* the current received byte
1446	*/
1447	val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1448	ret = i2c_slave_event(client: i2c_dev->slave_running,
1449	event: I2C_SLAVE_WRITE_RECEIVED,
1450	val: &val);
1451	if (!ret) {
1452	cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1453	cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1454	writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1455	} else {
1456	mask = STM32F7_I2C_CR2_NACK;
1457	stm32f7_i2c_set_bits(reg: base + STM32F7_I2C_CR2, mask);
1458	}
1459	}
1460
1461	/* NACK received */
1462	if (status & STM32F7_I2C_ISR_NACKF) {
1463	dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1464	writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1465	}
1466
1467	/* STOP received */
1468	if (status & STM32F7_I2C_ISR_STOPF) {
1469	/* Disable interrupts */
1470	stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1471
1472	if (i2c_dev->slave_dir) {
1473	/*
1474	* Flush TX buffer in order to not used the byte in
1475	* TXDR for the next transfer
1476	*/
1477	mask = STM32F7_I2C_ISR_TXE;
1478	stm32f7_i2c_set_bits(reg: base + STM32F7_I2C_ISR, mask);
1479	}
1480
1481	/* Clear STOP flag */
1482	writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1483
1484	/* Notify i2c slave that a STOP flag has been detected */
1485	i2c_slave_event(client: i2c_dev->slave_running, event: I2C_SLAVE_STOP, val: &val);
1486
1487	i2c_dev->slave_running = NULL;
1488	}
1489
1490	/* Address match received */
1491	if (status & STM32F7_I2C_ISR_ADDR)
1492	stm32f7_i2c_slave_addr(i2c_dev);
1493
1494	return IRQ_HANDLED;
1495	}
1496
1497	static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1498	{
1499	struct stm32f7_i2c_dev *i2c_dev = data;
1500	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1501	struct stm32_i2c_dma *dma = i2c_dev->dma;
1502	void __iomem *base = i2c_dev->base;
1503	u32 status, mask;
1504	int ret = IRQ_HANDLED;
1505
1506	/* Check if the interrupt if for a slave device */
1507	if (!i2c_dev->master_mode) {
1508	ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1509	return ret;
1510	}
1511
1512	status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1513
1514	/* Tx empty */
1515	if (status & STM32F7_I2C_ISR_TXIS)
1516	stm32f7_i2c_write_tx_data(i2c_dev);
1517
1518	/* RX not empty */
1519	if (status & STM32F7_I2C_ISR_RXNE)
1520	stm32f7_i2c_read_rx_data(i2c_dev);
1521
1522	/* NACK received */
1523	if (status & STM32F7_I2C_ISR_NACKF) {
1524	dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
1525	__func__, f7_msg->addr);
1526	writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1527	if (i2c_dev->use_dma) {
1528	stm32f7_i2c_disable_dma_req(i2c_dev);
1529	dmaengine_terminate_async(chan: dma->chan_using);
1530	}
1531	f7_msg->result = -ENXIO;
1532	}
1533
1534	/* STOP detection flag */
1535	if (status & STM32F7_I2C_ISR_STOPF) {
1536	/* Disable interrupts */
1537	if (stm32f7_i2c_is_slave_registered(i2c_dev))
1538	mask = STM32F7_I2C_XFER_IRQ_MASK;
1539	else
1540	mask = STM32F7_I2C_ALL_IRQ_MASK;
1541	stm32f7_i2c_disable_irq(i2c_dev, mask);
1542
1543	/* Clear STOP flag */
1544	writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1545
1546	if (i2c_dev->use_dma && !f7_msg->result) {
1547	ret = IRQ_WAKE_THREAD;
1548	} else {
1549	i2c_dev->master_mode = false;
1550	complete(&i2c_dev->complete);
1551	}
1552	}
1553
1554	/* Transfer complete */
1555	if (status & STM32F7_I2C_ISR_TC) {
1556	if (f7_msg->stop) {
1557	mask = STM32F7_I2C_CR2_STOP;
1558	stm32f7_i2c_set_bits(reg: base + STM32F7_I2C_CR2, mask);
1559	} else if (i2c_dev->use_dma && !f7_msg->result) {
1560	ret = IRQ_WAKE_THREAD;
1561	} else if (f7_msg->smbus) {
1562	stm32f7_i2c_smbus_rep_start(i2c_dev);
1563	} else {
1564	i2c_dev->msg_id++;
1565	i2c_dev->msg++;
1566	stm32f7_i2c_xfer_msg(i2c_dev, msg: i2c_dev->msg);
1567	}
1568	}
1569
1570	if (status & STM32F7_I2C_ISR_TCR) {
1571	if (f7_msg->smbus)
1572	stm32f7_i2c_smbus_reload(i2c_dev);
1573	else
1574	stm32f7_i2c_reload(i2c_dev);
1575	}
1576
1577	return ret;
1578	}
1579
1580	static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1581	{
1582	struct stm32f7_i2c_dev *i2c_dev = data;
1583	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1584	struct stm32_i2c_dma *dma = i2c_dev->dma;
1585	u32 status;
1586	int ret;
1587
1588	/*
1589	* Wait for dma transfer completion before sending next message or
1590	* notity the end of xfer to the client
1591	*/
1592	ret = wait_for_completion_timeout(x: &i2c_dev->dma->dma_complete, HZ);
1593	if (!ret) {
1594	dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1595	stm32f7_i2c_disable_dma_req(i2c_dev);
1596	dmaengine_terminate_async(chan: dma->chan_using);
1597	f7_msg->result = -ETIMEDOUT;
1598	}
1599
1600	status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1601
1602	if (status & STM32F7_I2C_ISR_TC) {
1603	if (f7_msg->smbus) {
1604	stm32f7_i2c_smbus_rep_start(i2c_dev);
1605	} else {
1606	i2c_dev->msg_id++;
1607	i2c_dev->msg++;
1608	stm32f7_i2c_xfer_msg(i2c_dev, msg: i2c_dev->msg);
1609	}
1610	} else {
1611	i2c_dev->master_mode = false;
1612	complete(&i2c_dev->complete);
1613	}
1614
1615	return IRQ_HANDLED;
1616	}
1617
1618	static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1619	{
1620	struct stm32f7_i2c_dev *i2c_dev = data;
1621	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1622	void __iomem *base = i2c_dev->base;
1623	struct device *dev = i2c_dev->dev;
1624	struct stm32_i2c_dma *dma = i2c_dev->dma;
1625	u32 status;
1626
1627	status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1628
1629	/* Bus error */
1630	if (status & STM32F7_I2C_ISR_BERR) {
1631	dev_err(dev, "<%s>: Bus error accessing addr 0x%x\n",
1632	__func__, f7_msg->addr);
1633	writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1634	stm32f7_i2c_release_bus(i2c_adap: &i2c_dev->adap);
1635	f7_msg->result = -EIO;
1636	}
1637
1638	/* Arbitration loss */
1639	if (status & STM32F7_I2C_ISR_ARLO) {
1640	dev_dbg(dev, "<%s>: Arbitration loss accessing addr 0x%x\n",
1641	__func__, f7_msg->addr);
1642	writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1643	f7_msg->result = -EAGAIN;
1644	}
1645
1646	if (status & STM32F7_I2C_ISR_PECERR) {
1647	dev_err(dev, "<%s>: PEC error in reception accessing addr 0x%x\n",
1648	__func__, f7_msg->addr);
1649	writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1650	f7_msg->result = -EINVAL;
1651	}
1652
1653	if (status & STM32F7_I2C_ISR_ALERT) {
1654	dev_dbg(dev, "<%s>: SMBus alert received\n", __func__);
1655	writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);
1656	i2c_handle_smbus_alert(ara: i2c_dev->alert->ara);
1657	return IRQ_HANDLED;
1658	}
1659
1660	if (!i2c_dev->slave_running) {
1661	u32 mask;
1662	/* Disable interrupts */
1663	if (stm32f7_i2c_is_slave_registered(i2c_dev))
1664	mask = STM32F7_I2C_XFER_IRQ_MASK;
1665	else
1666	mask = STM32F7_I2C_ALL_IRQ_MASK;
1667	stm32f7_i2c_disable_irq(i2c_dev, mask);
1668	}
1669
1670	/* Disable dma */
1671	if (i2c_dev->use_dma) {
1672	stm32f7_i2c_disable_dma_req(i2c_dev);
1673	dmaengine_terminate_async(chan: dma->chan_using);
1674	}
1675
1676	i2c_dev->master_mode = false;
1677	complete(&i2c_dev->complete);
1678
1679	return IRQ_HANDLED;
1680	}
1681
1682	static int stm32f7_i2c_wait_polling(struct stm32f7_i2c_dev *i2c_dev)
1683	{
1684	ktime_t timeout = ktime_add_ms(kt: ktime_get(), msec: i2c_dev->adap.timeout);
1685
1686	while (ktime_compare(cmp1: ktime_get(), cmp2: timeout) < 0) {
1687	udelay(5);
1688	stm32f7_i2c_isr_event(irq: 0, data: i2c_dev);
1689
1690	if (completion_done(x: &i2c_dev->complete))
1691	return 1;
1692	}
1693
1694	return 0;
1695	}
1696
1697	static int stm32f7_i2c_xfer_core(struct i2c_adapter *i2c_adap,
1698	struct i2c_msg msgs[], int num)
1699	{
1700	struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap: i2c_adap);
1701	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1702	struct stm32_i2c_dma *dma = i2c_dev->dma;
1703	unsigned long time_left;
1704	int ret;
1705
1706	i2c_dev->msg = msgs;
1707	i2c_dev->msg_num = num;
1708	i2c_dev->msg_id = 0;
1709	f7_msg->smbus = false;
1710
1711	ret = pm_runtime_resume_and_get(dev: i2c_dev->dev);
1712	if (ret < 0)
1713	return ret;
1714
1715	ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1716	if (ret)
1717	goto pm_free;
1718
1719	stm32f7_i2c_xfer_msg(i2c_dev, msg: msgs);
1720
1721	if (!i2c_dev->atomic)
1722	time_left = wait_for_completion_timeout(x: &i2c_dev->complete,
1723	timeout: i2c_dev->adap.timeout);
1724	else
1725	time_left = stm32f7_i2c_wait_polling(i2c_dev);
1726
1727	ret = f7_msg->result;
1728	if (ret) {
1729	if (i2c_dev->use_dma)
1730	dmaengine_synchronize(chan: dma->chan_using);
1731
1732	/*
1733	* It is possible that some unsent data have already been
1734	* written into TXDR. To avoid sending old data in a
1735	* further transfer, flush TXDR in case of any error
1736	*/
1737	writel_relaxed(STM32F7_I2C_ISR_TXE,
1738	i2c_dev->base + STM32F7_I2C_ISR);
1739	goto pm_free;
1740	}
1741
1742	if (!time_left) {
1743	dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1744	i2c_dev->msg->addr);
1745	if (i2c_dev->use_dma)
1746	dmaengine_terminate_sync(chan: dma->chan_using);
1747	stm32f7_i2c_wait_free_bus(i2c_dev);
1748	ret = -ETIMEDOUT;
1749	}
1750
1751	pm_free:
1752	pm_runtime_mark_last_busy(dev: i2c_dev->dev);
1753	pm_runtime_put_autosuspend(dev: i2c_dev->dev);
1754
1755	return (ret < 0) ? ret : num;
1756	}
1757
1758	static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1759	struct i2c_msg msgs[], int num)
1760	{
1761	struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap: i2c_adap);
1762
1763	i2c_dev->atomic = false;
1764	return stm32f7_i2c_xfer_core(i2c_adap, msgs, num);
1765	}
1766
1767	static int stm32f7_i2c_xfer_atomic(struct i2c_adapter *i2c_adap,
1768	struct i2c_msg msgs[], int num)
1769	{
1770	struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap: i2c_adap);
1771
1772	i2c_dev->atomic = true;
1773	return stm32f7_i2c_xfer_core(i2c_adap, msgs, num);
1774	}
1775
1776	static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1777	unsigned short flags, char read_write,
1778	u8 command, int size,
1779	union i2c_smbus_data *data)
1780	{
1781	struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap: adapter);
1782	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1783	struct stm32_i2c_dma *dma = i2c_dev->dma;
1784	struct device *dev = i2c_dev->dev;
1785	unsigned long timeout;
1786	int i, ret;
1787
1788	f7_msg->addr = addr;
1789	f7_msg->size = size;
1790	f7_msg->read_write = read_write;
1791	f7_msg->smbus = true;
1792
1793	ret = pm_runtime_resume_and_get(dev);
1794	if (ret < 0)
1795	return ret;
1796
1797	ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1798	if (ret)
1799	goto pm_free;
1800
1801	ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1802	if (ret)
1803	goto pm_free;
1804
1805	timeout = wait_for_completion_timeout(x: &i2c_dev->complete,
1806	timeout: i2c_dev->adap.timeout);
1807	ret = f7_msg->result;
1808	if (ret) {
1809	if (i2c_dev->use_dma)
1810	dmaengine_synchronize(chan: dma->chan_using);
1811
1812	/*
1813	* It is possible that some unsent data have already been
1814	* written into TXDR. To avoid sending old data in a
1815	* further transfer, flush TXDR in case of any error
1816	*/
1817	writel_relaxed(STM32F7_I2C_ISR_TXE,
1818	i2c_dev->base + STM32F7_I2C_ISR);
1819	goto pm_free;
1820	}
1821
1822	if (!timeout) {
1823	dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1824	if (i2c_dev->use_dma)
1825	dmaengine_terminate_sync(chan: dma->chan_using);
1826	stm32f7_i2c_wait_free_bus(i2c_dev);
1827	ret = -ETIMEDOUT;
1828	goto pm_free;
1829	}
1830
1831	/* Check PEC */
1832	if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1833	ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1834	if (ret)
1835	goto pm_free;
1836	}
1837
1838	if (read_write && size != I2C_SMBUS_QUICK) {
1839	switch (size) {
1840	case I2C_SMBUS_BYTE:
1841	case I2C_SMBUS_BYTE_DATA:
1842	data->byte = f7_msg->smbus_buf[0];
1843	break;
1844	case I2C_SMBUS_WORD_DATA:
1845	case I2C_SMBUS_PROC_CALL:
1846	data->word = f7_msg->smbus_buf[0] |
1847	(f7_msg->smbus_buf[1] << 8);
1848	break;
1849	case I2C_SMBUS_BLOCK_DATA:
1850	case I2C_SMBUS_BLOCK_PROC_CALL:
1851	for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1852	data->block[i] = f7_msg->smbus_buf[i];
1853	break;
1854	default:
1855	dev_err(dev, "Unsupported smbus transaction\n");
1856	ret = -EINVAL;
1857	}
1858	}
1859
1860	pm_free:
1861	pm_runtime_mark_last_busy(dev);
1862	pm_runtime_put_autosuspend(dev);
1863	return ret;
1864	}
1865
1866	static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1867	bool enable)
1868	{
1869	void __iomem *base = i2c_dev->base;
1870	u32 mask = STM32F7_I2C_CR1_WUPEN;
1871
1872	if (!i2c_dev->wakeup_src)
1873	return;
1874
1875	if (enable) {
1876	device_set_wakeup_enable(dev: i2c_dev->dev, enable: true);
1877	stm32f7_i2c_set_bits(reg: base + STM32F7_I2C_CR1, mask);
1878	} else {
1879	device_set_wakeup_enable(dev: i2c_dev->dev, enable: false);
1880	stm32f7_i2c_clr_bits(reg: base + STM32F7_I2C_CR1, mask);
1881	}
1882	}
1883
1884	static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1885	{
1886	struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap: slave->adapter);
1887	void __iomem *base = i2c_dev->base;
1888	struct device *dev = i2c_dev->dev;
1889	u32 oar1, oar2, mask;
1890	int id, ret;
1891
1892	if (slave->flags & I2C_CLIENT_PEC) {
1893	dev_err(dev, "SMBus PEC not supported in slave mode\n");
1894	return -EINVAL;
1895	}
1896
1897	if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1898	dev_err(dev, "Too much slave registered\n");
1899	return -EBUSY;
1900	}
1901
1902	ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, id: &id);
1903	if (ret)
1904	return ret;
1905
1906	ret = pm_runtime_resume_and_get(dev);
1907	if (ret < 0)
1908	return ret;
1909
1910	if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1911	stm32f7_i2c_enable_wakeup(i2c_dev, enable: true);
1912
1913	switch (id) {
1914	case 0:
1915	/* Slave SMBus Host */
1916	i2c_dev->slave[id] = slave;
1917	break;
1918
1919	case 1:
1920	/* Configure Own Address 1 */
1921	oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1922	oar1 &= ~STM32F7_I2C_OAR1_MASK;
1923	if (slave->flags & I2C_CLIENT_TEN) {
1924	oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1925	oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1926	} else {
1927	oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1928	}
1929	oar1 |= STM32F7_I2C_OAR1_OA1EN;
1930	i2c_dev->slave[id] = slave;
1931	writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1932	break;
1933
1934	case 2:
1935	/* Configure Own Address 2 */
1936	oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1937	oar2 &= ~STM32F7_I2C_OAR2_MASK;
1938	if (slave->flags & I2C_CLIENT_TEN) {
1939	ret = -EOPNOTSUPP;
1940	goto pm_free;
1941	}
1942
1943	oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1944	oar2 |= STM32F7_I2C_OAR2_OA2EN;
1945	i2c_dev->slave[id] = slave;
1946	writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1947	break;
1948
1949	default:
1950	dev_err(dev, "I2C slave id not supported\n");
1951	ret = -ENODEV;
1952	goto pm_free;
1953	}
1954
1955	/* Enable ACK */
1956	stm32f7_i2c_clr_bits(reg: base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1957
1958	/* Enable Address match interrupt, error interrupt and enable I2C */
1959	mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1960	STM32F7_I2C_CR1_PE;
1961	stm32f7_i2c_set_bits(reg: base + STM32F7_I2C_CR1, mask);
1962
1963	ret = 0;
1964	pm_free:
1965	if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1966	stm32f7_i2c_enable_wakeup(i2c_dev, enable: false);
1967
1968	pm_runtime_mark_last_busy(dev);
1969	pm_runtime_put_autosuspend(dev);
1970
1971	return ret;
1972	}
1973
1974	static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1975	{
1976	struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap: slave->adapter);
1977	void __iomem *base = i2c_dev->base;
1978	u32 mask;
1979	int id, ret;
1980
1981	ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, id: &id);
1982	if (ret)
1983	return ret;
1984
1985	WARN_ON(!i2c_dev->slave[id]);
1986
1987	ret = pm_runtime_resume_and_get(dev: i2c_dev->dev);
1988	if (ret < 0)
1989	return ret;
1990
1991	if (id == 1) {
1992	mask = STM32F7_I2C_OAR1_OA1EN;
1993	stm32f7_i2c_clr_bits(reg: base + STM32F7_I2C_OAR1, mask);
1994	} else if (id == 2) {
1995	mask = STM32F7_I2C_OAR2_OA2EN;
1996	stm32f7_i2c_clr_bits(reg: base + STM32F7_I2C_OAR2, mask);
1997	}
1998
1999	i2c_dev->slave[id] = NULL;
2000
2001	if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2002	stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
2003	stm32f7_i2c_enable_wakeup(i2c_dev, enable: false);
2004	}
2005
2006	pm_runtime_mark_last_busy(dev: i2c_dev->dev);
2007	pm_runtime_put_autosuspend(dev: i2c_dev->dev);
2008
2009	return 0;
2010	}
2011
2012	static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
2013	bool enable)
2014	{
2015	int ret;
2016
2017	if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
2018	IS_ERR_OR_NULL(ptr: i2c_dev->regmap))
2019	/* Optional */
2020	return 0;
2021
2022	if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
2023	ret = regmap_update_bits(map: i2c_dev->regmap,
2024	reg: i2c_dev->fmp_sreg,
2025	mask: i2c_dev->fmp_mask,
2026	val: enable ? i2c_dev->fmp_mask : 0);
2027	else
2028	ret = regmap_write(map: i2c_dev->regmap,
2029	reg: enable ? i2c_dev->fmp_sreg :
2030	i2c_dev->fmp_creg,
2031	val: i2c_dev->fmp_mask);
2032
2033	return ret;
2034	}
2035
2036	static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
2037	struct stm32f7_i2c_dev *i2c_dev)
2038	{
2039	struct device_node *np = pdev->dev.of_node;
2040	int ret;
2041
2042	i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, property: "st,syscfg-fmp");
2043	if (IS_ERR(ptr: i2c_dev->regmap))
2044	/* Optional */
2045	return 0;
2046
2047	ret = of_property_read_u32_index(np, propname: "st,syscfg-fmp", index: 1,
2048	out_value: &i2c_dev->fmp_sreg);
2049	if (ret)
2050	return ret;
2051
2052	i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
2053	i2c_dev->setup.fmp_clr_offset;
2054
2055	return of_property_read_u32_index(np, propname: "st,syscfg-fmp", index: 2,
2056	out_value: &i2c_dev->fmp_mask);
2057	}
2058
2059	static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2060	{
2061	struct i2c_adapter *adap = &i2c_dev->adap;
2062	void __iomem *base = i2c_dev->base;
2063	struct i2c_client *client;
2064
2065	client = i2c_new_slave_host_notify_device(adapter: adap);
2066	if (IS_ERR(ptr: client))
2067	return PTR_ERR(ptr: client);
2068
2069	i2c_dev->host_notify_client = client;
2070
2071	/* Enable SMBus Host address */
2072	stm32f7_i2c_set_bits(reg: base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);
2073
2074	return 0;
2075	}
2076
2077	static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2078	{
2079	void __iomem *base = i2c_dev->base;
2080
2081	if (i2c_dev->host_notify_client) {
2082	/* Disable SMBus Host address */
2083	stm32f7_i2c_clr_bits(reg: base + STM32F7_I2C_CR1,
2084	STM32F7_I2C_CR1_SMBHEN);
2085	i2c_free_slave_host_notify_device(client: i2c_dev->host_notify_client);
2086	}
2087	}
2088
2089	static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2090	{
2091	struct stm32f7_i2c_alert *alert;
2092	struct i2c_adapter *adap = &i2c_dev->adap;
2093	struct device *dev = i2c_dev->dev;
2094	void __iomem *base = i2c_dev->base;
2095
2096	alert = devm_kzalloc(dev, size: sizeof(*alert), GFP_KERNEL);
2097	if (!alert)
2098	return -ENOMEM;
2099
2100	alert->ara = i2c_new_smbus_alert_device(adapter: adap, setup: &alert->setup);
2101	if (IS_ERR(ptr: alert->ara))
2102	return PTR_ERR(ptr: alert->ara);
2103
2104	i2c_dev->alert = alert;
2105
2106	/* Enable SMBus Alert */
2107	stm32f7_i2c_set_bits(reg: base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);
2108
2109	return 0;
2110	}
2111
2112	static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2113	{
2114	struct stm32f7_i2c_alert *alert = i2c_dev->alert;
2115	void __iomem *base = i2c_dev->base;
2116
2117	if (alert) {
2118	/* Disable SMBus Alert */
2119	stm32f7_i2c_clr_bits(reg: base + STM32F7_I2C_CR1,
2120	STM32F7_I2C_CR1_ALERTEN);
2121	i2c_unregister_device(client: alert->ara);
2122	}
2123	}
2124
2125	static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
2126	{
2127	struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
2128
2129	u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
2130	I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
2131	I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
2132	I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
2133	I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
2134	I2C_FUNC_SMBUS_I2C_BLOCK;
2135
2136	if (i2c_dev->smbus_mode)
2137	func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
2138
2139	return func;
2140	}
2141
2142	static const struct i2c_algorithm stm32f7_i2c_algo = {
2143	.master_xfer = stm32f7_i2c_xfer,
2144	.master_xfer_atomic = stm32f7_i2c_xfer_atomic,
2145	.smbus_xfer = stm32f7_i2c_smbus_xfer,
2146	.functionality = stm32f7_i2c_func,
2147	.reg_slave = stm32f7_i2c_reg_slave,
2148	.unreg_slave = stm32f7_i2c_unreg_slave,
2149	};
2150
2151	static int stm32f7_i2c_probe(struct platform_device *pdev)
2152	{
2153	struct stm32f7_i2c_dev *i2c_dev;
2154	const struct stm32f7_i2c_setup *setup;
2155	struct resource *res;
2156	struct i2c_adapter *adap;
2157	struct reset_control *rst;
2158	dma_addr_t phy_addr;
2159	int irq_error, irq_event, ret;
2160
2161	i2c_dev = devm_kzalloc(dev: &pdev->dev, size: sizeof(*i2c_dev), GFP_KERNEL);
2162	if (!i2c_dev)
2163	return -ENOMEM;
2164
2165	i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, index: 0, res: &res);
2166	if (IS_ERR(ptr: i2c_dev->base))
2167	return PTR_ERR(ptr: i2c_dev->base);
2168	phy_addr = (dma_addr_t)res->start;
2169
2170	irq_event = platform_get_irq(pdev, 0);
2171	if (irq_event < 0)
2172	return irq_event;
2173
2174	irq_error = platform_get_irq(pdev, 1);
2175	if (irq_error < 0)
2176	return irq_error;
2177
2178	i2c_dev->wakeup_src = of_property_read_bool(np: pdev->dev.of_node,
2179	propname: "wakeup-source");
2180
2181	i2c_dev->clk = devm_clk_get_enabled(dev: &pdev->dev, NULL);
2182	if (IS_ERR(ptr: i2c_dev->clk))
2183	return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: i2c_dev->clk),
2184	fmt: "Failed to enable controller clock\n");
2185
2186	rst = devm_reset_control_get(dev: &pdev->dev, NULL);
2187	if (IS_ERR(ptr: rst))
2188	return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: rst),
2189	fmt: "Error: Missing reset ctrl\n");
2190
2191	reset_control_assert(rstc: rst);
2192	udelay(2);
2193	reset_control_deassert(rstc: rst);
2194
2195	i2c_dev->dev = &pdev->dev;
2196
2197	ret = devm_request_threaded_irq(dev: &pdev->dev, irq: irq_event,
2198	handler: stm32f7_i2c_isr_event,
2199	thread_fn: stm32f7_i2c_isr_event_thread,
2200	IRQF_ONESHOT,
2201	devname: pdev->name, dev_id: i2c_dev);
2202	if (ret) {
2203	dev_err(&pdev->dev, "Failed to request irq event %i\n",
2204	irq_event);
2205	return ret;
2206	}
2207
2208	ret = devm_request_irq(dev: &pdev->dev, irq: irq_error, handler: stm32f7_i2c_isr_error, irqflags: 0,
2209	devname: pdev->name, dev_id: i2c_dev);
2210	if (ret) {
2211	dev_err(&pdev->dev, "Failed to request irq error %i\n",
2212	irq_error);
2213	return ret;
2214	}
2215
2216	setup = of_device_get_match_data(dev: &pdev->dev);
2217	if (!setup) {
2218	dev_err(&pdev->dev, "Can't get device data\n");
2219	return -ENODEV;
2220	}
2221	i2c_dev->setup = *setup;
2222
2223	ret = stm32f7_i2c_setup_timing(i2c_dev, setup: &i2c_dev->setup);
2224	if (ret)
2225	return ret;
2226
2227	/* Setup Fast mode plus if necessary */
2228	if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
2229	ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2230	if (ret)
2231	return ret;
2232	ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, enable: true);
2233	if (ret)
2234	return ret;
2235	}
2236
2237	adap = &i2c_dev->adap;
2238	i2c_set_adapdata(adap, data: i2c_dev);
2239	snprintf(buf: adap->name, size: sizeof(adap->name), fmt: "STM32F7 I2C(%pa)",
2240	&res->start);
2241	adap->owner = THIS_MODULE;
2242	adap->timeout = 2 * HZ;
2243	adap->retries = 3;
2244	adap->algo = &stm32f7_i2c_algo;
2245	adap->dev.parent = &pdev->dev;
2246	adap->dev.of_node = pdev->dev.of_node;
2247
2248	init_completion(x: &i2c_dev->complete);
2249
2250	/* Init DMA config if supported */
2251	i2c_dev->dma = stm32_i2c_dma_request(dev: i2c_dev->dev, phy_addr,
2252	STM32F7_I2C_TXDR,
2253	STM32F7_I2C_RXDR);
2254	if (IS_ERR(ptr: i2c_dev->dma)) {
2255	ret = PTR_ERR(ptr: i2c_dev->dma);
2256	/* DMA support is optional, only report other errors */
2257	if (ret != -ENODEV)
2258	goto fmp_clear;
2259	dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n");
2260	i2c_dev->dma = NULL;
2261	}
2262
2263	if (i2c_dev->wakeup_src) {
2264	device_set_wakeup_capable(dev: i2c_dev->dev, capable: true);
2265
2266	ret = dev_pm_set_wake_irq(dev: i2c_dev->dev, irq: irq_event);
2267	if (ret) {
2268	dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
2269	goto clr_wakeup_capable;
2270	}
2271	}
2272
2273	platform_set_drvdata(pdev, data: i2c_dev);
2274
2275	pm_runtime_set_autosuspend_delay(dev: i2c_dev->dev,
2276	STM32F7_AUTOSUSPEND_DELAY);
2277	pm_runtime_use_autosuspend(dev: i2c_dev->dev);
2278	pm_runtime_set_active(dev: i2c_dev->dev);
2279	pm_runtime_enable(dev: i2c_dev->dev);
2280
2281	pm_runtime_get_noresume(dev: &pdev->dev);
2282
2283	stm32f7_i2c_hw_config(i2c_dev);
2284
2285	i2c_dev->smbus_mode = of_property_read_bool(np: pdev->dev.of_node, propname: "smbus");
2286
2287	ret = i2c_add_adapter(adap);
2288	if (ret)
2289	goto pm_disable;
2290
2291	if (i2c_dev->smbus_mode) {
2292	ret = stm32f7_i2c_enable_smbus_host(i2c_dev);
2293	if (ret) {
2294	dev_err(i2c_dev->dev,
2295	"failed to enable SMBus Host-Notify protocol (%d)\n",
2296	ret);
2297	goto i2c_adapter_remove;
2298	}
2299	}
2300
2301	if (of_property_read_bool(np: pdev->dev.of_node, propname: "smbus-alert")) {
2302	ret = stm32f7_i2c_enable_smbus_alert(i2c_dev);
2303	if (ret) {
2304	dev_err(i2c_dev->dev,
2305	"failed to enable SMBus alert protocol (%d)\n",
2306	ret);
2307	goto i2c_disable_smbus_host;
2308	}
2309	}
2310
2311	dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2312
2313	pm_runtime_mark_last_busy(dev: i2c_dev->dev);
2314	pm_runtime_put_autosuspend(dev: i2c_dev->dev);
2315
2316	return 0;
2317
2318	i2c_disable_smbus_host:
2319	stm32f7_i2c_disable_smbus_host(i2c_dev);
2320
2321	i2c_adapter_remove:
2322	i2c_del_adapter(adap);
2323
2324	pm_disable:
2325	pm_runtime_put_noidle(dev: i2c_dev->dev);
2326	pm_runtime_disable(dev: i2c_dev->dev);
2327	pm_runtime_set_suspended(dev: i2c_dev->dev);
2328	pm_runtime_dont_use_autosuspend(dev: i2c_dev->dev);
2329
2330	if (i2c_dev->wakeup_src)
2331	dev_pm_clear_wake_irq(dev: i2c_dev->dev);
2332
2333	clr_wakeup_capable:
2334	if (i2c_dev->wakeup_src)
2335	device_set_wakeup_capable(dev: i2c_dev->dev, capable: false);
2336
2337	if (i2c_dev->dma) {
2338	stm32_i2c_dma_free(dma: i2c_dev->dma);
2339	i2c_dev->dma = NULL;
2340	}
2341
2342	fmp_clear:
2343	stm32f7_i2c_write_fm_plus_bits(i2c_dev, enable: false);
2344
2345	return ret;
2346	}
2347
2348	static void stm32f7_i2c_remove(struct platform_device *pdev)
2349	{
2350	struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2351
2352	stm32f7_i2c_disable_smbus_alert(i2c_dev);
2353	stm32f7_i2c_disable_smbus_host(i2c_dev);
2354
2355	i2c_del_adapter(adap: &i2c_dev->adap);
2356	pm_runtime_get_sync(dev: i2c_dev->dev);
2357
2358	if (i2c_dev->wakeup_src) {
2359	dev_pm_clear_wake_irq(dev: i2c_dev->dev);
2360	/*
2361	* enforce that wakeup is disabled and that the device
2362	* is marked as non wakeup capable
2363	*/
2364	device_init_wakeup(dev: i2c_dev->dev, enable: false);
2365	}
2366
2367	pm_runtime_put_noidle(dev: i2c_dev->dev);
2368	pm_runtime_disable(dev: i2c_dev->dev);
2369	pm_runtime_set_suspended(dev: i2c_dev->dev);
2370	pm_runtime_dont_use_autosuspend(dev: i2c_dev->dev);
2371
2372	if (i2c_dev->dma) {
2373	stm32_i2c_dma_free(dma: i2c_dev->dma);
2374	i2c_dev->dma = NULL;
2375	}
2376
2377	stm32f7_i2c_write_fm_plus_bits(i2c_dev, enable: false);
2378	}
2379
2380	static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2381	{
2382	struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2383
2384	if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2385	clk_disable_unprepare(clk: i2c_dev->clk);
2386
2387	return 0;
2388	}
2389
2390	static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2391	{
2392	struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2393	int ret;
2394
2395	if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2396	ret = clk_prepare_enable(clk: i2c_dev->clk);
2397	if (ret) {
2398	dev_err(dev, "failed to prepare_enable clock\n");
2399	return ret;
2400	}
2401	}
2402
2403	return 0;
2404	}
2405
2406	static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2407	{
2408	int ret;
2409	struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2410
2411	ret = pm_runtime_resume_and_get(dev: i2c_dev->dev);
2412	if (ret < 0)
2413	return ret;
2414
2415	backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2416	backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2417	backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2418	backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2419	backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2420	stm32f7_i2c_write_fm_plus_bits(i2c_dev, enable: false);
2421
2422	pm_runtime_put_sync(dev: i2c_dev->dev);
2423
2424	return ret;
2425	}
2426
2427	static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2428	{
2429	u32 cr1;
2430	int ret;
2431	struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2432
2433	ret = pm_runtime_resume_and_get(dev: i2c_dev->dev);
2434	if (ret < 0)
2435	return ret;
2436
2437	cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2438	if (cr1 & STM32F7_I2C_CR1_PE)
2439	stm32f7_i2c_clr_bits(reg: i2c_dev->base + STM32F7_I2C_CR1,
2440	STM32F7_I2C_CR1_PE);
2441
2442	writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2443	writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2444	i2c_dev->base + STM32F7_I2C_CR1);
2445	if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2446	stm32f7_i2c_set_bits(reg: i2c_dev->base + STM32F7_I2C_CR1,
2447	STM32F7_I2C_CR1_PE);
2448	writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2449	writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2450	writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2451	stm32f7_i2c_write_fm_plus_bits(i2c_dev, enable: true);
2452
2453	pm_runtime_put_sync(dev: i2c_dev->dev);
2454
2455	return ret;
2456	}
2457
2458	static int __maybe_unused stm32f7_i2c_suspend(struct device *dev)
2459	{
2460	struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2461	int ret;
2462
2463	i2c_mark_adapter_suspended(adap: &i2c_dev->adap);
2464
2465	if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2466	ret = stm32f7_i2c_regs_backup(i2c_dev);
2467	if (ret < 0) {
2468	i2c_mark_adapter_resumed(adap: &i2c_dev->adap);
2469	return ret;
2470	}
2471
2472	pinctrl_pm_select_sleep_state(dev);
2473	pm_runtime_force_suspend(dev);
2474	}
2475
2476	return 0;
2477	}
2478
2479	static int __maybe_unused stm32f7_i2c_resume(struct device *dev)
2480	{
2481	struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2482	int ret;
2483
2484	if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2485	ret = pm_runtime_force_resume(dev);
2486	if (ret < 0)
2487	return ret;
2488	pinctrl_pm_select_default_state(dev);
2489
2490	ret = stm32f7_i2c_regs_restore(i2c_dev);
2491	if (ret < 0)
2492	return ret;
2493	}
2494
2495	i2c_mark_adapter_resumed(adap: &i2c_dev->adap);
2496
2497	return 0;
2498	}
2499
2500	static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2501	SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2502	stm32f7_i2c_runtime_resume, NULL)
2503	SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2504	};
2505
2506	static const struct of_device_id stm32f7_i2c_match[] = {
2507	{ .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2508	{ .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2509	{ .compatible = "st,stm32mp13-i2c", .data = &stm32mp13_setup},
2510	{},
2511	};
2512	MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2513
2514	static struct platform_driver stm32f7_i2c_driver = {
2515	.driver = {
2516	.name = "stm32f7-i2c",
2517	.of_match_table = stm32f7_i2c_match,
2518	.pm = &stm32f7_i2c_pm_ops,
2519	},
2520	.probe = stm32f7_i2c_probe,
2521	.remove_new = stm32f7_i2c_remove,
2522	};
2523
2524	module_platform_driver(stm32f7_i2c_driver);
2525
2526	MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2527	MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2528	MODULE_LICENSE("GPL v2");
2529