1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * AD7904/AD7914/AD7923/AD7924/AD7908/AD7918/AD7928 SPI ADC driver |
4 | * |
5 | * Copyright 2011 Analog Devices Inc (from AD7923 Driver) |
6 | * Copyright 2012 CS Systemes d'Information |
7 | */ |
8 | |
9 | #include <linux/device.h> |
10 | #include <linux/kernel.h> |
11 | #include <linux/property.h> |
12 | #include <linux/slab.h> |
13 | #include <linux/sysfs.h> |
14 | #include <linux/spi/spi.h> |
15 | #include <linux/regulator/consumer.h> |
16 | #include <linux/err.h> |
17 | #include <linux/delay.h> |
18 | #include <linux/module.h> |
19 | #include <linux/interrupt.h> |
20 | |
21 | #include <linux/iio/iio.h> |
22 | #include <linux/iio/sysfs.h> |
23 | #include <linux/iio/buffer.h> |
24 | #include <linux/iio/trigger_consumer.h> |
25 | #include <linux/iio/triggered_buffer.h> |
26 | |
27 | #define AD7923_WRITE_CR BIT(11) /* write control register */ |
28 | #define AD7923_RANGE BIT(1) /* range to REFin */ |
29 | #define AD7923_CODING BIT(0) /* coding is straight binary */ |
30 | #define AD7923_PM_MODE_AS (1) /* auto shutdown */ |
31 | #define AD7923_PM_MODE_FS (2) /* full shutdown */ |
32 | #define AD7923_PM_MODE_OPS (3) /* normal operation */ |
33 | #define AD7923_SEQUENCE_OFF (0) /* no sequence fonction */ |
34 | #define AD7923_SEQUENCE_PROTECT (2) /* no interrupt write cycle */ |
35 | #define AD7923_SEQUENCE_ON (3) /* continuous sequence */ |
36 | |
37 | |
38 | #define AD7923_PM_MODE_WRITE(mode) ((mode) << 4) /* write mode */ |
39 | #define AD7923_CHANNEL_WRITE(channel) ((channel) << 6) /* write channel */ |
40 | #define AD7923_SEQUENCE_WRITE(sequence) ((((sequence) & 1) << 3) \ |
41 | + (((sequence) & 2) << 9)) |
42 | /* write sequence fonction */ |
43 | /* left shift for CR : bit 11 transmit in first */ |
44 | #define AD7923_SHIFT_REGISTER 4 |
45 | |
46 | /* val = value, dec = left shift, bits = number of bits of the mask */ |
47 | #define (val, dec, bits) (((val) >> (dec)) & ((1 << (bits)) - 1)) |
48 | |
49 | struct ad7923_state { |
50 | struct spi_device *spi; |
51 | struct spi_transfer ring_xfer[5]; |
52 | struct spi_transfer scan_single_xfer[2]; |
53 | struct spi_message ring_msg; |
54 | struct spi_message scan_single_msg; |
55 | |
56 | struct regulator *reg; |
57 | |
58 | unsigned int settings; |
59 | |
60 | /* |
61 | * DMA (thus cache coherency maintenance) may require the |
62 | * transfer buffers to live in their own cache lines. |
63 | * Ensure rx_buf can be directly used in iio_push_to_buffers_with_timetamp |
64 | * Length = 8 channels + 4 extra for 8 byte timestamp |
65 | */ |
66 | __be16 rx_buf[12] __aligned(IIO_DMA_MINALIGN); |
67 | __be16 tx_buf[4]; |
68 | }; |
69 | |
70 | struct ad7923_chip_info { |
71 | const struct iio_chan_spec *channels; |
72 | unsigned int num_channels; |
73 | }; |
74 | |
75 | enum ad7923_id { |
76 | AD7904, |
77 | AD7914, |
78 | AD7924, |
79 | AD7908, |
80 | AD7918, |
81 | AD7928 |
82 | }; |
83 | |
84 | #define AD7923_V_CHAN(index, bits) \ |
85 | { \ |
86 | .type = IIO_VOLTAGE, \ |
87 | .indexed = 1, \ |
88 | .channel = index, \ |
89 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ |
90 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ |
91 | .address = index, \ |
92 | .scan_index = index, \ |
93 | .scan_type = { \ |
94 | .sign = 'u', \ |
95 | .realbits = (bits), \ |
96 | .storagebits = 16, \ |
97 | .shift = 12 - (bits), \ |
98 | .endianness = IIO_BE, \ |
99 | }, \ |
100 | } |
101 | |
102 | #define DECLARE_AD7923_CHANNELS(name, bits) \ |
103 | const struct iio_chan_spec name ## _channels[] = { \ |
104 | AD7923_V_CHAN(0, bits), \ |
105 | AD7923_V_CHAN(1, bits), \ |
106 | AD7923_V_CHAN(2, bits), \ |
107 | AD7923_V_CHAN(3, bits), \ |
108 | IIO_CHAN_SOFT_TIMESTAMP(4), \ |
109 | } |
110 | |
111 | #define DECLARE_AD7908_CHANNELS(name, bits) \ |
112 | const struct iio_chan_spec name ## _channels[] = { \ |
113 | AD7923_V_CHAN(0, bits), \ |
114 | AD7923_V_CHAN(1, bits), \ |
115 | AD7923_V_CHAN(2, bits), \ |
116 | AD7923_V_CHAN(3, bits), \ |
117 | AD7923_V_CHAN(4, bits), \ |
118 | AD7923_V_CHAN(5, bits), \ |
119 | AD7923_V_CHAN(6, bits), \ |
120 | AD7923_V_CHAN(7, bits), \ |
121 | IIO_CHAN_SOFT_TIMESTAMP(8), \ |
122 | } |
123 | |
124 | static DECLARE_AD7923_CHANNELS(ad7904, 8); |
125 | static DECLARE_AD7923_CHANNELS(ad7914, 10); |
126 | static DECLARE_AD7923_CHANNELS(ad7924, 12); |
127 | static DECLARE_AD7908_CHANNELS(ad7908, 8); |
128 | static DECLARE_AD7908_CHANNELS(ad7918, 10); |
129 | static DECLARE_AD7908_CHANNELS(ad7928, 12); |
130 | |
131 | static const struct ad7923_chip_info ad7923_chip_info[] = { |
132 | [AD7904] = { |
133 | .channels = ad7904_channels, |
134 | .num_channels = ARRAY_SIZE(ad7904_channels), |
135 | }, |
136 | [AD7914] = { |
137 | .channels = ad7914_channels, |
138 | .num_channels = ARRAY_SIZE(ad7914_channels), |
139 | }, |
140 | [AD7924] = { |
141 | .channels = ad7924_channels, |
142 | .num_channels = ARRAY_SIZE(ad7924_channels), |
143 | }, |
144 | [AD7908] = { |
145 | .channels = ad7908_channels, |
146 | .num_channels = ARRAY_SIZE(ad7908_channels), |
147 | }, |
148 | [AD7918] = { |
149 | .channels = ad7918_channels, |
150 | .num_channels = ARRAY_SIZE(ad7918_channels), |
151 | }, |
152 | [AD7928] = { |
153 | .channels = ad7928_channels, |
154 | .num_channels = ARRAY_SIZE(ad7928_channels), |
155 | }, |
156 | }; |
157 | |
158 | /* |
159 | * ad7923_update_scan_mode() setup the spi transfer buffer for the new scan mask |
160 | */ |
161 | static int ad7923_update_scan_mode(struct iio_dev *indio_dev, |
162 | const unsigned long *active_scan_mask) |
163 | { |
164 | struct ad7923_state *st = iio_priv(indio_dev); |
165 | int i, cmd, len; |
166 | |
167 | len = 0; |
168 | /* |
169 | * For this driver the last channel is always the software timestamp so |
170 | * skip that one. |
171 | */ |
172 | for_each_set_bit(i, active_scan_mask, indio_dev->num_channels - 1) { |
173 | cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(i) | |
174 | AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) | |
175 | st->settings; |
176 | cmd <<= AD7923_SHIFT_REGISTER; |
177 | st->tx_buf[len++] = cpu_to_be16(cmd); |
178 | } |
179 | /* build spi ring message */ |
180 | st->ring_xfer[0].tx_buf = &st->tx_buf[0]; |
181 | st->ring_xfer[0].len = len; |
182 | st->ring_xfer[0].cs_change = 1; |
183 | |
184 | spi_message_init(m: &st->ring_msg); |
185 | spi_message_add_tail(t: &st->ring_xfer[0], m: &st->ring_msg); |
186 | |
187 | for (i = 0; i < len; i++) { |
188 | st->ring_xfer[i + 1].rx_buf = &st->rx_buf[i]; |
189 | st->ring_xfer[i + 1].len = 2; |
190 | st->ring_xfer[i + 1].cs_change = 1; |
191 | spi_message_add_tail(t: &st->ring_xfer[i + 1], m: &st->ring_msg); |
192 | } |
193 | /* make sure last transfer cs_change is not set */ |
194 | st->ring_xfer[i + 1].cs_change = 0; |
195 | |
196 | return 0; |
197 | } |
198 | |
199 | static irqreturn_t ad7923_trigger_handler(int irq, void *p) |
200 | { |
201 | struct iio_poll_func *pf = p; |
202 | struct iio_dev *indio_dev = pf->indio_dev; |
203 | struct ad7923_state *st = iio_priv(indio_dev); |
204 | int b_sent; |
205 | |
206 | b_sent = spi_sync(spi: st->spi, message: &st->ring_msg); |
207 | if (b_sent) |
208 | goto done; |
209 | |
210 | iio_push_to_buffers_with_timestamp(indio_dev, data: st->rx_buf, |
211 | timestamp: iio_get_time_ns(indio_dev)); |
212 | |
213 | done: |
214 | iio_trigger_notify_done(trig: indio_dev->trig); |
215 | |
216 | return IRQ_HANDLED; |
217 | } |
218 | |
219 | static int ad7923_scan_direct(struct ad7923_state *st, unsigned int ch) |
220 | { |
221 | int ret, cmd; |
222 | |
223 | cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(ch) | |
224 | AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) | |
225 | st->settings; |
226 | cmd <<= AD7923_SHIFT_REGISTER; |
227 | st->tx_buf[0] = cpu_to_be16(cmd); |
228 | |
229 | ret = spi_sync(spi: st->spi, message: &st->scan_single_msg); |
230 | if (ret) |
231 | return ret; |
232 | |
233 | return be16_to_cpu(st->rx_buf[0]); |
234 | } |
235 | |
236 | static int ad7923_get_range(struct ad7923_state *st) |
237 | { |
238 | int vref; |
239 | |
240 | vref = regulator_get_voltage(regulator: st->reg); |
241 | if (vref < 0) |
242 | return vref; |
243 | |
244 | vref /= 1000; |
245 | |
246 | if (!(st->settings & AD7923_RANGE)) |
247 | vref *= 2; |
248 | |
249 | return vref; |
250 | } |
251 | |
252 | static int ad7923_read_raw(struct iio_dev *indio_dev, |
253 | struct iio_chan_spec const *chan, |
254 | int *val, |
255 | int *val2, |
256 | long m) |
257 | { |
258 | int ret; |
259 | struct ad7923_state *st = iio_priv(indio_dev); |
260 | |
261 | switch (m) { |
262 | case IIO_CHAN_INFO_RAW: |
263 | ret = iio_device_claim_direct_mode(indio_dev); |
264 | if (ret) |
265 | return ret; |
266 | ret = ad7923_scan_direct(st, ch: chan->address); |
267 | iio_device_release_direct_mode(indio_dev); |
268 | |
269 | if (ret < 0) |
270 | return ret; |
271 | |
272 | if (chan->address == EXTRACT(ret, 12, 4)) |
273 | *val = EXTRACT(ret, chan->scan_type.shift, |
274 | chan->scan_type.realbits); |
275 | else |
276 | return -EIO; |
277 | |
278 | return IIO_VAL_INT; |
279 | case IIO_CHAN_INFO_SCALE: |
280 | ret = ad7923_get_range(st); |
281 | if (ret < 0) |
282 | return ret; |
283 | *val = ret; |
284 | *val2 = chan->scan_type.realbits; |
285 | return IIO_VAL_FRACTIONAL_LOG2; |
286 | } |
287 | return -EINVAL; |
288 | } |
289 | |
290 | static const struct iio_info ad7923_info = { |
291 | .read_raw = &ad7923_read_raw, |
292 | .update_scan_mode = ad7923_update_scan_mode, |
293 | }; |
294 | |
295 | static void ad7923_regulator_disable(void *data) |
296 | { |
297 | struct ad7923_state *st = data; |
298 | |
299 | regulator_disable(regulator: st->reg); |
300 | } |
301 | |
302 | static int ad7923_probe(struct spi_device *spi) |
303 | { |
304 | u32 ad7923_range = AD7923_RANGE; |
305 | struct ad7923_state *st; |
306 | struct iio_dev *indio_dev; |
307 | const struct ad7923_chip_info *info; |
308 | int ret; |
309 | |
310 | indio_dev = devm_iio_device_alloc(parent: &spi->dev, sizeof_priv: sizeof(*st)); |
311 | if (!indio_dev) |
312 | return -ENOMEM; |
313 | |
314 | st = iio_priv(indio_dev); |
315 | |
316 | if (device_property_read_bool(dev: &spi->dev, propname: "adi,range-double" )) |
317 | ad7923_range = 0; |
318 | |
319 | st->spi = spi; |
320 | st->settings = AD7923_CODING | ad7923_range | |
321 | AD7923_PM_MODE_WRITE(AD7923_PM_MODE_OPS); |
322 | |
323 | info = &ad7923_chip_info[spi_get_device_id(sdev: spi)->driver_data]; |
324 | |
325 | indio_dev->name = spi_get_device_id(sdev: spi)->name; |
326 | indio_dev->modes = INDIO_DIRECT_MODE; |
327 | indio_dev->channels = info->channels; |
328 | indio_dev->num_channels = info->num_channels; |
329 | indio_dev->info = &ad7923_info; |
330 | |
331 | /* Setup default message */ |
332 | |
333 | st->scan_single_xfer[0].tx_buf = &st->tx_buf[0]; |
334 | st->scan_single_xfer[0].len = 2; |
335 | st->scan_single_xfer[0].cs_change = 1; |
336 | st->scan_single_xfer[1].rx_buf = &st->rx_buf[0]; |
337 | st->scan_single_xfer[1].len = 2; |
338 | |
339 | spi_message_init(m: &st->scan_single_msg); |
340 | spi_message_add_tail(t: &st->scan_single_xfer[0], m: &st->scan_single_msg); |
341 | spi_message_add_tail(t: &st->scan_single_xfer[1], m: &st->scan_single_msg); |
342 | |
343 | st->reg = devm_regulator_get(dev: &spi->dev, id: "refin" ); |
344 | if (IS_ERR(ptr: st->reg)) |
345 | return PTR_ERR(ptr: st->reg); |
346 | |
347 | ret = regulator_enable(regulator: st->reg); |
348 | if (ret) |
349 | return ret; |
350 | |
351 | ret = devm_add_action_or_reset(&spi->dev, ad7923_regulator_disable, st); |
352 | if (ret) |
353 | return ret; |
354 | |
355 | ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL, |
356 | &ad7923_trigger_handler, NULL); |
357 | if (ret) |
358 | return ret; |
359 | |
360 | return devm_iio_device_register(&spi->dev, indio_dev); |
361 | } |
362 | |
363 | static const struct spi_device_id ad7923_id[] = { |
364 | {"ad7904" , AD7904}, |
365 | {"ad7914" , AD7914}, |
366 | {"ad7923" , AD7924}, |
367 | {"ad7924" , AD7924}, |
368 | {"ad7908" , AD7908}, |
369 | {"ad7918" , AD7918}, |
370 | {"ad7928" , AD7928}, |
371 | {} |
372 | }; |
373 | MODULE_DEVICE_TABLE(spi, ad7923_id); |
374 | |
375 | static const struct of_device_id ad7923_of_match[] = { |
376 | { .compatible = "adi,ad7904" , }, |
377 | { .compatible = "adi,ad7914" , }, |
378 | { .compatible = "adi,ad7923" , }, |
379 | { .compatible = "adi,ad7924" , }, |
380 | { .compatible = "adi,ad7908" , }, |
381 | { .compatible = "adi,ad7918" , }, |
382 | { .compatible = "adi,ad7928" , }, |
383 | { }, |
384 | }; |
385 | MODULE_DEVICE_TABLE(of, ad7923_of_match); |
386 | |
387 | static struct spi_driver ad7923_driver = { |
388 | .driver = { |
389 | .name = "ad7923" , |
390 | .of_match_table = ad7923_of_match, |
391 | }, |
392 | .probe = ad7923_probe, |
393 | .id_table = ad7923_id, |
394 | }; |
395 | module_spi_driver(ad7923_driver); |
396 | |
397 | MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>" ); |
398 | MODULE_AUTHOR("Patrick Vasseur <patrick.vasseur@c-s.fr>" ); |
399 | MODULE_DESCRIPTION("Analog Devices AD7923 and similar ADC" ); |
400 | MODULE_LICENSE("GPL v2" ); |
401 | |