| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * This file is part of STM32 DFSDM driver |
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| 4 | * |
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| 5 | * Copyright (C) 2017, STMicroelectronics - All Rights Reserved |
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| 6 | * Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com>. |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef MDF_STM32_DFSDM__H |
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| 10 | #define MDF_STM32_DFSDM__H |
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| 11 | |
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| 12 | #include <linux/bitfield.h> |
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| 13 | |
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| 14 | /* |
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| 15 | * STM32 DFSDM - global register map |
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| 16 | * __________________________________________________________ |
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| 17 | * | Offset | Registers block | |
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| 18 | * ---------------------------------------------------------- |
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| 19 | * | 0x000 | CHANNEL 0 + COMMON CHANNEL FIELDS | |
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| 20 | * ---------------------------------------------------------- |
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| 21 | * | 0x020 | CHANNEL 1 | |
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| 22 | * ---------------------------------------------------------- |
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| 23 | * | ... | ..... | |
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| 24 | * ---------------------------------------------------------- |
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| 25 | * | 0x20 x n | CHANNEL n | |
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| 26 | * ---------------------------------------------------------- |
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| 27 | * | 0x100 | FILTER 0 + COMMON FILTER FIELDs | |
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| 28 | * ---------------------------------------------------------- |
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| 29 | * | 0x200 | FILTER 1 | |
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| 30 | * ---------------------------------------------------------- |
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| 31 | * | | ..... | |
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| 32 | * ---------------------------------------------------------- |
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| 33 | * | 0x100 x m | FILTER m | |
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| 34 | * ---------------------------------------------------------- |
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| 35 | * | | ..... | |
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| 36 | * ---------------------------------------------------------- |
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| 37 | * | 0x7F0-7FC | Identification registers | |
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| 38 | * ---------------------------------------------------------- |
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| 39 | */ |
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| 40 | |
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| 41 | /* |
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| 42 | * Channels register definitions |
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| 43 | */ |
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| 44 | #define DFSDM_CHCFGR1(y) ((y) * 0x20 + 0x00) |
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| 45 | #define DFSDM_CHCFGR2(y) ((y) * 0x20 + 0x04) |
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| 46 | #define DFSDM_AWSCDR(y) ((y) * 0x20 + 0x08) |
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| 47 | #define DFSDM_CHWDATR(y) ((y) * 0x20 + 0x0C) |
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| 48 | #define DFSDM_CHDATINR(y) ((y) * 0x20 + 0x10) |
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| 49 | |
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| 50 | /* CHCFGR1: Channel configuration register 1 */ |
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| 51 | #define DFSDM_CHCFGR1_SITP_MASK GENMASK(1, 0) |
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| 52 | #define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v) |
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| 53 | #define DFSDM_CHCFGR1_SPICKSEL_MASK GENMASK(3, 2) |
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| 54 | #define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v) |
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| 55 | #define DFSDM_CHCFGR1_SCDEN_MASK BIT(5) |
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| 56 | #define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v) |
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| 57 | #define DFSDM_CHCFGR1_CKABEN_MASK BIT(6) |
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| 58 | #define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v) |
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| 59 | #define DFSDM_CHCFGR1_CHEN_MASK BIT(7) |
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| 60 | #define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v) |
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| 61 | #define DFSDM_CHCFGR1_CHINSEL_MASK BIT(8) |
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| 62 | #define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v) |
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| 63 | #define DFSDM_CHCFGR1_DATMPX_MASK GENMASK(13, 12) |
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| 64 | #define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v) |
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| 65 | #define DFSDM_CHCFGR1_DATPACK_MASK GENMASK(15, 14) |
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| 66 | #define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v) |
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| 67 | #define DFSDM_CHCFGR1_CKOUTDIV_MASK GENMASK(23, 16) |
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| 68 | #define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v) |
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| 69 | #define DFSDM_CHCFGR1_CKOUTSRC_MASK BIT(30) |
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| 70 | #define DFSDM_CHCFGR1_CKOUTSRC(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MASK, v) |
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| 71 | #define DFSDM_CHCFGR1_DFSDMEN_MASK BIT(31) |
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| 72 | #define DFSDM_CHCFGR1_DFSDMEN(v) FIELD_PREP(DFSDM_CHCFGR1_DFSDMEN_MASK, v) |
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| 73 | |
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| 74 | /* CHCFGR2: Channel configuration register 2 */ |
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| 75 | #define DFSDM_CHCFGR2_DTRBS_MASK GENMASK(7, 3) |
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| 76 | #define DFSDM_CHCFGR2_DTRBS(v) FIELD_PREP(DFSDM_CHCFGR2_DTRBS_MASK, v) |
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| 77 | #define DFSDM_CHCFGR2_OFFSET_MASK GENMASK(31, 8) |
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| 78 | #define DFSDM_CHCFGR2_OFFSET(v) FIELD_PREP(DFSDM_CHCFGR2_OFFSET_MASK, v) |
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| 79 | |
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| 80 | /* AWSCDR: Channel analog watchdog and short circuit detector */ |
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| 81 | #define DFSDM_AWSCDR_SCDT_MASK GENMASK(7, 0) |
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| 82 | #define DFSDM_AWSCDR_SCDT(v) FIELD_PREP(DFSDM_AWSCDR_SCDT_MASK, v) |
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| 83 | #define DFSDM_AWSCDR_BKSCD_MASK GENMASK(15, 12) |
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| 84 | #define DFSDM_AWSCDR_BKSCD(v) FIELD_PREP(DFSDM_AWSCDR_BKSCD_MASK, v) |
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| 85 | #define DFSDM_AWSCDR_AWFOSR_MASK GENMASK(20, 16) |
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| 86 | #define DFSDM_AWSCDR_AWFOSR(v) FIELD_PREP(DFSDM_AWSCDR_AWFOSR_MASK, v) |
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| 87 | #define DFSDM_AWSCDR_AWFORD_MASK GENMASK(23, 22) |
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| 88 | #define DFSDM_AWSCDR_AWFORD(v) FIELD_PREP(DFSDM_AWSCDR_AWFORD_MASK, v) |
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| 89 | |
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| 90 | /* |
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| 91 | * Filters register definitions |
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| 92 | */ |
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| 93 | #define DFSDM_FILTER_BASE_ADR 0x100 |
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| 94 | #define DFSDM_FILTER_REG_MASK 0x7F |
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| 95 | #define DFSDM_FILTER_X_BASE_ADR(x) ((x) * 0x80 + DFSDM_FILTER_BASE_ADR) |
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| 96 | |
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| 97 | #define DFSDM_CR1(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x00) |
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| 98 | #define DFSDM_CR2(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x04) |
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| 99 | #define DFSDM_ISR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x08) |
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| 100 | #define DFSDM_ICR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x0C) |
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| 101 | #define DFSDM_JCHGR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x10) |
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| 102 | #define DFSDM_FCR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x14) |
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| 103 | #define DFSDM_JDATAR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x18) |
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| 104 | #define DFSDM_RDATAR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x1C) |
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| 105 | #define DFSDM_AWHTR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x20) |
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| 106 | #define DFSDM_AWLTR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x24) |
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| 107 | #define DFSDM_AWSR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x28) |
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| 108 | #define DFSDM_AWCFR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x2C) |
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| 109 | #define DFSDM_EXMAX(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x30) |
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| 110 | #define DFSDM_EXMIN(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x34) |
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| 111 | #define DFSDM_CNVTIMR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x38) |
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| 112 | |
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| 113 | /* CR1 Control register 1 */ |
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| 114 | #define DFSDM_CR1_DFEN_MASK BIT(0) |
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| 115 | #define DFSDM_CR1_DFEN(v) FIELD_PREP(DFSDM_CR1_DFEN_MASK, v) |
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| 116 | #define DFSDM_CR1_JSWSTART_MASK BIT(1) |
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| 117 | #define DFSDM_CR1_JSWSTART(v) FIELD_PREP(DFSDM_CR1_JSWSTART_MASK, v) |
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| 118 | #define DFSDM_CR1_JSYNC_MASK BIT(3) |
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| 119 | #define DFSDM_CR1_JSYNC(v) FIELD_PREP(DFSDM_CR1_JSYNC_MASK, v) |
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| 120 | #define DFSDM_CR1_JSCAN_MASK BIT(4) |
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| 121 | #define DFSDM_CR1_JSCAN(v) FIELD_PREP(DFSDM_CR1_JSCAN_MASK, v) |
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| 122 | #define DFSDM_CR1_JDMAEN_MASK BIT(5) |
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| 123 | #define DFSDM_CR1_JDMAEN(v) FIELD_PREP(DFSDM_CR1_JDMAEN_MASK, v) |
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| 124 | #define DFSDM_CR1_JEXTSEL_MASK GENMASK(12, 8) |
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| 125 | #define DFSDM_CR1_JEXTSEL(v) FIELD_PREP(DFSDM_CR1_JEXTSEL_MASK, v) |
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| 126 | #define DFSDM_CR1_JEXTEN_MASK GENMASK(14, 13) |
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| 127 | #define DFSDM_CR1_JEXTEN(v) FIELD_PREP(DFSDM_CR1_JEXTEN_MASK, v) |
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| 128 | #define DFSDM_CR1_RSWSTART_MASK BIT(17) |
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| 129 | #define DFSDM_CR1_RSWSTART(v) FIELD_PREP(DFSDM_CR1_RSWSTART_MASK, v) |
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| 130 | #define DFSDM_CR1_RCONT_MASK BIT(18) |
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| 131 | #define DFSDM_CR1_RCONT(v) FIELD_PREP(DFSDM_CR1_RCONT_MASK, v) |
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| 132 | #define DFSDM_CR1_RSYNC_MASK BIT(19) |
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| 133 | #define DFSDM_CR1_RSYNC(v) FIELD_PREP(DFSDM_CR1_RSYNC_MASK, v) |
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| 134 | #define DFSDM_CR1_RDMAEN_MASK BIT(21) |
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| 135 | #define DFSDM_CR1_RDMAEN(v) FIELD_PREP(DFSDM_CR1_RDMAEN_MASK, v) |
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| 136 | #define DFSDM_CR1_RCH_MASK GENMASK(26, 24) |
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| 137 | #define DFSDM_CR1_RCH(v) FIELD_PREP(DFSDM_CR1_RCH_MASK, v) |
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| 138 | #define DFSDM_CR1_FAST_MASK BIT(29) |
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| 139 | #define DFSDM_CR1_FAST(v) FIELD_PREP(DFSDM_CR1_FAST_MASK, v) |
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| 140 | #define DFSDM_CR1_AWFSEL_MASK BIT(30) |
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| 141 | #define DFSDM_CR1_AWFSEL(v) FIELD_PREP(DFSDM_CR1_AWFSEL_MASK, v) |
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| 142 | |
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| 143 | /* CR2: Control register 2 */ |
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| 144 | #define DFSDM_CR2_IE_MASK GENMASK(6, 0) |
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| 145 | #define DFSDM_CR2_IE(v) FIELD_PREP(DFSDM_CR2_IE_MASK, v) |
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| 146 | #define DFSDM_CR2_JEOCIE_MASK BIT(0) |
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| 147 | #define DFSDM_CR2_JEOCIE(v) FIELD_PREP(DFSDM_CR2_JEOCIE_MASK, v) |
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| 148 | #define DFSDM_CR2_REOCIE_MASK BIT(1) |
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| 149 | #define DFSDM_CR2_REOCIE(v) FIELD_PREP(DFSDM_CR2_REOCIE_MASK, v) |
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| 150 | #define DFSDM_CR2_JOVRIE_MASK BIT(2) |
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| 151 | #define DFSDM_CR2_JOVRIE(v) FIELD_PREP(DFSDM_CR2_JOVRIE_MASK, v) |
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| 152 | #define DFSDM_CR2_ROVRIE_MASK BIT(3) |
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| 153 | #define DFSDM_CR2_ROVRIE(v) FIELD_PREP(DFSDM_CR2_ROVRIE_MASK, v) |
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| 154 | #define DFSDM_CR2_AWDIE_MASK BIT(4) |
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| 155 | #define DFSDM_CR2_AWDIE(v) FIELD_PREP(DFSDM_CR2_AWDIE_MASK, v) |
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| 156 | #define DFSDM_CR2_SCDIE_MASK BIT(5) |
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| 157 | #define DFSDM_CR2_SCDIE(v) FIELD_PREP(DFSDM_CR2_SCDIE_MASK, v) |
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| 158 | #define DFSDM_CR2_CKABIE_MASK BIT(6) |
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| 159 | #define DFSDM_CR2_CKABIE(v) FIELD_PREP(DFSDM_CR2_CKABIE_MASK, v) |
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| 160 | #define DFSDM_CR2_EXCH_MASK GENMASK(15, 8) |
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| 161 | #define DFSDM_CR2_EXCH(v) FIELD_PREP(DFSDM_CR2_EXCH_MASK, v) |
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| 162 | #define DFSDM_CR2_AWDCH_MASK GENMASK(23, 16) |
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| 163 | #define DFSDM_CR2_AWDCH(v) FIELD_PREP(DFSDM_CR2_AWDCH_MASK, v) |
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| 164 | |
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| 165 | /* ISR: Interrupt status register */ |
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| 166 | #define DFSDM_ISR_JEOCF_MASK BIT(0) |
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| 167 | #define DFSDM_ISR_JEOCF(v) FIELD_PREP(DFSDM_ISR_JEOCF_MASK, v) |
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| 168 | #define DFSDM_ISR_REOCF_MASK BIT(1) |
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| 169 | #define DFSDM_ISR_REOCF(v) FIELD_PREP(DFSDM_ISR_REOCF_MASK, v) |
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| 170 | #define DFSDM_ISR_JOVRF_MASK BIT(2) |
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| 171 | #define DFSDM_ISR_JOVRF(v) FIELD_PREP(DFSDM_ISR_JOVRF_MASK, v) |
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| 172 | #define DFSDM_ISR_ROVRF_MASK BIT(3) |
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| 173 | #define DFSDM_ISR_ROVRF(v) FIELD_PREP(DFSDM_ISR_ROVRF_MASK, v) |
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| 174 | #define DFSDM_ISR_AWDF_MASK BIT(4) |
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| 175 | #define DFSDM_ISR_AWDF(v) FIELD_PREP(DFSDM_ISR_AWDF_MASK, v) |
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| 176 | #define DFSDM_ISR_JCIP_MASK BIT(13) |
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| 177 | #define DFSDM_ISR_JCIP(v) FIELD_PREP(DFSDM_ISR_JCIP_MASK, v) |
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| 178 | #define DFSDM_ISR_RCIP_MASK BIT(14) |
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| 179 | #define DFSDM_ISR_RCIP(v) FIELD_PREP(DFSDM_ISR_RCIP, v) |
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| 180 | #define DFSDM_ISR_CKABF_MASK GENMASK(23, 16) |
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| 181 | #define DFSDM_ISR_CKABF(v) FIELD_PREP(DFSDM_ISR_CKABF_MASK, v) |
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| 182 | #define DFSDM_ISR_SCDF_MASK GENMASK(31, 24) |
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| 183 | #define DFSDM_ISR_SCDF(v) FIELD_PREP(DFSDM_ISR_SCDF_MASK, v) |
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| 184 | |
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| 185 | /* ICR: Interrupt flag clear register */ |
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| 186 | #define DFSDM_ICR_CLRJOVRF_MASK BIT(2) |
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| 187 | #define DFSDM_ICR_CLRJOVRF(v) FIELD_PREP(DFSDM_ICR_CLRJOVRF_MASK, v) |
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| 188 | #define DFSDM_ICR_CLRROVRF_MASK BIT(3) |
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| 189 | #define DFSDM_ICR_CLRROVRF(v) FIELD_PREP(DFSDM_ICR_CLRROVRF_MASK, v) |
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| 190 | #define DFSDM_ICR_CLRCKABF_MASK GENMASK(23, 16) |
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| 191 | #define DFSDM_ICR_CLRCKABF(v) FIELD_PREP(DFSDM_ICR_CLRCKABF_MASK, v) |
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| 192 | #define DFSDM_ICR_CLRCKABF_CH_MASK(y) BIT(16 + (y)) |
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| 193 | #define DFSDM_ICR_CLRCKABF_CH(v, y) \ |
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| 194 | (((v) << (16 + (y))) & DFSDM_ICR_CLRCKABF_CH_MASK(y)) |
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| 195 | #define DFSDM_ICR_CLRSCDF_MASK GENMASK(31, 24) |
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| 196 | #define DFSDM_ICR_CLRSCDF(v) FIELD_PREP(DFSDM_ICR_CLRSCDF_MASK, v) |
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| 197 | #define DFSDM_ICR_CLRSCDF_CH_MASK(y) BIT(24 + (y)) |
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| 198 | #define DFSDM_ICR_CLRSCDF_CH(v, y) \ |
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| 199 | (((v) << (24 + (y))) & DFSDM_ICR_CLRSCDF_MASK(y)) |
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| 200 | |
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| 201 | /* FCR: Filter control register */ |
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| 202 | #define DFSDM_FCR_IOSR_MASK GENMASK(7, 0) |
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| 203 | #define DFSDM_FCR_IOSR(v) FIELD_PREP(DFSDM_FCR_IOSR_MASK, v) |
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| 204 | #define DFSDM_FCR_FOSR_MASK GENMASK(25, 16) |
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| 205 | #define DFSDM_FCR_FOSR(v) FIELD_PREP(DFSDM_FCR_FOSR_MASK, v) |
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| 206 | #define DFSDM_FCR_FORD_MASK GENMASK(31, 29) |
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| 207 | #define DFSDM_FCR_FORD(v) FIELD_PREP(DFSDM_FCR_FORD_MASK, v) |
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| 208 | |
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| 209 | /* RDATAR: Filter data register for regular channel */ |
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| 210 | #define DFSDM_DATAR_CH_MASK GENMASK(2, 0) |
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| 211 | #define DFSDM_DATAR_DATA_OFFSET 8 |
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| 212 | #define DFSDM_DATAR_DATA_MASK GENMASK(31, DFSDM_DATAR_DATA_OFFSET) |
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| 213 | |
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| 214 | /* AWLTR: Filter analog watchdog low threshold register */ |
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| 215 | #define DFSDM_AWLTR_BKAWL_MASK GENMASK(3, 0) |
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| 216 | #define DFSDM_AWLTR_BKAWL(v) FIELD_PREP(DFSDM_AWLTR_BKAWL_MASK, v) |
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| 217 | #define DFSDM_AWLTR_AWLT_MASK GENMASK(31, 8) |
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| 218 | #define DFSDM_AWLTR_AWLT(v) FIELD_PREP(DFSDM_AWLTR_AWLT_MASK, v) |
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| 219 | |
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| 220 | /* AWHTR: Filter analog watchdog low threshold register */ |
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| 221 | #define DFSDM_AWHTR_BKAWH_MASK GENMASK(3, 0) |
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| 222 | #define DFSDM_AWHTR_BKAWH(v) FIELD_PREP(DFSDM_AWHTR_BKAWH_MASK, v) |
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| 223 | #define DFSDM_AWHTR_AWHT_MASK GENMASK(31, 8) |
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| 224 | #define DFSDM_AWHTR_AWHT(v) FIELD_PREP(DFSDM_AWHTR_AWHT_MASK, v) |
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| 225 | |
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| 226 | /* AWSR: Filter watchdog status register */ |
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| 227 | #define DFSDM_AWSR_AWLTF_MASK GENMASK(7, 0) |
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| 228 | #define DFSDM_AWSR_AWLTF(v) FIELD_PREP(DFSDM_AWSR_AWLTF_MASK, v) |
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| 229 | #define DFSDM_AWSR_AWHTF_MASK GENMASK(15, 8) |
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| 230 | #define DFSDM_AWSR_AWHTF(v) FIELD_PREP(DFSDM_AWSR_AWHTF_MASK, v) |
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| 231 | |
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| 232 | /* AWCFR: Filter watchdog status register */ |
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| 233 | #define DFSDM_AWCFR_AWLTF_MASK GENMASK(7, 0) |
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| 234 | #define DFSDM_AWCFR_AWLTF(v) FIELD_PREP(DFSDM_AWCFR_AWLTF_MASK, v) |
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| 235 | #define DFSDM_AWCFR_AWHTF_MASK GENMASK(15, 8) |
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| 236 | #define DFSDM_AWCFR_AWHTF(v) FIELD_PREP(DFSDM_AWCFR_AWHTF_MASK, v) |
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| 237 | |
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| 238 | /* |
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| 239 | * Identification register definitions |
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| 240 | */ |
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| 241 | #define DFSDM_HWCFGR 0x7F0 |
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| 242 | #define DFSDM_VERR 0x7F4 |
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| 243 | #define DFSDM_IPIDR 0x7F8 |
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| 244 | #define DFSDM_SIDR 0x7FC |
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| 245 | |
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| 246 | /* HWCFGR: Hardware configuration register */ |
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| 247 | #define DFSDM_HWCFGR_NBT_MASK GENMASK(7, 0) |
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| 248 | #define DFSDM_HWCFGR_NBF_MASK GENMASK(15, 8) |
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| 249 | |
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| 250 | /* VERR: Version register */ |
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| 251 | #define DFSDM_VERR_MINREV_MASK GENMASK(3, 0) |
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| 252 | #define DFSDM_VERR_MAJREV_MASK GENMASK(7, 4) |
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| 253 | |
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| 254 | #define STM32MP15_IPIDR_NUMBER 0x00110031 |
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| 255 | |
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| 256 | /* DFSDM filter order */ |
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| 257 | enum stm32_dfsdm_sinc_order { |
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| 258 | DFSDM_FASTSINC_ORDER, /* FastSinc filter type */ |
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| 259 | DFSDM_SINC1_ORDER, /* Sinc 1 filter type */ |
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| 260 | DFSDM_SINC2_ORDER, /* Sinc 2 filter type */ |
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| 261 | DFSDM_SINC3_ORDER, /* Sinc 3 filter type */ |
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| 262 | DFSDM_SINC4_ORDER, /* Sinc 4 filter type (N.A. for watchdog) */ |
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| 263 | DFSDM_SINC5_ORDER, /* Sinc 5 filter type (N.A. for watchdog) */ |
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| 264 | DFSDM_NB_SINC_ORDER, |
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| 265 | }; |
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| 266 | |
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| 267 | /** |
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| 268 | * struct stm32_dfsdm_filter_osr - DFSDM filter settings linked to oversampling |
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| 269 | * @iosr: integrator oversampling |
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| 270 | * @fosr: filter oversampling |
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| 271 | * @rshift: output sample right shift (hardware shift) |
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| 272 | * @lshift: output sample left shift (software shift) |
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| 273 | * @res: output sample resolution |
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| 274 | * @bits: output sample resolution in bits |
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| 275 | * @max: output sample maximum positive value |
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| 276 | */ |
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| 277 | struct stm32_dfsdm_filter_osr { |
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| 278 | unsigned int iosr; |
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| 279 | unsigned int fosr; |
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| 280 | unsigned int rshift; |
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| 281 | unsigned int lshift; |
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| 282 | u64 res; |
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| 283 | u32 bits; |
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| 284 | s32 max; |
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| 285 | }; |
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| 286 | |
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| 287 | /** |
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| 288 | * struct stm32_dfsdm_filter - structure relative to stm32 FDSDM filter |
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| 289 | * @ford: filter order |
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| 290 | * @flo: filter oversampling data table indexed by fast mode flag |
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| 291 | * @sync_mode: filter synchronized with filter 0 |
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| 292 | * @fast: filter fast mode |
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| 293 | */ |
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| 294 | struct stm32_dfsdm_filter { |
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| 295 | enum stm32_dfsdm_sinc_order ford; |
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| 296 | struct stm32_dfsdm_filter_osr flo[2]; |
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| 297 | unsigned int sync_mode; |
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| 298 | unsigned int fast; |
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| 299 | }; |
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| 300 | |
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| 301 | /** |
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| 302 | * struct stm32_dfsdm_channel - structure relative to stm32 FDSDM channel |
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| 303 | * @id: id of the channel |
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| 304 | * @type: interface type linked to stm32_dfsdm_chan_type |
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| 305 | * @src: interface type linked to stm32_dfsdm_chan_src |
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| 306 | * @alt_si: alternative serial input interface |
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| 307 | */ |
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| 308 | struct stm32_dfsdm_channel { |
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| 309 | unsigned int id; |
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| 310 | unsigned int type; |
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| 311 | unsigned int src; |
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| 312 | unsigned int alt_si; |
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| 313 | }; |
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| 314 | |
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| 315 | /** |
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| 316 | * struct stm32_dfsdm - stm32 FDSDM driver common data (for all instances) |
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| 317 | * @base: control registers base cpu addr |
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| 318 | * @phys_base: DFSDM IP register physical address |
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| 319 | * @regmap: regmap for register read/write |
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| 320 | * @fl_list: filter resources list |
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| 321 | * @num_fls: number of filter resources available |
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| 322 | * @ch_list: channel resources list |
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| 323 | * @num_chs: number of channel resources available |
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| 324 | * @spi_master_freq: SPI clock out frequency |
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| 325 | */ |
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| 326 | struct stm32_dfsdm { |
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| 327 | void __iomem *base; |
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| 328 | phys_addr_t phys_base; |
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| 329 | struct regmap *regmap; |
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| 330 | struct stm32_dfsdm_filter *fl_list; |
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| 331 | unsigned int num_fls; |
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| 332 | struct stm32_dfsdm_channel *ch_list; |
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| 333 | unsigned int num_chs; |
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| 334 | unsigned int spi_master_freq; |
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| 335 | }; |
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| 336 | |
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| 337 | /* DFSDM channel serial spi clock source */ |
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| 338 | enum stm32_dfsdm_spi_clk_src { |
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| 339 | DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL, |
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| 340 | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL, |
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| 341 | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING, |
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| 342 | DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING |
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| 343 | }; |
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| 344 | |
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| 345 | int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm); |
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| 346 | int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm); |
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| 347 | |
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| 348 | #endif |
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| 349 | |
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