| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef _TSC200X_CORE_H |
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| 3 | #define _TSC200X_CORE_H |
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| 4 | |
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| 5 | /* control byte 1 */ |
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| 6 | #define TSC200X_CMD 0x80 |
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| 7 | #define TSC200X_CMD_NORMAL 0x00 |
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| 8 | #define TSC200X_CMD_STOP 0x01 |
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| 9 | #define TSC200X_CMD_12BIT 0x04 |
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| 10 | |
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| 11 | /* control byte 0 */ |
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| 12 | #define TSC200X_REG_READ 0x01 /* R/W access */ |
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| 13 | #define TSC200X_REG_PND0 0x02 /* Power Not Down Control */ |
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| 14 | #define TSC200X_REG_X (0x0 << 3) |
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| 15 | #define TSC200X_REG_Y (0x1 << 3) |
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| 16 | #define TSC200X_REG_Z1 (0x2 << 3) |
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| 17 | #define TSC200X_REG_Z2 (0x3 << 3) |
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| 18 | #define TSC200X_REG_AUX (0x4 << 3) |
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| 19 | #define TSC200X_REG_TEMP1 (0x5 << 3) |
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| 20 | #define TSC200X_REG_TEMP2 (0x6 << 3) |
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| 21 | #define TSC200X_REG_STATUS (0x7 << 3) |
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| 22 | #define TSC200X_REG_AUX_HIGH (0x8 << 3) |
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| 23 | #define TSC200X_REG_AUX_LOW (0x9 << 3) |
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| 24 | #define TSC200X_REG_TEMP_HIGH (0xA << 3) |
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| 25 | #define TSC200X_REG_TEMP_LOW (0xB << 3) |
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| 26 | #define TSC200X_REG_CFR0 (0xC << 3) |
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| 27 | #define TSC200X_REG_CFR1 (0xD << 3) |
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| 28 | #define TSC200X_REG_CFR2 (0xE << 3) |
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| 29 | #define TSC200X_REG_CONV_FUNC (0xF << 3) |
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| 30 | |
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| 31 | /* configuration register 0 */ |
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| 32 | #define TSC200X_CFR0_PRECHARGE_276US 0x0040 |
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| 33 | #define TSC200X_CFR0_STABTIME_1MS 0x0300 |
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| 34 | #define TSC200X_CFR0_CLOCK_1MHZ 0x1000 |
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| 35 | #define TSC200X_CFR0_RESOLUTION12 0x2000 |
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| 36 | #define TSC200X_CFR0_PENMODE 0x8000 |
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| 37 | #define TSC200X_CFR0_INITVALUE (TSC200X_CFR0_STABTIME_1MS | \ |
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| 38 | TSC200X_CFR0_CLOCK_1MHZ | \ |
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| 39 | TSC200X_CFR0_RESOLUTION12 | \ |
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| 40 | TSC200X_CFR0_PRECHARGE_276US | \ |
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| 41 | TSC200X_CFR0_PENMODE) |
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| 42 | |
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| 43 | /* bits common to both read and write of configuration register 0 */ |
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| 44 | #define TSC200X_CFR0_RW_MASK 0x3fff |
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| 45 | |
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| 46 | /* configuration register 1 */ |
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| 47 | #define TSC200X_CFR1_BATCHDELAY_4MS 0x0003 |
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| 48 | #define TSC200X_CFR1_INITVALUE TSC200X_CFR1_BATCHDELAY_4MS |
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| 49 | |
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| 50 | /* configuration register 2 */ |
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| 51 | #define TSC200X_CFR2_MAVE_Z 0x0004 |
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| 52 | #define TSC200X_CFR2_MAVE_Y 0x0008 |
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| 53 | #define TSC200X_CFR2_MAVE_X 0x0010 |
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| 54 | #define TSC200X_CFR2_AVG_7 0x0800 |
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| 55 | #define TSC200X_CFR2_MEDIUM_15 0x3000 |
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| 56 | #define TSC200X_CFR2_INITVALUE (TSC200X_CFR2_MAVE_X | \ |
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| 57 | TSC200X_CFR2_MAVE_Y | \ |
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| 58 | TSC200X_CFR2_MAVE_Z | \ |
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| 59 | TSC200X_CFR2_MEDIUM_15 | \ |
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| 60 | TSC200X_CFR2_AVG_7) |
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| 61 | |
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| 62 | #define MAX_12BIT 0xfff |
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| 63 | #define TSC200X_DEF_X_FUZZ 4 |
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| 64 | #define TSC200X_DEF_Y_FUZZ 8 |
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| 65 | #define TSC200X_DEF_P_FUZZ 2 |
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| 66 | #define TSC200X_DEF_RESISTOR 280 |
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| 67 | |
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| 68 | #define TSC2005_SPI_MAX_SPEED_HZ 10000000 |
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| 69 | #define TSC200X_PENUP_TIME_MS 40 |
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| 70 | |
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| 71 | extern const struct regmap_config tsc200x_regmap_config; |
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| 72 | extern const struct dev_pm_ops tsc200x_pm_ops; |
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| 73 | |
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| 74 | int tsc200x_probe(struct device *dev, int irq, const struct input_id *tsc_id, |
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| 75 | struct regmap *regmap, |
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| 76 | int (*tsc200x_cmd)(struct device *dev, u8 cmd)); |
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| 77 | void tsc200x_remove(struct device *dev); |
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| 78 | |
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| 79 | #endif |
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| 80 | |
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