1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/device.h>
7#include <linux/interconnect.h>
8#include <linux/interconnect-provider.h>
9#include <linux/module.h>
10#include <linux/mod_devicetable.h>
11#include <linux/platform_device.h>
12
13#include <dt-bindings/interconnect/qcom,sdm845.h>
14
15#include "bcm-voter.h"
16#include "icc-rpmh.h"
17#include "sdm845.h"
18
19static struct qcom_icc_node qhm_a1noc_cfg = {
20 .name = "qhm_a1noc_cfg",
21 .id = SDM845_MASTER_A1NOC_CFG,
22 .channels = 1,
23 .buswidth = 4,
24 .num_links = 1,
25 .links = { SDM845_SLAVE_SERVICE_A1NOC },
26};
27
28static struct qcom_icc_node qhm_qup1 = {
29 .name = "qhm_qup1",
30 .id = SDM845_MASTER_BLSP_1,
31 .channels = 1,
32 .buswidth = 4,
33 .num_links = 1,
34 .links = { SDM845_SLAVE_A1NOC_SNOC },
35};
36
37static struct qcom_icc_node qhm_tsif = {
38 .name = "qhm_tsif",
39 .id = SDM845_MASTER_TSIF,
40 .channels = 1,
41 .buswidth = 4,
42 .num_links = 1,
43 .links = { SDM845_SLAVE_A1NOC_SNOC },
44};
45
46static struct qcom_icc_node xm_sdc2 = {
47 .name = "xm_sdc2",
48 .id = SDM845_MASTER_SDCC_2,
49 .channels = 1,
50 .buswidth = 8,
51 .num_links = 1,
52 .links = { SDM845_SLAVE_A1NOC_SNOC },
53};
54
55static struct qcom_icc_node xm_sdc4 = {
56 .name = "xm_sdc4",
57 .id = SDM845_MASTER_SDCC_4,
58 .channels = 1,
59 .buswidth = 8,
60 .num_links = 1,
61 .links = { SDM845_SLAVE_A1NOC_SNOC },
62};
63
64static struct qcom_icc_node xm_ufs_card = {
65 .name = "xm_ufs_card",
66 .id = SDM845_MASTER_UFS_CARD,
67 .channels = 1,
68 .buswidth = 8,
69 .num_links = 1,
70 .links = { SDM845_SLAVE_A1NOC_SNOC },
71};
72
73static struct qcom_icc_node xm_ufs_mem = {
74 .name = "xm_ufs_mem",
75 .id = SDM845_MASTER_UFS_MEM,
76 .channels = 1,
77 .buswidth = 8,
78 .num_links = 1,
79 .links = { SDM845_SLAVE_A1NOC_SNOC },
80};
81
82static struct qcom_icc_node xm_pcie_0 = {
83 .name = "xm_pcie_0",
84 .id = SDM845_MASTER_PCIE_0,
85 .channels = 1,
86 .buswidth = 8,
87 .num_links = 1,
88 .links = { SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC },
89};
90
91static struct qcom_icc_node qhm_a2noc_cfg = {
92 .name = "qhm_a2noc_cfg",
93 .id = SDM845_MASTER_A2NOC_CFG,
94 .channels = 1,
95 .buswidth = 4,
96 .num_links = 1,
97 .links = { SDM845_SLAVE_SERVICE_A2NOC },
98};
99
100static struct qcom_icc_node qhm_qdss_bam = {
101 .name = "qhm_qdss_bam",
102 .id = SDM845_MASTER_QDSS_BAM,
103 .channels = 1,
104 .buswidth = 4,
105 .num_links = 1,
106 .links = { SDM845_SLAVE_A2NOC_SNOC },
107};
108
109static struct qcom_icc_node qhm_qup2 = {
110 .name = "qhm_qup2",
111 .id = SDM845_MASTER_BLSP_2,
112 .channels = 1,
113 .buswidth = 4,
114 .num_links = 1,
115 .links = { SDM845_SLAVE_A2NOC_SNOC },
116};
117
118static struct qcom_icc_node qnm_cnoc = {
119 .name = "qnm_cnoc",
120 .id = SDM845_MASTER_CNOC_A2NOC,
121 .channels = 1,
122 .buswidth = 8,
123 .num_links = 1,
124 .links = { SDM845_SLAVE_A2NOC_SNOC },
125};
126
127static struct qcom_icc_node qxm_crypto = {
128 .name = "qxm_crypto",
129 .id = SDM845_MASTER_CRYPTO,
130 .channels = 1,
131 .buswidth = 8,
132 .num_links = 1,
133 .links = { SDM845_SLAVE_A2NOC_SNOC },
134};
135
136static struct qcom_icc_node qxm_ipa = {
137 .name = "qxm_ipa",
138 .id = SDM845_MASTER_IPA,
139 .channels = 1,
140 .buswidth = 8,
141 .num_links = 1,
142 .links = { SDM845_SLAVE_A2NOC_SNOC },
143};
144
145static struct qcom_icc_node xm_pcie3_1 = {
146 .name = "xm_pcie3_1",
147 .id = SDM845_MASTER_PCIE_1,
148 .channels = 1,
149 .buswidth = 8,
150 .num_links = 1,
151 .links = { SDM845_SLAVE_ANOC_PCIE_SNOC },
152};
153
154static struct qcom_icc_node xm_qdss_etr = {
155 .name = "xm_qdss_etr",
156 .id = SDM845_MASTER_QDSS_ETR,
157 .channels = 1,
158 .buswidth = 8,
159 .num_links = 1,
160 .links = { SDM845_SLAVE_A2NOC_SNOC },
161};
162
163static struct qcom_icc_node xm_usb3_0 = {
164 .name = "xm_usb3_0",
165 .id = SDM845_MASTER_USB3_0,
166 .channels = 1,
167 .buswidth = 8,
168 .num_links = 1,
169 .links = { SDM845_SLAVE_A2NOC_SNOC },
170};
171
172static struct qcom_icc_node xm_usb3_1 = {
173 .name = "xm_usb3_1",
174 .id = SDM845_MASTER_USB3_1,
175 .channels = 1,
176 .buswidth = 8,
177 .num_links = 1,
178 .links = { SDM845_SLAVE_A2NOC_SNOC },
179};
180
181static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
182 .name = "qxm_camnoc_hf0_uncomp",
183 .id = SDM845_MASTER_CAMNOC_HF0_UNCOMP,
184 .channels = 1,
185 .buswidth = 32,
186 .num_links = 1,
187 .links = { SDM845_SLAVE_CAMNOC_UNCOMP },
188};
189
190static struct qcom_icc_node qxm_camnoc_hf1_uncomp = {
191 .name = "qxm_camnoc_hf1_uncomp",
192 .id = SDM845_MASTER_CAMNOC_HF1_UNCOMP,
193 .channels = 1,
194 .buswidth = 32,
195 .num_links = 1,
196 .links = { SDM845_SLAVE_CAMNOC_UNCOMP },
197};
198
199static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
200 .name = "qxm_camnoc_sf_uncomp",
201 .id = SDM845_MASTER_CAMNOC_SF_UNCOMP,
202 .channels = 1,
203 .buswidth = 32,
204 .num_links = 1,
205 .links = { SDM845_SLAVE_CAMNOC_UNCOMP },
206};
207
208static struct qcom_icc_node qhm_spdm = {
209 .name = "qhm_spdm",
210 .id = SDM845_MASTER_SPDM,
211 .channels = 1,
212 .buswidth = 4,
213 .num_links = 1,
214 .links = { SDM845_SLAVE_CNOC_A2NOC },
215};
216
217static struct qcom_icc_node qhm_tic = {
218 .name = "qhm_tic",
219 .id = SDM845_MASTER_TIC,
220 .channels = 1,
221 .buswidth = 4,
222 .num_links = 43,
223 .links = { SDM845_SLAVE_A1NOC_CFG,
224 SDM845_SLAVE_A2NOC_CFG,
225 SDM845_SLAVE_AOP,
226 SDM845_SLAVE_AOSS,
227 SDM845_SLAVE_CAMERA_CFG,
228 SDM845_SLAVE_CLK_CTL,
229 SDM845_SLAVE_CDSP_CFG,
230 SDM845_SLAVE_RBCPR_CX_CFG,
231 SDM845_SLAVE_CRYPTO_0_CFG,
232 SDM845_SLAVE_DCC_CFG,
233 SDM845_SLAVE_CNOC_DDRSS,
234 SDM845_SLAVE_DISPLAY_CFG,
235 SDM845_SLAVE_GLM,
236 SDM845_SLAVE_GFX3D_CFG,
237 SDM845_SLAVE_IMEM_CFG,
238 SDM845_SLAVE_IPA_CFG,
239 SDM845_SLAVE_CNOC_MNOC_CFG,
240 SDM845_SLAVE_PCIE_0_CFG,
241 SDM845_SLAVE_PCIE_1_CFG,
242 SDM845_SLAVE_PDM,
243 SDM845_SLAVE_SOUTH_PHY_CFG,
244 SDM845_SLAVE_PIMEM_CFG,
245 SDM845_SLAVE_PRNG,
246 SDM845_SLAVE_QDSS_CFG,
247 SDM845_SLAVE_BLSP_2,
248 SDM845_SLAVE_BLSP_1,
249 SDM845_SLAVE_SDCC_2,
250 SDM845_SLAVE_SDCC_4,
251 SDM845_SLAVE_SNOC_CFG,
252 SDM845_SLAVE_SPDM_WRAPPER,
253 SDM845_SLAVE_SPSS_CFG,
254 SDM845_SLAVE_TCSR,
255 SDM845_SLAVE_TLMM_NORTH,
256 SDM845_SLAVE_TLMM_SOUTH,
257 SDM845_SLAVE_TSIF,
258 SDM845_SLAVE_UFS_CARD_CFG,
259 SDM845_SLAVE_UFS_MEM_CFG,
260 SDM845_SLAVE_USB3_0,
261 SDM845_SLAVE_USB3_1,
262 SDM845_SLAVE_VENUS_CFG,
263 SDM845_SLAVE_VSENSE_CTRL_CFG,
264 SDM845_SLAVE_CNOC_A2NOC,
265 SDM845_SLAVE_SERVICE_CNOC
266 },
267};
268
269static struct qcom_icc_node qnm_snoc = {
270 .name = "qnm_snoc",
271 .id = SDM845_MASTER_SNOC_CNOC,
272 .channels = 1,
273 .buswidth = 8,
274 .num_links = 42,
275 .links = { SDM845_SLAVE_A1NOC_CFG,
276 SDM845_SLAVE_A2NOC_CFG,
277 SDM845_SLAVE_AOP,
278 SDM845_SLAVE_AOSS,
279 SDM845_SLAVE_CAMERA_CFG,
280 SDM845_SLAVE_CLK_CTL,
281 SDM845_SLAVE_CDSP_CFG,
282 SDM845_SLAVE_RBCPR_CX_CFG,
283 SDM845_SLAVE_CRYPTO_0_CFG,
284 SDM845_SLAVE_DCC_CFG,
285 SDM845_SLAVE_CNOC_DDRSS,
286 SDM845_SLAVE_DISPLAY_CFG,
287 SDM845_SLAVE_GLM,
288 SDM845_SLAVE_GFX3D_CFG,
289 SDM845_SLAVE_IMEM_CFG,
290 SDM845_SLAVE_IPA_CFG,
291 SDM845_SLAVE_CNOC_MNOC_CFG,
292 SDM845_SLAVE_PCIE_0_CFG,
293 SDM845_SLAVE_PCIE_1_CFG,
294 SDM845_SLAVE_PDM,
295 SDM845_SLAVE_SOUTH_PHY_CFG,
296 SDM845_SLAVE_PIMEM_CFG,
297 SDM845_SLAVE_PRNG,
298 SDM845_SLAVE_QDSS_CFG,
299 SDM845_SLAVE_BLSP_2,
300 SDM845_SLAVE_BLSP_1,
301 SDM845_SLAVE_SDCC_2,
302 SDM845_SLAVE_SDCC_4,
303 SDM845_SLAVE_SNOC_CFG,
304 SDM845_SLAVE_SPDM_WRAPPER,
305 SDM845_SLAVE_SPSS_CFG,
306 SDM845_SLAVE_TCSR,
307 SDM845_SLAVE_TLMM_NORTH,
308 SDM845_SLAVE_TLMM_SOUTH,
309 SDM845_SLAVE_TSIF,
310 SDM845_SLAVE_UFS_CARD_CFG,
311 SDM845_SLAVE_UFS_MEM_CFG,
312 SDM845_SLAVE_USB3_0,
313 SDM845_SLAVE_USB3_1,
314 SDM845_SLAVE_VENUS_CFG,
315 SDM845_SLAVE_VSENSE_CTRL_CFG,
316 SDM845_SLAVE_SERVICE_CNOC
317 },
318};
319
320static struct qcom_icc_node xm_qdss_dap = {
321 .name = "xm_qdss_dap",
322 .id = SDM845_MASTER_QDSS_DAP,
323 .channels = 1,
324 .buswidth = 8,
325 .num_links = 43,
326 .links = { SDM845_SLAVE_A1NOC_CFG,
327 SDM845_SLAVE_A2NOC_CFG,
328 SDM845_SLAVE_AOP,
329 SDM845_SLAVE_AOSS,
330 SDM845_SLAVE_CAMERA_CFG,
331 SDM845_SLAVE_CLK_CTL,
332 SDM845_SLAVE_CDSP_CFG,
333 SDM845_SLAVE_RBCPR_CX_CFG,
334 SDM845_SLAVE_CRYPTO_0_CFG,
335 SDM845_SLAVE_DCC_CFG,
336 SDM845_SLAVE_CNOC_DDRSS,
337 SDM845_SLAVE_DISPLAY_CFG,
338 SDM845_SLAVE_GLM,
339 SDM845_SLAVE_GFX3D_CFG,
340 SDM845_SLAVE_IMEM_CFG,
341 SDM845_SLAVE_IPA_CFG,
342 SDM845_SLAVE_CNOC_MNOC_CFG,
343 SDM845_SLAVE_PCIE_0_CFG,
344 SDM845_SLAVE_PCIE_1_CFG,
345 SDM845_SLAVE_PDM,
346 SDM845_SLAVE_SOUTH_PHY_CFG,
347 SDM845_SLAVE_PIMEM_CFG,
348 SDM845_SLAVE_PRNG,
349 SDM845_SLAVE_QDSS_CFG,
350 SDM845_SLAVE_BLSP_2,
351 SDM845_SLAVE_BLSP_1,
352 SDM845_SLAVE_SDCC_2,
353 SDM845_SLAVE_SDCC_4,
354 SDM845_SLAVE_SNOC_CFG,
355 SDM845_SLAVE_SPDM_WRAPPER,
356 SDM845_SLAVE_SPSS_CFG,
357 SDM845_SLAVE_TCSR,
358 SDM845_SLAVE_TLMM_NORTH,
359 SDM845_SLAVE_TLMM_SOUTH,
360 SDM845_SLAVE_TSIF,
361 SDM845_SLAVE_UFS_CARD_CFG,
362 SDM845_SLAVE_UFS_MEM_CFG,
363 SDM845_SLAVE_USB3_0,
364 SDM845_SLAVE_USB3_1,
365 SDM845_SLAVE_VENUS_CFG,
366 SDM845_SLAVE_VSENSE_CTRL_CFG,
367 SDM845_SLAVE_CNOC_A2NOC,
368 SDM845_SLAVE_SERVICE_CNOC
369 },
370};
371
372static struct qcom_icc_node qhm_cnoc = {
373 .name = "qhm_cnoc",
374 .id = SDM845_MASTER_CNOC_DC_NOC,
375 .channels = 1,
376 .buswidth = 4,
377 .num_links = 2,
378 .links = { SDM845_SLAVE_LLCC_CFG,
379 SDM845_SLAVE_MEM_NOC_CFG
380 },
381};
382
383static struct qcom_icc_node acm_l3 = {
384 .name = "acm_l3",
385 .id = SDM845_MASTER_APPSS_PROC,
386 .channels = 1,
387 .buswidth = 16,
388 .num_links = 3,
389 .links = { SDM845_SLAVE_GNOC_SNOC,
390 SDM845_SLAVE_GNOC_MEM_NOC,
391 SDM845_SLAVE_SERVICE_GNOC
392 },
393};
394
395static struct qcom_icc_node pm_gnoc_cfg = {
396 .name = "pm_gnoc_cfg",
397 .id = SDM845_MASTER_GNOC_CFG,
398 .channels = 1,
399 .buswidth = 4,
400 .num_links = 1,
401 .links = { SDM845_SLAVE_SERVICE_GNOC },
402};
403
404static struct qcom_icc_node llcc_mc = {
405 .name = "llcc_mc",
406 .id = SDM845_MASTER_LLCC,
407 .channels = 4,
408 .buswidth = 4,
409 .num_links = 1,
410 .links = { SDM845_SLAVE_EBI1 },
411};
412
413static struct qcom_icc_node acm_tcu = {
414 .name = "acm_tcu",
415 .id = SDM845_MASTER_TCU_0,
416 .channels = 1,
417 .buswidth = 8,
418 .num_links = 3,
419 .links = { SDM845_SLAVE_MEM_NOC_GNOC,
420 SDM845_SLAVE_LLCC,
421 SDM845_SLAVE_MEM_NOC_SNOC
422 },
423};
424
425static struct qcom_icc_node qhm_memnoc_cfg = {
426 .name = "qhm_memnoc_cfg",
427 .id = SDM845_MASTER_MEM_NOC_CFG,
428 .channels = 1,
429 .buswidth = 4,
430 .num_links = 2,
431 .links = { SDM845_SLAVE_MSS_PROC_MS_MPU_CFG,
432 SDM845_SLAVE_SERVICE_MEM_NOC
433 },
434};
435
436static struct qcom_icc_node qnm_apps = {
437 .name = "qnm_apps",
438 .id = SDM845_MASTER_GNOC_MEM_NOC,
439 .channels = 2,
440 .buswidth = 32,
441 .num_links = 1,
442 .links = { SDM845_SLAVE_LLCC },
443};
444
445static struct qcom_icc_node qnm_mnoc_hf = {
446 .name = "qnm_mnoc_hf",
447 .id = SDM845_MASTER_MNOC_HF_MEM_NOC,
448 .channels = 2,
449 .buswidth = 32,
450 .num_links = 2,
451 .links = { SDM845_SLAVE_MEM_NOC_GNOC,
452 SDM845_SLAVE_LLCC
453 },
454};
455
456static struct qcom_icc_node qnm_mnoc_sf = {
457 .name = "qnm_mnoc_sf",
458 .id = SDM845_MASTER_MNOC_SF_MEM_NOC,
459 .channels = 1,
460 .buswidth = 32,
461 .num_links = 3,
462 .links = { SDM845_SLAVE_MEM_NOC_GNOC,
463 SDM845_SLAVE_LLCC,
464 SDM845_SLAVE_MEM_NOC_SNOC
465 },
466};
467
468static struct qcom_icc_node qnm_snoc_gc = {
469 .name = "qnm_snoc_gc",
470 .id = SDM845_MASTER_SNOC_GC_MEM_NOC,
471 .channels = 1,
472 .buswidth = 8,
473 .num_links = 1,
474 .links = { SDM845_SLAVE_LLCC },
475};
476
477static struct qcom_icc_node qnm_snoc_sf = {
478 .name = "qnm_snoc_sf",
479 .id = SDM845_MASTER_SNOC_SF_MEM_NOC,
480 .channels = 1,
481 .buswidth = 16,
482 .num_links = 2,
483 .links = { SDM845_SLAVE_MEM_NOC_GNOC,
484 SDM845_SLAVE_LLCC
485 },
486};
487
488static struct qcom_icc_node qxm_gpu = {
489 .name = "qxm_gpu",
490 .id = SDM845_MASTER_GFX3D,
491 .channels = 2,
492 .buswidth = 32,
493 .num_links = 3,
494 .links = { SDM845_SLAVE_MEM_NOC_GNOC,
495 SDM845_SLAVE_LLCC,
496 SDM845_SLAVE_MEM_NOC_SNOC
497 },
498};
499
500static struct qcom_icc_node qhm_mnoc_cfg = {
501 .name = "qhm_mnoc_cfg",
502 .id = SDM845_MASTER_CNOC_MNOC_CFG,
503 .channels = 1,
504 .buswidth = 4,
505 .num_links = 1,
506 .links = { SDM845_SLAVE_SERVICE_MNOC },
507};
508
509static struct qcom_icc_node qxm_camnoc_hf0 = {
510 .name = "qxm_camnoc_hf0",
511 .id = SDM845_MASTER_CAMNOC_HF0,
512 .channels = 1,
513 .buswidth = 32,
514 .num_links = 1,
515 .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC },
516};
517
518static struct qcom_icc_node qxm_camnoc_hf1 = {
519 .name = "qxm_camnoc_hf1",
520 .id = SDM845_MASTER_CAMNOC_HF1,
521 .channels = 1,
522 .buswidth = 32,
523 .num_links = 1,
524 .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC },
525};
526
527static struct qcom_icc_node qxm_camnoc_sf = {
528 .name = "qxm_camnoc_sf",
529 .id = SDM845_MASTER_CAMNOC_SF,
530 .channels = 1,
531 .buswidth = 32,
532 .num_links = 1,
533 .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
534};
535
536static struct qcom_icc_node qxm_mdp0 = {
537 .name = "qxm_mdp0",
538 .id = SDM845_MASTER_MDP0,
539 .channels = 1,
540 .buswidth = 32,
541 .num_links = 1,
542 .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC },
543};
544
545static struct qcom_icc_node qxm_mdp1 = {
546 .name = "qxm_mdp1",
547 .id = SDM845_MASTER_MDP1,
548 .channels = 1,
549 .buswidth = 32,
550 .num_links = 1,
551 .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC },
552};
553
554static struct qcom_icc_node qxm_rot = {
555 .name = "qxm_rot",
556 .id = SDM845_MASTER_ROTATOR,
557 .channels = 1,
558 .buswidth = 32,
559 .num_links = 1,
560 .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
561};
562
563static struct qcom_icc_node qxm_venus0 = {
564 .name = "qxm_venus0",
565 .id = SDM845_MASTER_VIDEO_P0,
566 .channels = 1,
567 .buswidth = 32,
568 .num_links = 1,
569 .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
570};
571
572static struct qcom_icc_node qxm_venus1 = {
573 .name = "qxm_venus1",
574 .id = SDM845_MASTER_VIDEO_P1,
575 .channels = 1,
576 .buswidth = 32,
577 .num_links = 1,
578 .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
579};
580
581static struct qcom_icc_node qxm_venus_arm9 = {
582 .name = "qxm_venus_arm9",
583 .id = SDM845_MASTER_VIDEO_PROC,
584 .channels = 1,
585 .buswidth = 8,
586 .num_links = 1,
587 .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC },
588};
589
590static struct qcom_icc_node qhm_snoc_cfg = {
591 .name = "qhm_snoc_cfg",
592 .id = SDM845_MASTER_SNOC_CFG,
593 .channels = 1,
594 .buswidth = 4,
595 .num_links = 1,
596 .links = { SDM845_SLAVE_SERVICE_SNOC },
597};
598
599static struct qcom_icc_node qnm_aggre1_noc = {
600 .name = "qnm_aggre1_noc",
601 .id = SDM845_MASTER_A1NOC_SNOC,
602 .channels = 1,
603 .buswidth = 16,
604 .num_links = 6,
605 .links = { SDM845_SLAVE_APPSS,
606 SDM845_SLAVE_SNOC_CNOC,
607 SDM845_SLAVE_SNOC_MEM_NOC_SF,
608 SDM845_SLAVE_IMEM,
609 SDM845_SLAVE_PIMEM,
610 SDM845_SLAVE_QDSS_STM
611 },
612};
613
614static struct qcom_icc_node qnm_aggre2_noc = {
615 .name = "qnm_aggre2_noc",
616 .id = SDM845_MASTER_A2NOC_SNOC,
617 .channels = 1,
618 .buswidth = 16,
619 .num_links = 9,
620 .links = { SDM845_SLAVE_APPSS,
621 SDM845_SLAVE_SNOC_CNOC,
622 SDM845_SLAVE_SNOC_MEM_NOC_SF,
623 SDM845_SLAVE_IMEM,
624 SDM845_SLAVE_PCIE_0,
625 SDM845_SLAVE_PCIE_1,
626 SDM845_SLAVE_PIMEM,
627 SDM845_SLAVE_QDSS_STM,
628 SDM845_SLAVE_TCU
629 },
630};
631
632static struct qcom_icc_node qnm_gladiator_sodv = {
633 .name = "qnm_gladiator_sodv",
634 .id = SDM845_MASTER_GNOC_SNOC,
635 .channels = 1,
636 .buswidth = 8,
637 .num_links = 8,
638 .links = { SDM845_SLAVE_APPSS,
639 SDM845_SLAVE_SNOC_CNOC,
640 SDM845_SLAVE_IMEM,
641 SDM845_SLAVE_PCIE_0,
642 SDM845_SLAVE_PCIE_1,
643 SDM845_SLAVE_PIMEM,
644 SDM845_SLAVE_QDSS_STM,
645 SDM845_SLAVE_TCU
646 },
647};
648
649static struct qcom_icc_node qnm_memnoc = {
650 .name = "qnm_memnoc",
651 .id = SDM845_MASTER_MEM_NOC_SNOC,
652 .channels = 1,
653 .buswidth = 8,
654 .num_links = 5,
655 .links = { SDM845_SLAVE_APPSS,
656 SDM845_SLAVE_SNOC_CNOC,
657 SDM845_SLAVE_IMEM,
658 SDM845_SLAVE_PIMEM,
659 SDM845_SLAVE_QDSS_STM
660 },
661};
662
663static struct qcom_icc_node qnm_pcie_anoc = {
664 .name = "qnm_pcie_anoc",
665 .id = SDM845_MASTER_ANOC_PCIE_SNOC,
666 .channels = 1,
667 .buswidth = 16,
668 .num_links = 5,
669 .links = { SDM845_SLAVE_APPSS,
670 SDM845_SLAVE_SNOC_CNOC,
671 SDM845_SLAVE_SNOC_MEM_NOC_SF,
672 SDM845_SLAVE_IMEM,
673 SDM845_SLAVE_QDSS_STM
674 },
675};
676
677static struct qcom_icc_node qxm_pimem = {
678 .name = "qxm_pimem",
679 .id = SDM845_MASTER_PIMEM,
680 .channels = 1,
681 .buswidth = 8,
682 .num_links = 2,
683 .links = { SDM845_SLAVE_SNOC_MEM_NOC_GC,
684 SDM845_SLAVE_IMEM
685 },
686};
687
688static struct qcom_icc_node xm_gic = {
689 .name = "xm_gic",
690 .id = SDM845_MASTER_GIC,
691 .channels = 1,
692 .buswidth = 8,
693 .num_links = 2,
694 .links = { SDM845_SLAVE_SNOC_MEM_NOC_GC,
695 SDM845_SLAVE_IMEM
696 },
697};
698
699static struct qcom_icc_node qns_a1noc_snoc = {
700 .name = "qns_a1noc_snoc",
701 .id = SDM845_SLAVE_A1NOC_SNOC,
702 .channels = 1,
703 .buswidth = 16,
704 .num_links = 1,
705 .links = { SDM845_MASTER_A1NOC_SNOC },
706};
707
708static struct qcom_icc_node srvc_aggre1_noc = {
709 .name = "srvc_aggre1_noc",
710 .id = SDM845_SLAVE_SERVICE_A1NOC,
711 .channels = 1,
712 .buswidth = 4,
713 .num_links = 1,
714 .links = { 0 },
715};
716
717static struct qcom_icc_node qns_pcie_a1noc_snoc = {
718 .name = "qns_pcie_a1noc_snoc",
719 .id = SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC,
720 .channels = 1,
721 .buswidth = 16,
722 .num_links = 1,
723 .links = { SDM845_MASTER_ANOC_PCIE_SNOC },
724};
725
726static struct qcom_icc_node qns_a2noc_snoc = {
727 .name = "qns_a2noc_snoc",
728 .id = SDM845_SLAVE_A2NOC_SNOC,
729 .channels = 1,
730 .buswidth = 16,
731 .num_links = 1,
732 .links = { SDM845_MASTER_A2NOC_SNOC },
733};
734
735static struct qcom_icc_node qns_pcie_snoc = {
736 .name = "qns_pcie_snoc",
737 .id = SDM845_SLAVE_ANOC_PCIE_SNOC,
738 .channels = 1,
739 .buswidth = 16,
740 .num_links = 1,
741 .links = { SDM845_MASTER_ANOC_PCIE_SNOC },
742};
743
744static struct qcom_icc_node srvc_aggre2_noc = {
745 .name = "srvc_aggre2_noc",
746 .id = SDM845_SLAVE_SERVICE_A2NOC,
747 .channels = 1,
748 .buswidth = 4,
749};
750
751static struct qcom_icc_node qns_camnoc_uncomp = {
752 .name = "qns_camnoc_uncomp",
753 .id = SDM845_SLAVE_CAMNOC_UNCOMP,
754 .channels = 1,
755 .buswidth = 32,
756};
757
758static struct qcom_icc_node qhs_a1_noc_cfg = {
759 .name = "qhs_a1_noc_cfg",
760 .id = SDM845_SLAVE_A1NOC_CFG,
761 .channels = 1,
762 .buswidth = 4,
763 .num_links = 1,
764 .links = { SDM845_MASTER_A1NOC_CFG },
765};
766
767static struct qcom_icc_node qhs_a2_noc_cfg = {
768 .name = "qhs_a2_noc_cfg",
769 .id = SDM845_SLAVE_A2NOC_CFG,
770 .channels = 1,
771 .buswidth = 4,
772 .num_links = 1,
773 .links = { SDM845_MASTER_A2NOC_CFG },
774};
775
776static struct qcom_icc_node qhs_aop = {
777 .name = "qhs_aop",
778 .id = SDM845_SLAVE_AOP,
779 .channels = 1,
780 .buswidth = 4,
781};
782
783static struct qcom_icc_node qhs_aoss = {
784 .name = "qhs_aoss",
785 .id = SDM845_SLAVE_AOSS,
786 .channels = 1,
787 .buswidth = 4,
788};
789
790static struct qcom_icc_node qhs_camera_cfg = {
791 .name = "qhs_camera_cfg",
792 .id = SDM845_SLAVE_CAMERA_CFG,
793 .channels = 1,
794 .buswidth = 4,
795};
796
797static struct qcom_icc_node qhs_clk_ctl = {
798 .name = "qhs_clk_ctl",
799 .id = SDM845_SLAVE_CLK_CTL,
800 .channels = 1,
801 .buswidth = 4,
802};
803
804static struct qcom_icc_node qhs_compute_dsp_cfg = {
805 .name = "qhs_compute_dsp_cfg",
806 .id = SDM845_SLAVE_CDSP_CFG,
807 .channels = 1,
808 .buswidth = 4,
809};
810
811static struct qcom_icc_node qhs_cpr_cx = {
812 .name = "qhs_cpr_cx",
813 .id = SDM845_SLAVE_RBCPR_CX_CFG,
814 .channels = 1,
815 .buswidth = 4,
816};
817
818static struct qcom_icc_node qhs_crypto0_cfg = {
819 .name = "qhs_crypto0_cfg",
820 .id = SDM845_SLAVE_CRYPTO_0_CFG,
821 .channels = 1,
822 .buswidth = 4,
823};
824
825static struct qcom_icc_node qhs_dcc_cfg = {
826 .name = "qhs_dcc_cfg",
827 .id = SDM845_SLAVE_DCC_CFG,
828 .channels = 1,
829 .buswidth = 4,
830 .num_links = 1,
831 .links = { SDM845_MASTER_CNOC_DC_NOC },
832};
833
834static struct qcom_icc_node qhs_ddrss_cfg = {
835 .name = "qhs_ddrss_cfg",
836 .id = SDM845_SLAVE_CNOC_DDRSS,
837 .channels = 1,
838 .buswidth = 4,
839};
840
841static struct qcom_icc_node qhs_display_cfg = {
842 .name = "qhs_display_cfg",
843 .id = SDM845_SLAVE_DISPLAY_CFG,
844 .channels = 1,
845 .buswidth = 4,
846};
847
848static struct qcom_icc_node qhs_glm = {
849 .name = "qhs_glm",
850 .id = SDM845_SLAVE_GLM,
851 .channels = 1,
852 .buswidth = 4,
853};
854
855static struct qcom_icc_node qhs_gpuss_cfg = {
856 .name = "qhs_gpuss_cfg",
857 .id = SDM845_SLAVE_GFX3D_CFG,
858 .channels = 1,
859 .buswidth = 8,
860};
861
862static struct qcom_icc_node qhs_imem_cfg = {
863 .name = "qhs_imem_cfg",
864 .id = SDM845_SLAVE_IMEM_CFG,
865 .channels = 1,
866 .buswidth = 4,
867};
868
869static struct qcom_icc_node qhs_ipa = {
870 .name = "qhs_ipa",
871 .id = SDM845_SLAVE_IPA_CFG,
872 .channels = 1,
873 .buswidth = 4,
874};
875
876static struct qcom_icc_node qhs_mnoc_cfg = {
877 .name = "qhs_mnoc_cfg",
878 .id = SDM845_SLAVE_CNOC_MNOC_CFG,
879 .channels = 1,
880 .buswidth = 4,
881 .num_links = 1,
882 .links = { SDM845_MASTER_CNOC_MNOC_CFG },
883};
884
885static struct qcom_icc_node qhs_pcie0_cfg = {
886 .name = "qhs_pcie0_cfg",
887 .id = SDM845_SLAVE_PCIE_0_CFG,
888 .channels = 1,
889 .buswidth = 4,
890};
891
892static struct qcom_icc_node qhs_pcie_gen3_cfg = {
893 .name = "qhs_pcie_gen3_cfg",
894 .id = SDM845_SLAVE_PCIE_1_CFG,
895 .channels = 1,
896 .buswidth = 4,
897};
898
899static struct qcom_icc_node qhs_pdm = {
900 .name = "qhs_pdm",
901 .id = SDM845_SLAVE_PDM,
902 .channels = 1,
903 .buswidth = 4,
904};
905
906static struct qcom_icc_node qhs_phy_refgen_south = {
907 .name = "qhs_phy_refgen_south",
908 .id = SDM845_SLAVE_SOUTH_PHY_CFG,
909 .channels = 1,
910 .buswidth = 4,
911};
912
913static struct qcom_icc_node qhs_pimem_cfg = {
914 .name = "qhs_pimem_cfg",
915 .id = SDM845_SLAVE_PIMEM_CFG,
916 .channels = 1,
917 .buswidth = 4,
918};
919
920static struct qcom_icc_node qhs_prng = {
921 .name = "qhs_prng",
922 .id = SDM845_SLAVE_PRNG,
923 .channels = 1,
924 .buswidth = 4,
925};
926
927static struct qcom_icc_node qhs_qdss_cfg = {
928 .name = "qhs_qdss_cfg",
929 .id = SDM845_SLAVE_QDSS_CFG,
930 .channels = 1,
931 .buswidth = 4,
932};
933
934static struct qcom_icc_node qhs_qupv3_north = {
935 .name = "qhs_qupv3_north",
936 .id = SDM845_SLAVE_BLSP_2,
937 .channels = 1,
938 .buswidth = 4,
939};
940
941static struct qcom_icc_node qhs_qupv3_south = {
942 .name = "qhs_qupv3_south",
943 .id = SDM845_SLAVE_BLSP_1,
944 .channels = 1,
945 .buswidth = 4,
946};
947
948static struct qcom_icc_node qhs_sdc2 = {
949 .name = "qhs_sdc2",
950 .id = SDM845_SLAVE_SDCC_2,
951 .channels = 1,
952 .buswidth = 4,
953};
954
955static struct qcom_icc_node qhs_sdc4 = {
956 .name = "qhs_sdc4",
957 .id = SDM845_SLAVE_SDCC_4,
958 .channels = 1,
959 .buswidth = 4,
960};
961
962static struct qcom_icc_node qhs_snoc_cfg = {
963 .name = "qhs_snoc_cfg",
964 .id = SDM845_SLAVE_SNOC_CFG,
965 .channels = 1,
966 .buswidth = 4,
967 .num_links = 1,
968 .links = { SDM845_MASTER_SNOC_CFG },
969};
970
971static struct qcom_icc_node qhs_spdm = {
972 .name = "qhs_spdm",
973 .id = SDM845_SLAVE_SPDM_WRAPPER,
974 .channels = 1,
975 .buswidth = 4,
976};
977
978static struct qcom_icc_node qhs_spss_cfg = {
979 .name = "qhs_spss_cfg",
980 .id = SDM845_SLAVE_SPSS_CFG,
981 .channels = 1,
982 .buswidth = 4,
983};
984
985static struct qcom_icc_node qhs_tcsr = {
986 .name = "qhs_tcsr",
987 .id = SDM845_SLAVE_TCSR,
988 .channels = 1,
989 .buswidth = 4,
990};
991
992static struct qcom_icc_node qhs_tlmm_north = {
993 .name = "qhs_tlmm_north",
994 .id = SDM845_SLAVE_TLMM_NORTH,
995 .channels = 1,
996 .buswidth = 4,
997};
998
999static struct qcom_icc_node qhs_tlmm_south = {
1000 .name = "qhs_tlmm_south",
1001 .id = SDM845_SLAVE_TLMM_SOUTH,
1002 .channels = 1,
1003 .buswidth = 4,
1004};
1005
1006static struct qcom_icc_node qhs_tsif = {
1007 .name = "qhs_tsif",
1008 .id = SDM845_SLAVE_TSIF,
1009 .channels = 1,
1010 .buswidth = 4,
1011};
1012
1013static struct qcom_icc_node qhs_ufs_card_cfg = {
1014 .name = "qhs_ufs_card_cfg",
1015 .id = SDM845_SLAVE_UFS_CARD_CFG,
1016 .channels = 1,
1017 .buswidth = 4,
1018};
1019
1020static struct qcom_icc_node qhs_ufs_mem_cfg = {
1021 .name = "qhs_ufs_mem_cfg",
1022 .id = SDM845_SLAVE_UFS_MEM_CFG,
1023 .channels = 1,
1024 .buswidth = 4,
1025};
1026
1027static struct qcom_icc_node qhs_usb3_0 = {
1028 .name = "qhs_usb3_0",
1029 .id = SDM845_SLAVE_USB3_0,
1030 .channels = 1,
1031 .buswidth = 4,
1032};
1033
1034static struct qcom_icc_node qhs_usb3_1 = {
1035 .name = "qhs_usb3_1",
1036 .id = SDM845_SLAVE_USB3_1,
1037 .channels = 1,
1038 .buswidth = 4,
1039};
1040
1041static struct qcom_icc_node qhs_venus_cfg = {
1042 .name = "qhs_venus_cfg",
1043 .id = SDM845_SLAVE_VENUS_CFG,
1044 .channels = 1,
1045 .buswidth = 4,
1046};
1047
1048static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1049 .name = "qhs_vsense_ctrl_cfg",
1050 .id = SDM845_SLAVE_VSENSE_CTRL_CFG,
1051 .channels = 1,
1052 .buswidth = 4,
1053};
1054
1055static struct qcom_icc_node qns_cnoc_a2noc = {
1056 .name = "qns_cnoc_a2noc",
1057 .id = SDM845_SLAVE_CNOC_A2NOC,
1058 .channels = 1,
1059 .buswidth = 8,
1060 .num_links = 1,
1061 .links = { SDM845_MASTER_CNOC_A2NOC },
1062};
1063
1064static struct qcom_icc_node srvc_cnoc = {
1065 .name = "srvc_cnoc",
1066 .id = SDM845_SLAVE_SERVICE_CNOC,
1067 .channels = 1,
1068 .buswidth = 4,
1069};
1070
1071static struct qcom_icc_node qhs_llcc = {
1072 .name = "qhs_llcc",
1073 .id = SDM845_SLAVE_LLCC_CFG,
1074 .channels = 1,
1075 .buswidth = 4,
1076};
1077
1078static struct qcom_icc_node qhs_memnoc = {
1079 .name = "qhs_memnoc",
1080 .id = SDM845_SLAVE_MEM_NOC_CFG,
1081 .channels = 1,
1082 .buswidth = 4,
1083 .num_links = 1,
1084 .links = { SDM845_MASTER_MEM_NOC_CFG },
1085};
1086
1087static struct qcom_icc_node qns_gladiator_sodv = {
1088 .name = "qns_gladiator_sodv",
1089 .id = SDM845_SLAVE_GNOC_SNOC,
1090 .channels = 1,
1091 .buswidth = 8,
1092 .num_links = 1,
1093 .links = { SDM845_MASTER_GNOC_SNOC },
1094};
1095
1096static struct qcom_icc_node qns_gnoc_memnoc = {
1097 .name = "qns_gnoc_memnoc",
1098 .id = SDM845_SLAVE_GNOC_MEM_NOC,
1099 .channels = 2,
1100 .buswidth = 32,
1101 .num_links = 1,
1102 .links = { SDM845_MASTER_GNOC_MEM_NOC },
1103};
1104
1105static struct qcom_icc_node srvc_gnoc = {
1106 .name = "srvc_gnoc",
1107 .id = SDM845_SLAVE_SERVICE_GNOC,
1108 .channels = 1,
1109 .buswidth = 4,
1110};
1111
1112static struct qcom_icc_node ebi = {
1113 .name = "ebi",
1114 .id = SDM845_SLAVE_EBI1,
1115 .channels = 4,
1116 .buswidth = 4,
1117};
1118
1119static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1120 .name = "qhs_mdsp_ms_mpu_cfg",
1121 .id = SDM845_SLAVE_MSS_PROC_MS_MPU_CFG,
1122 .channels = 1,
1123 .buswidth = 4,
1124};
1125
1126static struct qcom_icc_node qns_apps_io = {
1127 .name = "qns_apps_io",
1128 .id = SDM845_SLAVE_MEM_NOC_GNOC,
1129 .channels = 1,
1130 .buswidth = 32,
1131};
1132
1133static struct qcom_icc_node qns_llcc = {
1134 .name = "qns_llcc",
1135 .id = SDM845_SLAVE_LLCC,
1136 .channels = 4,
1137 .buswidth = 16,
1138 .num_links = 1,
1139 .links = { SDM845_MASTER_LLCC },
1140};
1141
1142static struct qcom_icc_node qns_memnoc_snoc = {
1143 .name = "qns_memnoc_snoc",
1144 .id = SDM845_SLAVE_MEM_NOC_SNOC,
1145 .channels = 1,
1146 .buswidth = 8,
1147 .num_links = 1,
1148 .links = { SDM845_MASTER_MEM_NOC_SNOC },
1149};
1150
1151static struct qcom_icc_node srvc_memnoc = {
1152 .name = "srvc_memnoc",
1153 .id = SDM845_SLAVE_SERVICE_MEM_NOC,
1154 .channels = 1,
1155 .buswidth = 4,
1156};
1157
1158static struct qcom_icc_node qns2_mem_noc = {
1159 .name = "qns2_mem_noc",
1160 .id = SDM845_SLAVE_MNOC_SF_MEM_NOC,
1161 .channels = 1,
1162 .buswidth = 32,
1163 .num_links = 1,
1164 .links = { SDM845_MASTER_MNOC_SF_MEM_NOC },
1165};
1166
1167static struct qcom_icc_node qns_mem_noc_hf = {
1168 .name = "qns_mem_noc_hf",
1169 .id = SDM845_SLAVE_MNOC_HF_MEM_NOC,
1170 .channels = 2,
1171 .buswidth = 32,
1172 .num_links = 1,
1173 .links = { SDM845_MASTER_MNOC_HF_MEM_NOC },
1174};
1175
1176static struct qcom_icc_node srvc_mnoc = {
1177 .name = "srvc_mnoc",
1178 .id = SDM845_SLAVE_SERVICE_MNOC,
1179 .channels = 1,
1180 .buswidth = 4,
1181};
1182
1183static struct qcom_icc_node qhs_apss = {
1184 .name = "qhs_apss",
1185 .id = SDM845_SLAVE_APPSS,
1186 .channels = 1,
1187 .buswidth = 8,
1188};
1189
1190static struct qcom_icc_node qns_cnoc = {
1191 .name = "qns_cnoc",
1192 .id = SDM845_SLAVE_SNOC_CNOC,
1193 .channels = 1,
1194 .buswidth = 8,
1195 .num_links = 1,
1196 .links = { SDM845_MASTER_SNOC_CNOC },
1197};
1198
1199static struct qcom_icc_node qns_memnoc_gc = {
1200 .name = "qns_memnoc_gc",
1201 .id = SDM845_SLAVE_SNOC_MEM_NOC_GC,
1202 .channels = 1,
1203 .buswidth = 8,
1204 .num_links = 1,
1205 .links = { SDM845_MASTER_SNOC_GC_MEM_NOC },
1206};
1207
1208static struct qcom_icc_node qns_memnoc_sf = {
1209 .name = "qns_memnoc_sf",
1210 .id = SDM845_SLAVE_SNOC_MEM_NOC_SF,
1211 .channels = 1,
1212 .buswidth = 16,
1213 .num_links = 1,
1214 .links = { SDM845_MASTER_SNOC_SF_MEM_NOC },
1215};
1216
1217static struct qcom_icc_node qxs_imem = {
1218 .name = "qxs_imem",
1219 .id = SDM845_SLAVE_IMEM,
1220 .channels = 1,
1221 .buswidth = 8,
1222};
1223
1224static struct qcom_icc_node qxs_pcie = {
1225 .name = "qxs_pcie",
1226 .id = SDM845_SLAVE_PCIE_0,
1227 .channels = 1,
1228 .buswidth = 8,
1229};
1230
1231static struct qcom_icc_node qxs_pcie_gen3 = {
1232 .name = "qxs_pcie_gen3",
1233 .id = SDM845_SLAVE_PCIE_1,
1234 .channels = 1,
1235 .buswidth = 8,
1236};
1237
1238static struct qcom_icc_node qxs_pimem = {
1239 .name = "qxs_pimem",
1240 .id = SDM845_SLAVE_PIMEM,
1241 .channels = 1,
1242 .buswidth = 8,
1243};
1244
1245static struct qcom_icc_node srvc_snoc = {
1246 .name = "srvc_snoc",
1247 .id = SDM845_SLAVE_SERVICE_SNOC,
1248 .channels = 1,
1249 .buswidth = 4,
1250};
1251
1252static struct qcom_icc_node xs_qdss_stm = {
1253 .name = "xs_qdss_stm",
1254 .id = SDM845_SLAVE_QDSS_STM,
1255 .channels = 1,
1256 .buswidth = 4,
1257};
1258
1259static struct qcom_icc_node xs_sys_tcu_cfg = {
1260 .name = "xs_sys_tcu_cfg",
1261 .id = SDM845_SLAVE_TCU,
1262 .channels = 1,
1263 .buswidth = 8,
1264};
1265
1266static struct qcom_icc_bcm bcm_acv = {
1267 .name = "ACV",
1268 .enable_mask = BIT(3),
1269 .keepalive = false,
1270 .num_nodes = 1,
1271 .nodes = { &ebi },
1272};
1273
1274static struct qcom_icc_bcm bcm_mc0 = {
1275 .name = "MC0",
1276 .keepalive = true,
1277 .num_nodes = 1,
1278 .nodes = { &ebi },
1279};
1280
1281static struct qcom_icc_bcm bcm_sh0 = {
1282 .name = "SH0",
1283 .keepalive = true,
1284 .num_nodes = 1,
1285 .nodes = { &qns_llcc },
1286};
1287
1288static struct qcom_icc_bcm bcm_mm0 = {
1289 .name = "MM0",
1290 .keepalive = false,
1291 .num_nodes = 1,
1292 .nodes = { &qns_mem_noc_hf },
1293};
1294
1295static struct qcom_icc_bcm bcm_sh1 = {
1296 .name = "SH1",
1297 .keepalive = false,
1298 .num_nodes = 1,
1299 .nodes = { &qns_apps_io },
1300};
1301
1302static struct qcom_icc_bcm bcm_mm1 = {
1303 .name = "MM1",
1304 .keepalive = true,
1305 .num_nodes = 7,
1306 .nodes = { &qxm_camnoc_hf0_uncomp,
1307 &qxm_camnoc_hf1_uncomp,
1308 &qxm_camnoc_sf_uncomp,
1309 &qxm_camnoc_hf0,
1310 &qxm_camnoc_hf1,
1311 &qxm_mdp0,
1312 &qxm_mdp1
1313 },
1314};
1315
1316static struct qcom_icc_bcm bcm_sh2 = {
1317 .name = "SH2",
1318 .keepalive = false,
1319 .num_nodes = 1,
1320 .nodes = { &qns_memnoc_snoc },
1321};
1322
1323static struct qcom_icc_bcm bcm_mm2 = {
1324 .name = "MM2",
1325 .keepalive = false,
1326 .num_nodes = 1,
1327 .nodes = { &qns2_mem_noc },
1328};
1329
1330static struct qcom_icc_bcm bcm_sh3 = {
1331 .name = "SH3",
1332 .keepalive = false,
1333 .num_nodes = 1,
1334 .nodes = { &acm_tcu },
1335};
1336
1337static struct qcom_icc_bcm bcm_mm3 = {
1338 .name = "MM3",
1339 .keepalive = false,
1340 .num_nodes = 5,
1341 .nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 },
1342};
1343
1344static struct qcom_icc_bcm bcm_sh5 = {
1345 .name = "SH5",
1346 .keepalive = false,
1347 .num_nodes = 1,
1348 .nodes = { &qnm_apps },
1349};
1350
1351static struct qcom_icc_bcm bcm_sn0 = {
1352 .name = "SN0",
1353 .keepalive = true,
1354 .num_nodes = 1,
1355 .nodes = { &qns_memnoc_sf },
1356};
1357
1358static struct qcom_icc_bcm bcm_ce0 = {
1359 .name = "CE0",
1360 .keepalive = false,
1361 .num_nodes = 1,
1362 .nodes = { &qxm_crypto },
1363};
1364
1365static struct qcom_icc_bcm bcm_cn0 = {
1366 .name = "CN0",
1367 .keepalive = false,
1368 .num_nodes = 47,
1369 .nodes = { &qhm_spdm,
1370 &qhm_tic,
1371 &qnm_snoc,
1372 &xm_qdss_dap,
1373 &qhs_a1_noc_cfg,
1374 &qhs_a2_noc_cfg,
1375 &qhs_aop,
1376 &qhs_aoss,
1377 &qhs_camera_cfg,
1378 &qhs_clk_ctl,
1379 &qhs_compute_dsp_cfg,
1380 &qhs_cpr_cx,
1381 &qhs_crypto0_cfg,
1382 &qhs_dcc_cfg,
1383 &qhs_ddrss_cfg,
1384 &qhs_display_cfg,
1385 &qhs_glm,
1386 &qhs_gpuss_cfg,
1387 &qhs_imem_cfg,
1388 &qhs_ipa,
1389 &qhs_mnoc_cfg,
1390 &qhs_pcie0_cfg,
1391 &qhs_pcie_gen3_cfg,
1392 &qhs_pdm,
1393 &qhs_phy_refgen_south,
1394 &qhs_pimem_cfg,
1395 &qhs_prng,
1396 &qhs_qdss_cfg,
1397 &qhs_qupv3_north,
1398 &qhs_qupv3_south,
1399 &qhs_sdc2,
1400 &qhs_sdc4,
1401 &qhs_snoc_cfg,
1402 &qhs_spdm,
1403 &qhs_spss_cfg,
1404 &qhs_tcsr,
1405 &qhs_tlmm_north,
1406 &qhs_tlmm_south,
1407 &qhs_tsif,
1408 &qhs_ufs_card_cfg,
1409 &qhs_ufs_mem_cfg,
1410 &qhs_usb3_0,
1411 &qhs_usb3_1,
1412 &qhs_venus_cfg,
1413 &qhs_vsense_ctrl_cfg,
1414 &qns_cnoc_a2noc,
1415 &srvc_cnoc
1416 },
1417};
1418
1419static struct qcom_icc_bcm bcm_qup0 = {
1420 .name = "QUP0",
1421 .keepalive = false,
1422 .num_nodes = 2,
1423 .nodes = { &qhm_qup1, &qhm_qup2 },
1424};
1425
1426static struct qcom_icc_bcm bcm_sn1 = {
1427 .name = "SN1",
1428 .keepalive = false,
1429 .num_nodes = 1,
1430 .nodes = { &qxs_imem },
1431};
1432
1433static struct qcom_icc_bcm bcm_sn2 = {
1434 .name = "SN2",
1435 .keepalive = false,
1436 .num_nodes = 1,
1437 .nodes = { &qns_memnoc_gc },
1438};
1439
1440static struct qcom_icc_bcm bcm_sn3 = {
1441 .name = "SN3",
1442 .keepalive = false,
1443 .num_nodes = 1,
1444 .nodes = { &qns_cnoc },
1445};
1446
1447static struct qcom_icc_bcm bcm_sn4 = {
1448 .name = "SN4",
1449 .keepalive = false,
1450 .num_nodes = 1,
1451 .nodes = { &qxm_pimem },
1452};
1453
1454static struct qcom_icc_bcm bcm_sn5 = {
1455 .name = "SN5",
1456 .keepalive = false,
1457 .num_nodes = 1,
1458 .nodes = { &xs_qdss_stm },
1459};
1460
1461static struct qcom_icc_bcm bcm_sn6 = {
1462 .name = "SN6",
1463 .keepalive = false,
1464 .num_nodes = 3,
1465 .nodes = { &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg },
1466};
1467
1468static struct qcom_icc_bcm bcm_sn7 = {
1469 .name = "SN7",
1470 .keepalive = false,
1471 .num_nodes = 1,
1472 .nodes = { &qxs_pcie },
1473};
1474
1475static struct qcom_icc_bcm bcm_sn8 = {
1476 .name = "SN8",
1477 .keepalive = false,
1478 .num_nodes = 1,
1479 .nodes = { &qxs_pcie_gen3 },
1480};
1481
1482static struct qcom_icc_bcm bcm_sn9 = {
1483 .name = "SN9",
1484 .keepalive = false,
1485 .num_nodes = 2,
1486 .nodes = { &srvc_aggre1_noc, &qnm_aggre1_noc },
1487};
1488
1489static struct qcom_icc_bcm bcm_sn11 = {
1490 .name = "SN11",
1491 .keepalive = false,
1492 .num_nodes = 2,
1493 .nodes = { &srvc_aggre2_noc, &qnm_aggre2_noc },
1494};
1495
1496static struct qcom_icc_bcm bcm_sn12 = {
1497 .name = "SN12",
1498 .keepalive = false,
1499 .num_nodes = 2,
1500 .nodes = { &qnm_gladiator_sodv, &xm_gic },
1501};
1502
1503static struct qcom_icc_bcm bcm_sn14 = {
1504 .name = "SN14",
1505 .keepalive = false,
1506 .num_nodes = 1,
1507 .nodes = { &qnm_pcie_anoc },
1508};
1509
1510static struct qcom_icc_bcm bcm_sn15 = {
1511 .name = "SN15",
1512 .keepalive = false,
1513 .num_nodes = 1,
1514 .nodes = { &qnm_memnoc },
1515};
1516
1517static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1518 &bcm_sn9,
1519 &bcm_qup0,
1520};
1521
1522static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1523 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
1524 [MASTER_TSIF] = &qhm_tsif,
1525 [MASTER_SDCC_2] = &xm_sdc2,
1526 [MASTER_SDCC_4] = &xm_sdc4,
1527 [MASTER_UFS_CARD] = &xm_ufs_card,
1528 [MASTER_UFS_MEM] = &xm_ufs_mem,
1529 [MASTER_PCIE_0] = &xm_pcie_0,
1530 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1531 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1532 [SLAVE_ANOC_PCIE_A1NOC_SNOC] = &qns_pcie_a1noc_snoc,
1533 [MASTER_QUP_1] = &qhm_qup1,
1534};
1535
1536static const struct qcom_icc_desc sdm845_aggre1_noc = {
1537 .nodes = aggre1_noc_nodes,
1538 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1539 .bcms = aggre1_noc_bcms,
1540 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1541};
1542
1543static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1544 &bcm_ce0,
1545 &bcm_sn11,
1546 &bcm_qup0,
1547};
1548
1549static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1550 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
1551 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1552 [MASTER_CNOC_A2NOC] = &qnm_cnoc,
1553 [MASTER_CRYPTO] = &qxm_crypto,
1554 [MASTER_IPA] = &qxm_ipa,
1555 [MASTER_PCIE_1] = &xm_pcie3_1,
1556 [MASTER_QDSS_ETR] = &xm_qdss_etr,
1557 [MASTER_USB3_0] = &xm_usb3_0,
1558 [MASTER_USB3_1] = &xm_usb3_1,
1559 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1560 [SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc,
1561 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1562 [MASTER_QUP_2] = &qhm_qup2,
1563};
1564
1565static const struct qcom_icc_desc sdm845_aggre2_noc = {
1566 .nodes = aggre2_noc_nodes,
1567 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1568 .bcms = aggre2_noc_bcms,
1569 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1570};
1571
1572static struct qcom_icc_bcm * const config_noc_bcms[] = {
1573 &bcm_cn0,
1574};
1575
1576static struct qcom_icc_node * const config_noc_nodes[] = {
1577 [MASTER_SPDM] = &qhm_spdm,
1578 [MASTER_TIC] = &qhm_tic,
1579 [MASTER_SNOC_CNOC] = &qnm_snoc,
1580 [MASTER_QDSS_DAP] = &xm_qdss_dap,
1581 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
1582 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
1583 [SLAVE_AOP] = &qhs_aop,
1584 [SLAVE_AOSS] = &qhs_aoss,
1585 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1586 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1587 [SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg,
1588 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1589 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1590 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
1591 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
1592 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1593 [SLAVE_GLM] = &qhs_glm,
1594 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1595 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1596 [SLAVE_IPA_CFG] = &qhs_ipa,
1597 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
1598 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1599 [SLAVE_PCIE_1_CFG] = &qhs_pcie_gen3_cfg,
1600 [SLAVE_PDM] = &qhs_pdm,
1601 [SLAVE_SOUTH_PHY_CFG] = &qhs_phy_refgen_south,
1602 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1603 [SLAVE_PRNG] = &qhs_prng,
1604 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1605 [SLAVE_BLSP_2] = &qhs_qupv3_north,
1606 [SLAVE_BLSP_1] = &qhs_qupv3_south,
1607 [SLAVE_SDCC_2] = &qhs_sdc2,
1608 [SLAVE_SDCC_4] = &qhs_sdc4,
1609 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
1610 [SLAVE_SPDM_WRAPPER] = &qhs_spdm,
1611 [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
1612 [SLAVE_TCSR] = &qhs_tcsr,
1613 [SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
1614 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
1615 [SLAVE_TSIF] = &qhs_tsif,
1616 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
1617 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1618 [SLAVE_USB3_0] = &qhs_usb3_0,
1619 [SLAVE_USB3_1] = &qhs_usb3_1,
1620 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1621 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1622 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
1623 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1624};
1625
1626static const struct qcom_icc_desc sdm845_config_noc = {
1627 .nodes = config_noc_nodes,
1628 .num_nodes = ARRAY_SIZE(config_noc_nodes),
1629 .bcms = config_noc_bcms,
1630 .num_bcms = ARRAY_SIZE(config_noc_bcms),
1631};
1632
1633static struct qcom_icc_bcm * const dc_noc_bcms[] = {
1634};
1635
1636static struct qcom_icc_node * const dc_noc_nodes[] = {
1637 [MASTER_CNOC_DC_NOC] = &qhm_cnoc,
1638 [SLAVE_LLCC_CFG] = &qhs_llcc,
1639 [SLAVE_MEM_NOC_CFG] = &qhs_memnoc,
1640};
1641
1642static const struct qcom_icc_desc sdm845_dc_noc = {
1643 .nodes = dc_noc_nodes,
1644 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
1645 .bcms = dc_noc_bcms,
1646 .num_bcms = ARRAY_SIZE(dc_noc_bcms),
1647};
1648
1649static struct qcom_icc_bcm * const gladiator_noc_bcms[] = {
1650};
1651
1652static struct qcom_icc_node * const gladiator_noc_nodes[] = {
1653 [MASTER_APPSS_PROC] = &acm_l3,
1654 [MASTER_GNOC_CFG] = &pm_gnoc_cfg,
1655 [SLAVE_GNOC_SNOC] = &qns_gladiator_sodv,
1656 [SLAVE_GNOC_MEM_NOC] = &qns_gnoc_memnoc,
1657 [SLAVE_SERVICE_GNOC] = &srvc_gnoc,
1658};
1659
1660static const struct qcom_icc_desc sdm845_gladiator_noc = {
1661 .nodes = gladiator_noc_nodes,
1662 .num_nodes = ARRAY_SIZE(gladiator_noc_nodes),
1663 .bcms = gladiator_noc_bcms,
1664 .num_bcms = ARRAY_SIZE(gladiator_noc_bcms),
1665};
1666
1667static struct qcom_icc_bcm * const mem_noc_bcms[] = {
1668 &bcm_mc0,
1669 &bcm_acv,
1670 &bcm_sh0,
1671 &bcm_sh1,
1672 &bcm_sh2,
1673 &bcm_sh3,
1674 &bcm_sh5,
1675};
1676
1677static struct qcom_icc_node * const mem_noc_nodes[] = {
1678 [MASTER_TCU_0] = &acm_tcu,
1679 [MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg,
1680 [MASTER_GNOC_MEM_NOC] = &qnm_apps,
1681 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1682 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1683 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1684 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1685 [MASTER_GFX3D] = &qxm_gpu,
1686 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1687 [SLAVE_MEM_NOC_GNOC] = &qns_apps_io,
1688 [SLAVE_LLCC] = &qns_llcc,
1689 [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc,
1690 [SLAVE_SERVICE_MEM_NOC] = &srvc_memnoc,
1691 [MASTER_LLCC] = &llcc_mc,
1692 [SLAVE_EBI1] = &ebi,
1693};
1694
1695static const struct qcom_icc_desc sdm845_mem_noc = {
1696 .nodes = mem_noc_nodes,
1697 .num_nodes = ARRAY_SIZE(mem_noc_nodes),
1698 .bcms = mem_noc_bcms,
1699 .num_bcms = ARRAY_SIZE(mem_noc_bcms),
1700};
1701
1702static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1703 &bcm_mm0,
1704 &bcm_mm1,
1705 &bcm_mm2,
1706 &bcm_mm3,
1707};
1708
1709static struct qcom_icc_node * const mmss_noc_nodes[] = {
1710 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
1711 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
1712 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
1713 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
1714 [MASTER_MDP0] = &qxm_mdp0,
1715 [MASTER_MDP1] = &qxm_mdp1,
1716 [MASTER_ROTATOR] = &qxm_rot,
1717 [MASTER_VIDEO_P0] = &qxm_venus0,
1718 [MASTER_VIDEO_P1] = &qxm_venus1,
1719 [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
1720 [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
1721 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1722 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1723 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
1724 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
1725 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
1726 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
1727};
1728
1729static const struct qcom_icc_desc sdm845_mmss_noc = {
1730 .nodes = mmss_noc_nodes,
1731 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1732 .bcms = mmss_noc_bcms,
1733 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1734};
1735
1736static struct qcom_icc_bcm * const system_noc_bcms[] = {
1737 &bcm_sn0,
1738 &bcm_sn1,
1739 &bcm_sn2,
1740 &bcm_sn3,
1741 &bcm_sn4,
1742 &bcm_sn5,
1743 &bcm_sn6,
1744 &bcm_sn7,
1745 &bcm_sn8,
1746 &bcm_sn9,
1747 &bcm_sn11,
1748 &bcm_sn12,
1749 &bcm_sn14,
1750 &bcm_sn15,
1751};
1752
1753static struct qcom_icc_node * const system_noc_nodes[] = {
1754 [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
1755 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1756 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1757 [MASTER_GNOC_SNOC] = &qnm_gladiator_sodv,
1758 [MASTER_MEM_NOC_SNOC] = &qnm_memnoc,
1759 [MASTER_ANOC_PCIE_SNOC] = &qnm_pcie_anoc,
1760 [MASTER_PIMEM] = &qxm_pimem,
1761 [MASTER_GIC] = &xm_gic,
1762 [SLAVE_APPSS] = &qhs_apss,
1763 [SLAVE_SNOC_CNOC] = &qns_cnoc,
1764 [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc,
1765 [SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf,
1766 [SLAVE_IMEM] = &qxs_imem,
1767 [SLAVE_PCIE_0] = &qxs_pcie,
1768 [SLAVE_PCIE_1] = &qxs_pcie_gen3,
1769 [SLAVE_PIMEM] = &qxs_pimem,
1770 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
1771 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1772 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1773};
1774
1775static const struct qcom_icc_desc sdm845_system_noc = {
1776 .nodes = system_noc_nodes,
1777 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1778 .bcms = system_noc_bcms,
1779 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1780};
1781
1782static const struct of_device_id qnoc_of_match[] = {
1783 { .compatible = "qcom,sdm845-aggre1-noc",
1784 .data = &sdm845_aggre1_noc},
1785 { .compatible = "qcom,sdm845-aggre2-noc",
1786 .data = &sdm845_aggre2_noc},
1787 { .compatible = "qcom,sdm845-config-noc",
1788 .data = &sdm845_config_noc},
1789 { .compatible = "qcom,sdm845-dc-noc",
1790 .data = &sdm845_dc_noc},
1791 { .compatible = "qcom,sdm845-gladiator-noc",
1792 .data = &sdm845_gladiator_noc},
1793 { .compatible = "qcom,sdm845-mem-noc",
1794 .data = &sdm845_mem_noc},
1795 { .compatible = "qcom,sdm845-mmss-noc",
1796 .data = &sdm845_mmss_noc},
1797 { .compatible = "qcom,sdm845-system-noc",
1798 .data = &sdm845_system_noc},
1799 { }
1800};
1801MODULE_DEVICE_TABLE(of, qnoc_of_match);
1802
1803static struct platform_driver qnoc_driver = {
1804 .probe = qcom_icc_rpmh_probe,
1805 .remove_new = qcom_icc_rpmh_remove,
1806 .driver = {
1807 .name = "qnoc-sdm845",
1808 .of_match_table = qnoc_of_match,
1809 .sync_state = icc_sync_state,
1810 },
1811};
1812module_platform_driver(qnoc_driver);
1813
1814MODULE_AUTHOR("David Dai <daidavid1@codeaurora.org>");
1815MODULE_DESCRIPTION("Qualcomm sdm845 NoC driver");
1816MODULE_LICENSE("GPL v2");
1817

source code of linux/drivers/interconnect/qcom/sdm845.c