1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
4 *
5 * Copyright (C) 2014-2017 Broadcom
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/init.h>
11#include <linux/slab.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/spinlock.h>
15#include <linux/of.h>
16#include <linux/of_irq.h>
17#include <linux/of_address.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21#include <linux/irqdomain.h>
22#include <linux/irqchip.h>
23#include <linux/irqchip/chained_irq.h>
24
25struct brcmstb_intc_init_params {
26 irq_flow_handler_t handler;
27 int cpu_status;
28 int cpu_clear;
29 int cpu_mask_status;
30 int cpu_mask_set;
31 int cpu_mask_clear;
32};
33
34/* Register offsets in the L2 latched interrupt controller */
35static const struct brcmstb_intc_init_params l2_edge_intc_init = {
36 .handler = handle_edge_irq,
37 .cpu_status = 0x00,
38 .cpu_clear = 0x08,
39 .cpu_mask_status = 0x0c,
40 .cpu_mask_set = 0x10,
41 .cpu_mask_clear = 0x14
42};
43
44/* Register offsets in the L2 level interrupt controller */
45static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
46 .handler = handle_level_irq,
47 .cpu_status = 0x00,
48 .cpu_clear = -1, /* Register not present */
49 .cpu_mask_status = 0x04,
50 .cpu_mask_set = 0x08,
51 .cpu_mask_clear = 0x0C
52};
53
54/* L2 intc private data structure */
55struct brcmstb_l2_intc_data {
56 struct irq_domain *domain;
57 struct irq_chip_generic *gc;
58 int status_offset;
59 int mask_offset;
60 bool can_wake;
61 u32 saved_mask; /* for suspend/resume */
62};
63
64/**
65 * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
66 * @d: irq_data
67 *
68 * Chip has separate enable/disable registers instead of a single mask
69 * register and pending interrupt is acknowledged by setting a bit.
70 *
71 * Note: This function is generic and could easily be added to the
72 * generic irqchip implementation if there ever becomes a will to do so.
73 * Perhaps with a name like irq_gc_mask_disable_and_ack_set().
74 *
75 * e.g.: https://patchwork.kernel.org/patch/9831047/
76 */
77static void brcmstb_l2_mask_and_ack(struct irq_data *d)
78{
79 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
80 struct irq_chip_type *ct = irq_data_get_chip_type(d);
81 u32 mask = d->mask;
82
83 irq_gc_lock(gc);
84 irq_reg_writel(gc, val: mask, reg_offset: ct->regs.disable);
85 *ct->mask_cache &= ~mask;
86 irq_reg_writel(gc, val: mask, reg_offset: ct->regs.ack);
87 irq_gc_unlock(gc);
88}
89
90static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
91{
92 struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
93 struct irq_chip *chip = irq_desc_get_chip(desc);
94 unsigned int irq;
95 u32 status;
96
97 chained_irq_enter(chip, desc);
98
99 status = irq_reg_readl(gc: b->gc, reg_offset: b->status_offset) &
100 ~(irq_reg_readl(gc: b->gc, reg_offset: b->mask_offset));
101
102 if (status == 0) {
103 raw_spin_lock(&desc->lock);
104 handle_bad_irq(desc);
105 raw_spin_unlock(&desc->lock);
106 goto out;
107 }
108
109 do {
110 irq = ffs(status) - 1;
111 status &= ~(1 << irq);
112 generic_handle_domain_irq(domain: b->domain, hwirq: irq);
113 } while (status);
114out:
115 chained_irq_exit(chip, desc);
116}
117
118static void brcmstb_l2_intc_suspend(struct irq_data *d)
119{
120 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
121 struct irq_chip_type *ct = irq_data_get_chip_type(d);
122 struct brcmstb_l2_intc_data *b = gc->private;
123 unsigned long flags;
124
125 irq_gc_lock_irqsave(gc, flags);
126 /* Save the current mask */
127 b->saved_mask = irq_reg_readl(gc, reg_offset: ct->regs.mask);
128
129 if (b->can_wake) {
130 /* Program the wakeup mask */
131 irq_reg_writel(gc, val: ~gc->wake_active, reg_offset: ct->regs.disable);
132 irq_reg_writel(gc, val: gc->wake_active, reg_offset: ct->regs.enable);
133 }
134 irq_gc_unlock_irqrestore(gc, flags);
135}
136
137static void brcmstb_l2_intc_resume(struct irq_data *d)
138{
139 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
140 struct irq_chip_type *ct = irq_data_get_chip_type(d);
141 struct brcmstb_l2_intc_data *b = gc->private;
142 unsigned long flags;
143
144 irq_gc_lock_irqsave(gc, flags);
145 if (ct->chip.irq_ack) {
146 /* Clear unmasked non-wakeup interrupts */
147 irq_reg_writel(gc, val: ~b->saved_mask & ~gc->wake_active,
148 reg_offset: ct->regs.ack);
149 }
150
151 /* Restore the saved mask */
152 irq_reg_writel(gc, val: b->saved_mask, reg_offset: ct->regs.disable);
153 irq_reg_writel(gc, val: ~b->saved_mask, reg_offset: ct->regs.enable);
154 irq_gc_unlock_irqrestore(gc, flags);
155}
156
157static int __init brcmstb_l2_intc_of_init(struct device_node *np,
158 struct device_node *parent,
159 const struct brcmstb_intc_init_params
160 *init_params)
161{
162 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
163 unsigned int set = 0;
164 struct brcmstb_l2_intc_data *data;
165 struct irq_chip_type *ct;
166 int ret;
167 unsigned int flags;
168 int parent_irq;
169 void __iomem *base;
170
171 data = kzalloc(size: sizeof(*data), GFP_KERNEL);
172 if (!data)
173 return -ENOMEM;
174
175 base = of_iomap(node: np, index: 0);
176 if (!base) {
177 pr_err("failed to remap intc L2 registers\n");
178 ret = -ENOMEM;
179 goto out_free;
180 }
181
182 /* Disable all interrupts by default */
183 writel(val: 0xffffffff, addr: base + init_params->cpu_mask_set);
184
185 /* Wakeup interrupts may be retained from S5 (cold boot) */
186 data->can_wake = of_property_read_bool(np, propname: "brcm,irq-can-wake");
187 if (!data->can_wake && (init_params->cpu_clear >= 0))
188 writel(val: 0xffffffff, addr: base + init_params->cpu_clear);
189
190 parent_irq = irq_of_parse_and_map(node: np, index: 0);
191 if (!parent_irq) {
192 pr_err("failed to find parent interrupt\n");
193 ret = -EINVAL;
194 goto out_unmap;
195 }
196
197 data->domain = irq_domain_add_linear(of_node: np, size: 32,
198 ops: &irq_generic_chip_ops, NULL);
199 if (!data->domain) {
200 ret = -ENOMEM;
201 goto out_unmap;
202 }
203
204 /* MIPS chips strapped for BE will automagically configure the
205 * peripheral registers for CPU-native byte order.
206 */
207 flags = 0;
208 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
209 flags |= IRQ_GC_BE_IO;
210
211 if (init_params->handler == handle_level_irq)
212 set |= IRQ_LEVEL;
213
214 /* Allocate a single Generic IRQ chip for this node */
215 ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
216 np->full_name, init_params->handler, clr, set, flags);
217 if (ret) {
218 pr_err("failed to allocate generic irq chip\n");
219 goto out_free_domain;
220 }
221
222 /* Set the IRQ chaining logic */
223 irq_set_chained_handler_and_data(irq: parent_irq,
224 handle: brcmstb_l2_intc_irq_handle, data);
225
226 data->gc = irq_get_domain_generic_chip(d: data->domain, hw_irq: 0);
227 data->gc->reg_base = base;
228 data->gc->private = data;
229 data->status_offset = init_params->cpu_status;
230 data->mask_offset = init_params->cpu_mask_status;
231
232 ct = data->gc->chip_types;
233
234 if (init_params->cpu_clear >= 0) {
235 ct->regs.ack = init_params->cpu_clear;
236 ct->chip.irq_ack = irq_gc_ack_set_bit;
237 ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;
238 } else {
239 /* No Ack - but still slightly more efficient to define this */
240 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
241 }
242
243 ct->chip.irq_mask = irq_gc_mask_disable_reg;
244 ct->regs.disable = init_params->cpu_mask_set;
245 ct->regs.mask = init_params->cpu_mask_status;
246
247 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
248 ct->regs.enable = init_params->cpu_mask_clear;
249
250 ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
251 ct->chip.irq_resume = brcmstb_l2_intc_resume;
252 ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend;
253
254 if (data->can_wake) {
255 /* This IRQ chip can wake the system, set all child interrupts
256 * in wake_enabled mask
257 */
258 data->gc->wake_enabled = 0xffffffff;
259 ct->chip.irq_set_wake = irq_gc_set_wake;
260 enable_irq_wake(irq: parent_irq);
261 }
262
263 pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq);
264
265 return 0;
266
267out_free_domain:
268 irq_domain_remove(host: data->domain);
269out_unmap:
270 iounmap(addr: base);
271out_free:
272 kfree(objp: data);
273 return ret;
274}
275
276static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
277 struct device_node *parent)
278{
279 return brcmstb_l2_intc_of_init(np, parent, init_params: &l2_edge_intc_init);
280}
281
282static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
283 struct device_node *parent)
284{
285 return brcmstb_l2_intc_of_init(np, parent, init_params: &l2_lvl_intc_init);
286}
287
288IRQCHIP_PLATFORM_DRIVER_BEGIN(brcmstb_l2)
289IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_of_init)
290IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init)
291IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_of_init)
292IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_of_init)
293IRQCHIP_PLATFORM_DRIVER_END(brcmstb_l2)
294MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller");
295MODULE_LICENSE("GPL v2");
296

source code of linux/drivers/irqchip/irq-brcmstb-l2.c