Warning: That file was not part of the compilation database. It may have many parsing errors.

1/*
2 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Interrupt architecture for the GIC:
9 *
10 * o There is one Interrupt Distributor, which receives interrupts
11 * from system devices and sends them to the Interrupt Controllers.
12 *
13 * o There is one CPU Interface per CPU, which sends interrupts sent
14 * by the Distributor, and interrupts generated locally, to the
15 * associated CPU. The base address of the CPU interface is usually
16 * aliased so that the same address points to different chips depending
17 * on the CPU it is accessed from.
18 *
19 * Note that IRQs 0-31 are special - they are local to each CPU.
20 * As such, the enable set/clear, pending set/clear and active bit
21 * registers are banked per-cpu for these sources.
22 */
23#include <linux/init.h>
24#include <linux/kernel.h>
25#include <linux/err.h>
26#include <linux/module.h>
27#include <linux/list.h>
28#include <linux/smp.h>
29#include <linux/cpu.h>
30#include <linux/cpu_pm.h>
31#include <linux/cpumask.h>
32#include <linux/io.h>
33#include <linux/of.h>
34#include <linux/of_address.h>
35#include <linux/of_irq.h>
36#include <linux/acpi.h>
37#include <linux/irqdomain.h>
38#include <linux/interrupt.h>
39#include <linux/percpu.h>
40#include <linux/slab.h>
41#include <linux/irqchip.h>
42#include <linux/irqchip/chained_irq.h>
43#include <linux/irqchip/arm-gic.h>
44
45#include <asm/cputype.h>
46#include <asm/irq.h>
47#include <asm/exception.h>
48#include <asm/smp_plat.h>
49#include <asm/virt.h>
50
51#include "irq-gic-common.h"
52
53#ifdef CONFIG_ARM64
54#include <asm/cpufeature.h>
55
56static void gic_check_cpu_features(void)
57{
58 WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
59 TAINT_CPU_OUT_OF_SPEC,
60 "GICv3 system registers enabled, broken firmware!\n");
61}
62#else
63#define gic_check_cpu_features() do { } while(0)
64#endif
65
66union gic_base {
67 void __iomem *common_base;
68 void __percpu * __iomem *percpu_base;
69};
70
71struct gic_chip_data {
72 struct irq_chip chip;
73 union gic_base dist_base;
74 union gic_base cpu_base;
75 void __iomem *raw_dist_base;
76 void __iomem *raw_cpu_base;
77 u32 percpu_offset;
78#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
79 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
80 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
81 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
82 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
83 u32 __percpu *saved_ppi_enable;
84 u32 __percpu *saved_ppi_active;
85 u32 __percpu *saved_ppi_conf;
86#endif
87 struct irq_domain *domain;
88 unsigned int gic_irqs;
89#ifdef CONFIG_GIC_NON_BANKED
90 void __iomem *(*get_base)(union gic_base *);
91#endif
92};
93
94#ifdef CONFIG_BL_SWITCHER
95
96static DEFINE_RAW_SPINLOCK(cpu_map_lock);
97
98#define gic_lock_irqsave(f) \
99 raw_spin_lock_irqsave(&cpu_map_lock, (f))
100#define gic_unlock_irqrestore(f) \
101 raw_spin_unlock_irqrestore(&cpu_map_lock, (f))
102
103#define gic_lock() raw_spin_lock(&cpu_map_lock)
104#define gic_unlock() raw_spin_unlock(&cpu_map_lock)
105
106#else
107
108#define gic_lock_irqsave(f) do { (void)(f); } while(0)
109#define gic_unlock_irqrestore(f) do { (void)(f); } while(0)
110
111#define gic_lock() do { } while(0)
112#define gic_unlock() do { } while(0)
113
114#endif
115
116/*
117 * The GIC mapping of CPU interfaces does not necessarily match
118 * the logical CPU numbering. Let's use a mapping as returned
119 * by the GIC itself.
120 */
121#define NR_GIC_CPU_IF 8
122static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
123
124static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
125
126static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
127
128static struct gic_kvm_info gic_v2_kvm_info;
129
130#ifdef CONFIG_GIC_NON_BANKED
131static void __iomem *gic_get_percpu_base(union gic_base *base)
132{
133 return raw_cpu_read(*base->percpu_base);
134}
135
136static void __iomem *gic_get_common_base(union gic_base *base)
137{
138 return base->common_base;
139}
140
141static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
142{
143 return data->get_base(&data->dist_base);
144}
145
146static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
147{
148 return data->get_base(&data->cpu_base);
149}
150
151static inline void gic_set_base_accessor(struct gic_chip_data *data,
152 void __iomem *(*f)(union gic_base *))
153{
154 data->get_base = f;
155}
156#else
157#define gic_data_dist_base(d) ((d)->dist_base.common_base)
158#define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
159#define gic_set_base_accessor(d, f)
160#endif
161
162static inline void __iomem *gic_dist_base(struct irq_data *d)
163{
164 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
165 return gic_data_dist_base(gic_data);
166}
167
168static inline void __iomem *gic_cpu_base(struct irq_data *d)
169{
170 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
171 return gic_data_cpu_base(gic_data);
172}
173
174static inline unsigned int gic_irq(struct irq_data *d)
175{
176 return d->hwirq;
177}
178
179static inline bool cascading_gic_irq(struct irq_data *d)
180{
181 void *data = irq_data_get_irq_handler_data(d);
182
183 /*
184 * If handler_data is set, this is a cascading interrupt, and
185 * it cannot possibly be forwarded.
186 */
187 return data != NULL;
188}
189
190/*
191 * Routines to acknowledge, disable and enable interrupts
192 */
193static void gic_poke_irq(struct irq_data *d, u32 offset)
194{
195 u32 mask = 1 << (gic_irq(d) % 32);
196 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
197}
198
199static int gic_peek_irq(struct irq_data *d, u32 offset)
200{
201 u32 mask = 1 << (gic_irq(d) % 32);
202 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
203}
204
205static void gic_mask_irq(struct irq_data *d)
206{
207 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
208}
209
210static void gic_eoimode1_mask_irq(struct irq_data *d)
211{
212 gic_mask_irq(d);
213 /*
214 * When masking a forwarded interrupt, make sure it is
215 * deactivated as well.
216 *
217 * This ensures that an interrupt that is getting
218 * disabled/masked will not get "stuck", because there is
219 * noone to deactivate it (guest is being terminated).
220 */
221 if (irqd_is_forwarded_to_vcpu(d))
222 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
223}
224
225static void gic_unmask_irq(struct irq_data *d)
226{
227 gic_poke_irq(d, GIC_DIST_ENABLE_SET);
228}
229
230static void gic_eoi_irq(struct irq_data *d)
231{
232 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
233}
234
235static void gic_eoimode1_eoi_irq(struct irq_data *d)
236{
237 /* Do not deactivate an IRQ forwarded to a vcpu. */
238 if (irqd_is_forwarded_to_vcpu(d))
239 return;
240
241 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
242}
243
244static int gic_irq_set_irqchip_state(struct irq_data *d,
245 enum irqchip_irq_state which, bool val)
246{
247 u32 reg;
248
249 switch (which) {
250 case IRQCHIP_STATE_PENDING:
251 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
252 break;
253
254 case IRQCHIP_STATE_ACTIVE:
255 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
256 break;
257
258 case IRQCHIP_STATE_MASKED:
259 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
260 break;
261
262 default:
263 return -EINVAL;
264 }
265
266 gic_poke_irq(d, reg);
267 return 0;
268}
269
270static int gic_irq_get_irqchip_state(struct irq_data *d,
271 enum irqchip_irq_state which, bool *val)
272{
273 switch (which) {
274 case IRQCHIP_STATE_PENDING:
275 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
276 break;
277
278 case IRQCHIP_STATE_ACTIVE:
279 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
280 break;
281
282 case IRQCHIP_STATE_MASKED:
283 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
284 break;
285
286 default:
287 return -EINVAL;
288 }
289
290 return 0;
291}
292
293static int gic_set_type(struct irq_data *d, unsigned int type)
294{
295 void __iomem *base = gic_dist_base(d);
296 unsigned int gicirq = gic_irq(d);
297
298 /* Interrupt configuration for SGIs can't be changed */
299 if (gicirq < 16)
300 return -EINVAL;
301
302 /* SPIs have restrictions on the supported types */
303 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
304 type != IRQ_TYPE_EDGE_RISING)
305 return -EINVAL;
306
307 return gic_configure_irq(gicirq, type, base, NULL);
308}
309
310static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
311{
312 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
313 if (cascading_gic_irq(d))
314 return -EINVAL;
315
316 if (vcpu)
317 irqd_set_forwarded_to_vcpu(d);
318 else
319 irqd_clr_forwarded_to_vcpu(d);
320 return 0;
321}
322
323#ifdef CONFIG_SMP
324static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
325 bool force)
326{
327 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
328 unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
329 u32 val, mask, bit;
330 unsigned long flags;
331
332 if (!force)
333 cpu = cpumask_any_and(mask_val, cpu_online_mask);
334 else
335 cpu = cpumask_first(mask_val);
336
337 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
338 return -EINVAL;
339
340 gic_lock_irqsave(flags);
341 mask = 0xff << shift;
342 bit = gic_cpu_map[cpu] << shift;
343 val = readl_relaxed(reg) & ~mask;
344 writel_relaxed(val | bit, reg);
345 gic_unlock_irqrestore(flags);
346
347 irq_data_update_effective_affinity(d, cpumask_of(cpu));
348
349 return IRQ_SET_MASK_OK_DONE;
350}
351#endif
352
353static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
354{
355 u32 irqstat, irqnr;
356 struct gic_chip_data *gic = &gic_data[0];
357 void __iomem *cpu_base = gic_data_cpu_base(gic);
358
359 do {
360 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
361 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
362
363 if (likely(irqnr > 15 && irqnr < 1020)) {
364 if (static_branch_likely(&supports_deactivate_key))
365 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
366 isb();
367 handle_domain_irq(gic->domain, irqnr, regs);
368 continue;
369 }
370 if (irqnr < 16) {
371 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
372 if (static_branch_likely(&supports_deactivate_key))
373 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
374#ifdef CONFIG_SMP
375 /*
376 * Ensure any shared data written by the CPU sending
377 * the IPI is read after we've read the ACK register
378 * on the GIC.
379 *
380 * Pairs with the write barrier in gic_raise_softirq
381 */
382 smp_rmb();
383 handle_IPI(irqnr, regs);
384#endif
385 continue;
386 }
387 break;
388 } while (1);
389}
390
391static void gic_handle_cascade_irq(struct irq_desc *desc)
392{
393 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
394 struct irq_chip *chip = irq_desc_get_chip(desc);
395 unsigned int cascade_irq, gic_irq;
396 unsigned long status;
397
398 chained_irq_enter(chip, desc);
399
400 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
401
402 gic_irq = (status & GICC_IAR_INT_ID_MASK);
403 if (gic_irq == GICC_INT_SPURIOUS)
404 goto out;
405
406 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
407 if (unlikely(gic_irq < 32 || gic_irq > 1020)) {
408 handle_bad_irq(desc);
409 } else {
410 isb();
411 generic_handle_irq(cascade_irq);
412 }
413
414 out:
415 chained_irq_exit(chip, desc);
416}
417
418static const struct irq_chip gic_chip = {
419 .irq_mask = gic_mask_irq,
420 .irq_unmask = gic_unmask_irq,
421 .irq_eoi = gic_eoi_irq,
422 .irq_set_type = gic_set_type,
423 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
424 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
425 .flags = IRQCHIP_SET_TYPE_MASKED |
426 IRQCHIP_SKIP_SET_WAKE |
427 IRQCHIP_MASK_ON_SUSPEND,
428};
429
430void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
431{
432 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
433 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
434 &gic_data[gic_nr]);
435}
436
437static u8 gic_get_cpumask(struct gic_chip_data *gic)
438{
439 void __iomem *base = gic_data_dist_base(gic);
440 u32 mask, i;
441
442 for (i = mask = 0; i < 32; i += 4) {
443 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
444 mask |= mask >> 16;
445 mask |= mask >> 8;
446 if (mask)
447 break;
448 }
449
450 if (!mask && num_possible_cpus() > 1)
451 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
452
453 return mask;
454}
455
456static bool gic_check_gicv2(void __iomem *base)
457{
458 u32 val = readl_relaxed(base + GIC_CPU_IDENT);
459 return (val & 0xff0fff) == 0x02043B;
460}
461
462static void gic_cpu_if_up(struct gic_chip_data *gic)
463{
464 void __iomem *cpu_base = gic_data_cpu_base(gic);
465 u32 bypass = 0;
466 u32 mode = 0;
467 int i;
468
469 if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key))
470 mode = GIC_CPU_CTRL_EOImodeNS;
471
472 if (gic_check_gicv2(cpu_base))
473 for (i = 0; i < 4; i++)
474 writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4);
475
476 /*
477 * Preserve bypass disable bits to be written back later
478 */
479 bypass = readl(cpu_base + GIC_CPU_CTRL);
480 bypass &= GICC_DIS_BYPASS_MASK;
481
482 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
483}
484
485
486static void gic_dist_init(struct gic_chip_data *gic)
487{
488 unsigned int i;
489 u32 cpumask;
490 unsigned int gic_irqs = gic->gic_irqs;
491 void __iomem *base = gic_data_dist_base(gic);
492
493 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
494
495 /*
496 * Set all global interrupts to this CPU only.
497 */
498 cpumask = gic_get_cpumask(gic);
499 cpumask |= cpumask << 8;
500 cpumask |= cpumask << 16;
501 for (i = 32; i < gic_irqs; i += 4)
502 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
503
504 gic_dist_config(base, gic_irqs, NULL);
505
506 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
507}
508
509static int gic_cpu_init(struct gic_chip_data *gic)
510{
511 void __iomem *dist_base = gic_data_dist_base(gic);
512 void __iomem *base = gic_data_cpu_base(gic);
513 unsigned int cpu_mask, cpu = smp_processor_id();
514 int i;
515
516 /*
517 * Setting up the CPU map is only relevant for the primary GIC
518 * because any nested/secondary GICs do not directly interface
519 * with the CPU(s).
520 */
521 if (gic == &gic_data[0]) {
522 /*
523 * Get what the GIC says our CPU mask is.
524 */
525 if (WARN_ON(cpu >= NR_GIC_CPU_IF))
526 return -EINVAL;
527
528 gic_check_cpu_features();
529 cpu_mask = gic_get_cpumask(gic);
530 gic_cpu_map[cpu] = cpu_mask;
531
532 /*
533 * Clear our mask from the other map entries in case they're
534 * still undefined.
535 */
536 for (i = 0; i < NR_GIC_CPU_IF; i++)
537 if (i != cpu)
538 gic_cpu_map[i] &= ~cpu_mask;
539 }
540
541 gic_cpu_config(dist_base, NULL);
542
543 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
544 gic_cpu_if_up(gic);
545
546 return 0;
547}
548
549int gic_cpu_if_down(unsigned int gic_nr)
550{
551 void __iomem *cpu_base;
552 u32 val = 0;
553
554 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
555 return -EINVAL;
556
557 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
558 val = readl(cpu_base + GIC_CPU_CTRL);
559 val &= ~GICC_ENABLE;
560 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
561
562 return 0;
563}
564
565#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
566/*
567 * Saves the GIC distributor registers during suspend or idle. Must be called
568 * with interrupts disabled but before powering down the GIC. After calling
569 * this function, no interrupts will be delivered by the GIC, and another
570 * platform-specific wakeup source must be enabled.
571 */
572void gic_dist_save(struct gic_chip_data *gic)
573{
574 unsigned int gic_irqs;
575 void __iomem *dist_base;
576 int i;
577
578 if (WARN_ON(!gic))
579 return;
580
581 gic_irqs = gic->gic_irqs;
582 dist_base = gic_data_dist_base(gic);
583
584 if (!dist_base)
585 return;
586
587 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
588 gic->saved_spi_conf[i] =
589 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
590
591 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
592 gic->saved_spi_target[i] =
593 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
594
595 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
596 gic->saved_spi_enable[i] =
597 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
598
599 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
600 gic->saved_spi_active[i] =
601 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
602}
603
604/*
605 * Restores the GIC distributor registers during resume or when coming out of
606 * idle. Must be called before enabling interrupts. If a level interrupt
607 * that occurred while the GIC was suspended is still present, it will be
608 * handled normally, but any edge interrupts that occurred will not be seen by
609 * the GIC and need to be handled by the platform-specific wakeup source.
610 */
611void gic_dist_restore(struct gic_chip_data *gic)
612{
613 unsigned int gic_irqs;
614 unsigned int i;
615 void __iomem *dist_base;
616
617 if (WARN_ON(!gic))
618 return;
619
620 gic_irqs = gic->gic_irqs;
621 dist_base = gic_data_dist_base(gic);
622
623 if (!dist_base)
624 return;
625
626 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
627
628 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
629 writel_relaxed(gic->saved_spi_conf[i],
630 dist_base + GIC_DIST_CONFIG + i * 4);
631
632 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
633 writel_relaxed(GICD_INT_DEF_PRI_X4,
634 dist_base + GIC_DIST_PRI + i * 4);
635
636 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
637 writel_relaxed(gic->saved_spi_target[i],
638 dist_base + GIC_DIST_TARGET + i * 4);
639
640 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
641 writel_relaxed(GICD_INT_EN_CLR_X32,
642 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
643 writel_relaxed(gic->saved_spi_enable[i],
644 dist_base + GIC_DIST_ENABLE_SET + i * 4);
645 }
646
647 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
648 writel_relaxed(GICD_INT_EN_CLR_X32,
649 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
650 writel_relaxed(gic->saved_spi_active[i],
651 dist_base + GIC_DIST_ACTIVE_SET + i * 4);
652 }
653
654 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
655}
656
657void gic_cpu_save(struct gic_chip_data *gic)
658{
659 int i;
660 u32 *ptr;
661 void __iomem *dist_base;
662 void __iomem *cpu_base;
663
664 if (WARN_ON(!gic))
665 return;
666
667 dist_base = gic_data_dist_base(gic);
668 cpu_base = gic_data_cpu_base(gic);
669
670 if (!dist_base || !cpu_base)
671 return;
672
673 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
674 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
675 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
676
677 ptr = raw_cpu_ptr(gic->saved_ppi_active);
678 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
679 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
680
681 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
682 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
683 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
684
685}
686
687void gic_cpu_restore(struct gic_chip_data *gic)
688{
689 int i;
690 u32 *ptr;
691 void __iomem *dist_base;
692 void __iomem *cpu_base;
693
694 if (WARN_ON(!gic))
695 return;
696
697 dist_base = gic_data_dist_base(gic);
698 cpu_base = gic_data_cpu_base(gic);
699
700 if (!dist_base || !cpu_base)
701 return;
702
703 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
704 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
705 writel_relaxed(GICD_INT_EN_CLR_X32,
706 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
707 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
708 }
709
710 ptr = raw_cpu_ptr(gic->saved_ppi_active);
711 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
712 writel_relaxed(GICD_INT_EN_CLR_X32,
713 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
714 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
715 }
716
717 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
718 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
719 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
720
721 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
722 writel_relaxed(GICD_INT_DEF_PRI_X4,
723 dist_base + GIC_DIST_PRI + i * 4);
724
725 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
726 gic_cpu_if_up(gic);
727}
728
729static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
730{
731 int i;
732
733 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
734#ifdef CONFIG_GIC_NON_BANKED
735 /* Skip over unused GICs */
736 if (!gic_data[i].get_base)
737 continue;
738#endif
739 switch (cmd) {
740 case CPU_PM_ENTER:
741 gic_cpu_save(&gic_data[i]);
742 break;
743 case CPU_PM_ENTER_FAILED:
744 case CPU_PM_EXIT:
745 gic_cpu_restore(&gic_data[i]);
746 break;
747 case CPU_CLUSTER_PM_ENTER:
748 gic_dist_save(&gic_data[i]);
749 break;
750 case CPU_CLUSTER_PM_ENTER_FAILED:
751 case CPU_CLUSTER_PM_EXIT:
752 gic_dist_restore(&gic_data[i]);
753 break;
754 }
755 }
756
757 return NOTIFY_OK;
758}
759
760static struct notifier_block gic_notifier_block = {
761 .notifier_call = gic_notifier,
762};
763
764static int gic_pm_init(struct gic_chip_data *gic)
765{
766 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
767 sizeof(u32));
768 if (WARN_ON(!gic->saved_ppi_enable))
769 return -ENOMEM;
770
771 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
772 sizeof(u32));
773 if (WARN_ON(!gic->saved_ppi_active))
774 goto free_ppi_enable;
775
776 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
777 sizeof(u32));
778 if (WARN_ON(!gic->saved_ppi_conf))
779 goto free_ppi_active;
780
781 if (gic == &gic_data[0])
782 cpu_pm_register_notifier(&gic_notifier_block);
783
784 return 0;
785
786free_ppi_active:
787 free_percpu(gic->saved_ppi_active);
788free_ppi_enable:
789 free_percpu(gic->saved_ppi_enable);
790
791 return -ENOMEM;
792}
793#else
794static int gic_pm_init(struct gic_chip_data *gic)
795{
796 return 0;
797}
798#endif
799
800#ifdef CONFIG_SMP
801static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
802{
803 int cpu;
804 unsigned long flags, map = 0;
805
806 if (unlikely(nr_cpu_ids == 1)) {
807 /* Only one CPU? let's do a self-IPI... */
808 writel_relaxed(2 << 24 | irq,
809 gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
810 return;
811 }
812
813 gic_lock_irqsave(flags);
814
815 /* Convert our logical CPU mask into a physical one. */
816 for_each_cpu(cpu, mask)
817 map |= gic_cpu_map[cpu];
818
819 /*
820 * Ensure that stores to Normal memory are visible to the
821 * other CPUs before they observe us issuing the IPI.
822 */
823 dmb(ishst);
824
825 /* this always happens on GIC0 */
826 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
827
828 gic_unlock_irqrestore(flags);
829}
830#endif
831
832#ifdef CONFIG_BL_SWITCHER
833/*
834 * gic_send_sgi - send a SGI directly to given CPU interface number
835 *
836 * cpu_id: the ID for the destination CPU interface
837 * irq: the IPI number to send a SGI for
838 */
839void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
840{
841 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
842 cpu_id = 1 << cpu_id;
843 /* this always happens on GIC0 */
844 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
845}
846
847/*
848 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
849 *
850 * @cpu: the logical CPU number to get the GIC ID for.
851 *
852 * Return the CPU interface ID for the given logical CPU number,
853 * or -1 if the CPU number is too large or the interface ID is
854 * unknown (more than one bit set).
855 */
856int gic_get_cpu_id(unsigned int cpu)
857{
858 unsigned int cpu_bit;
859
860 if (cpu >= NR_GIC_CPU_IF)
861 return -1;
862 cpu_bit = gic_cpu_map[cpu];
863 if (cpu_bit & (cpu_bit - 1))
864 return -1;
865 return __ffs(cpu_bit);
866}
867
868/*
869 * gic_migrate_target - migrate IRQs to another CPU interface
870 *
871 * @new_cpu_id: the CPU target ID to migrate IRQs to
872 *
873 * Migrate all peripheral interrupts with a target matching the current CPU
874 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
875 * is also updated. Targets to other CPU interfaces are unchanged.
876 * This must be called with IRQs locally disabled.
877 */
878void gic_migrate_target(unsigned int new_cpu_id)
879{
880 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
881 void __iomem *dist_base;
882 int i, ror_val, cpu = smp_processor_id();
883 u32 val, cur_target_mask, active_mask;
884
885 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
886
887 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
888 if (!dist_base)
889 return;
890 gic_irqs = gic_data[gic_nr].gic_irqs;
891
892 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
893 cur_target_mask = 0x01010101 << cur_cpu_id;
894 ror_val = (cur_cpu_id - new_cpu_id) & 31;
895
896 gic_lock();
897
898 /* Update the target interface for this logical CPU */
899 gic_cpu_map[cpu] = 1 << new_cpu_id;
900
901 /*
902 * Find all the peripheral interrupts targeting the current
903 * CPU interface and migrate them to the new CPU interface.
904 * We skip DIST_TARGET 0 to 7 as they are read-only.
905 */
906 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
907 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
908 active_mask = val & cur_target_mask;
909 if (active_mask) {
910 val &= ~active_mask;
911 val |= ror32(active_mask, ror_val);
912 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
913 }
914 }
915
916 gic_unlock();
917
918 /*
919 * Now let's migrate and clear any potential SGIs that might be
920 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
921 * is a banked register, we can only forward the SGI using
922 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
923 * doesn't use that information anyway.
924 *
925 * For the same reason we do not adjust SGI source information
926 * for previously sent SGIs by us to other CPUs either.
927 */
928 for (i = 0; i < 16; i += 4) {
929 int j;
930 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
931 if (!val)
932 continue;
933 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
934 for (j = i; j < i + 4; j++) {
935 if (val & 0xff)
936 writel_relaxed((1 << (new_cpu_id + 16)) | j,
937 dist_base + GIC_DIST_SOFTINT);
938 val >>= 8;
939 }
940 }
941}
942
943/*
944 * gic_get_sgir_physaddr - get the physical address for the SGI register
945 *
946 * REturn the physical address of the SGI register to be used
947 * by some early assembly code when the kernel is not yet available.
948 */
949static unsigned long gic_dist_physaddr;
950
951unsigned long gic_get_sgir_physaddr(void)
952{
953 if (!gic_dist_physaddr)
954 return 0;
955 return gic_dist_physaddr + GIC_DIST_SOFTINT;
956}
957
958static void __init gic_init_physaddr(struct device_node *node)
959{
960 struct resource res;
961 if (of_address_to_resource(node, 0, &res) == 0) {
962 gic_dist_physaddr = res.start;
963 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
964 }
965}
966
967#else
968#define gic_init_physaddr(node) do { } while (0)
969#endif
970
971static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
972 irq_hw_number_t hw)
973{
974 struct gic_chip_data *gic = d->host_data;
975
976 if (hw < 32) {
977 irq_set_percpu_devid(irq);
978 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
979 handle_percpu_devid_irq, NULL, NULL);
980 irq_set_status_flags(irq, IRQ_NOAUTOEN);
981 } else {
982 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
983 handle_fasteoi_irq, NULL, NULL);
984 irq_set_probe(irq);
985 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
986 }
987 return 0;
988}
989
990static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
991{
992}
993
994static int gic_irq_domain_translate(struct irq_domain *d,
995 struct irq_fwspec *fwspec,
996 unsigned long *hwirq,
997 unsigned int *type)
998{
999 if (is_of_node(fwspec->fwnode)) {
1000 if (fwspec->param_count < 3)
1001 return -EINVAL;
1002
1003 /* Get the interrupt number and add 16 to skip over SGIs */
1004 *hwirq = fwspec->param[1] + 16;
1005
1006 /*
1007 * For SPIs, we need to add 16 more to get the GIC irq
1008 * ID number
1009 */
1010 if (!fwspec->param[0])
1011 *hwirq += 16;
1012
1013 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1014
1015 /* Make it clear that broken DTs are... broken */
1016 WARN_ON(*type == IRQ_TYPE_NONE);
1017 return 0;
1018 }
1019
1020 if (is_fwnode_irqchip(fwspec->fwnode)) {
1021 if(fwspec->param_count != 2)
1022 return -EINVAL;
1023
1024 *hwirq = fwspec->param[0];
1025 *type = fwspec->param[1];
1026
1027 WARN_ON(*type == IRQ_TYPE_NONE);
1028 return 0;
1029 }
1030
1031 return -EINVAL;
1032}
1033
1034static int gic_starting_cpu(unsigned int cpu)
1035{
1036 gic_cpu_init(&gic_data[0]);
1037 return 0;
1038}
1039
1040static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1041 unsigned int nr_irqs, void *arg)
1042{
1043 int i, ret;
1044 irq_hw_number_t hwirq;
1045 unsigned int type = IRQ_TYPE_NONE;
1046 struct irq_fwspec *fwspec = arg;
1047
1048 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1049 if (ret)
1050 return ret;
1051
1052 for (i = 0; i < nr_irqs; i++) {
1053 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1054 if (ret)
1055 return ret;
1056 }
1057
1058 return 0;
1059}
1060
1061static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
1062 .translate = gic_irq_domain_translate,
1063 .alloc = gic_irq_domain_alloc,
1064 .free = irq_domain_free_irqs_top,
1065};
1066
1067static const struct irq_domain_ops gic_irq_domain_ops = {
1068 .map = gic_irq_domain_map,
1069 .unmap = gic_irq_domain_unmap,
1070};
1071
1072static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
1073 const char *name, bool use_eoimode1)
1074{
1075 /* Initialize irq_chip */
1076 gic->chip = gic_chip;
1077 gic->chip.name = name;
1078 gic->chip.parent_device = dev;
1079
1080 if (use_eoimode1) {
1081 gic->chip.irq_mask = gic_eoimode1_mask_irq;
1082 gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
1083 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
1084 }
1085
1086#ifdef CONFIG_SMP
1087 if (gic == &gic_data[0])
1088 gic->chip.irq_set_affinity = gic_set_affinity;
1089#endif
1090}
1091
1092static int gic_init_bases(struct gic_chip_data *gic,
1093 struct fwnode_handle *handle)
1094{
1095 int gic_irqs, ret;
1096
1097 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1098 /* Frankein-GIC without banked registers... */
1099 unsigned int cpu;
1100
1101 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1102 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1103 if (WARN_ON(!gic->dist_base.percpu_base ||
1104 !gic->cpu_base.percpu_base)) {
1105 ret = -ENOMEM;
1106 goto error;
1107 }
1108
1109 for_each_possible_cpu(cpu) {
1110 u32 mpidr = cpu_logical_map(cpu);
1111 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1112 unsigned long offset = gic->percpu_offset * core_id;
1113 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1114 gic->raw_dist_base + offset;
1115 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1116 gic->raw_cpu_base + offset;
1117 }
1118
1119 gic_set_base_accessor(gic, gic_get_percpu_base);
1120 } else {
1121 /* Normal, sane GIC... */
1122 WARN(gic->percpu_offset,
1123 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
1124 gic->percpu_offset);
1125 gic->dist_base.common_base = gic->raw_dist_base;
1126 gic->cpu_base.common_base = gic->raw_cpu_base;
1127 gic_set_base_accessor(gic, gic_get_common_base);
1128 }
1129
1130 /*
1131 * Find out how many interrupts are supported.
1132 * The GIC only supports up to 1020 interrupt sources.
1133 */
1134 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1135 gic_irqs = (gic_irqs + 1) * 32;
1136 if (gic_irqs > 1020)
1137 gic_irqs = 1020;
1138 gic->gic_irqs = gic_irqs;
1139
1140 if (handle) { /* DT/ACPI */
1141 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1142 &gic_irq_domain_hierarchy_ops,
1143 gic);
1144 } else { /* Legacy support */
1145 /*
1146 * For primary GICs, skip over SGIs.
1147 * No secondary GIC support whatsoever.
1148 */
1149 int irq_base;
1150
1151 gic_irqs -= 16; /* calculate # of irqs to allocate */
1152
1153 irq_base = irq_alloc_descs(16, 16, gic_irqs,
1154 numa_node_id());
1155 if (irq_base < 0) {
1156 WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n");
1157 irq_base = 16;
1158 }
1159
1160 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
1161 16, &gic_irq_domain_ops, gic);
1162 }
1163
1164 if (WARN_ON(!gic->domain)) {
1165 ret = -ENODEV;
1166 goto error;
1167 }
1168
1169 gic_dist_init(gic);
1170 ret = gic_cpu_init(gic);
1171 if (ret)
1172 goto error;
1173
1174 ret = gic_pm_init(gic);
1175 if (ret)
1176 goto error;
1177
1178 return 0;
1179
1180error:
1181 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1182 free_percpu(gic->dist_base.percpu_base);
1183 free_percpu(gic->cpu_base.percpu_base);
1184 }
1185
1186 return ret;
1187}
1188
1189static int __init __gic_init_bases(struct gic_chip_data *gic,
1190 struct fwnode_handle *handle)
1191{
1192 char *name;
1193 int i, ret;
1194
1195 if (WARN_ON(!gic || gic->domain))
1196 return -EINVAL;
1197
1198 if (gic == &gic_data[0]) {
1199 /*
1200 * Initialize the CPU interface map to all CPUs.
1201 * It will be refined as each CPU probes its ID.
1202 * This is only necessary for the primary GIC.
1203 */
1204 for (i = 0; i < NR_GIC_CPU_IF; i++)
1205 gic_cpu_map[i] = 0xff;
1206#ifdef CONFIG_SMP
1207 set_smp_cross_call(gic_raise_softirq);
1208#endif
1209 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1210 "irqchip/arm/gic:starting",
1211 gic_starting_cpu, NULL);
1212 set_handle_irq(gic_handle_irq);
1213 if (static_branch_likely(&supports_deactivate_key))
1214 pr_info("GIC: Using split EOI/Deactivate mode\n");
1215 }
1216
1217 if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) {
1218 name = kasprintf(GFP_KERNEL, "GICv2");
1219 gic_init_chip(gic, NULL, name, true);
1220 } else {
1221 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));
1222 gic_init_chip(gic, NULL, name, false);
1223 }
1224
1225 ret = gic_init_bases(gic, handle);
1226 if (ret)
1227 kfree(name);
1228
1229 return ret;
1230}
1231
1232void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base)
1233{
1234 struct gic_chip_data *gic;
1235
1236 /*
1237 * Non-DT/ACPI systems won't run a hypervisor, so let's not
1238 * bother with these...
1239 */
1240 static_branch_disable(&supports_deactivate_key);
1241
1242 gic = &gic_data[0];
1243 gic->raw_dist_base = dist_base;
1244 gic->raw_cpu_base = cpu_base;
1245
1246 __gic_init_bases(gic, NULL);
1247}
1248
1249static void gic_teardown(struct gic_chip_data *gic)
1250{
1251 if (WARN_ON(!gic))
1252 return;
1253
1254 if (gic->raw_dist_base)
1255 iounmap(gic->raw_dist_base);
1256 if (gic->raw_cpu_base)
1257 iounmap(gic->raw_cpu_base);
1258}
1259
1260#ifdef CONFIG_OF
1261static int gic_cnt __initdata;
1262static bool gicv2_force_probe;
1263
1264static int __init gicv2_force_probe_cfg(char *buf)
1265{
1266 return strtobool(buf, &gicv2_force_probe);
1267}
1268early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg);
1269
1270static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1271{
1272 struct resource cpuif_res;
1273
1274 of_address_to_resource(node, 1, &cpuif_res);
1275
1276 if (!is_hyp_mode_available())
1277 return false;
1278 if (resource_size(&cpuif_res) < SZ_8K) {
1279 void __iomem *alt;
1280 /*
1281 * Check for a stupid firmware that only exposes the
1282 * first page of a GICv2.
1283 */
1284 if (!gic_check_gicv2(*base))
1285 return false;
1286
1287 if (!gicv2_force_probe) {
1288 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n");
1289 return false;
1290 }
1291
1292 alt = ioremap(cpuif_res.start, SZ_8K);
1293 if (!alt)
1294 return false;
1295 if (!gic_check_gicv2(alt + SZ_4K)) {
1296 /*
1297 * The first page was that of a GICv2, and
1298 * the second was *something*. Let's trust it
1299 * to be a GICv2, and update the mapping.
1300 */
1301 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n",
1302 &cpuif_res.start);
1303 iounmap(*base);
1304 *base = alt;
1305 return true;
1306 }
1307
1308 /*
1309 * We detected *two* initial GICv2 pages in a
1310 * row. Could be a GICv2 aliased over two 64kB
1311 * pages. Update the resource, map the iospace, and
1312 * pray.
1313 */
1314 iounmap(alt);
1315 alt = ioremap(cpuif_res.start, SZ_128K);
1316 if (!alt)
1317 return false;
1318 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n",
1319 &cpuif_res.start);
1320 cpuif_res.end = cpuif_res.start + SZ_128K -1;
1321 iounmap(*base);
1322 *base = alt;
1323 }
1324 if (resource_size(&cpuif_res) == SZ_128K) {
1325 /*
1326 * Verify that we have the first 4kB of a GICv2
1327 * aliased over the first 64kB by checking the
1328 * GICC_IIDR register on both ends.
1329 */
1330 if (!gic_check_gicv2(*base) ||
1331 !gic_check_gicv2(*base + 0xf000))
1332 return false;
1333
1334 /*
1335 * Move the base up by 60kB, so that we have a 8kB
1336 * contiguous region, which allows us to use GICC_DIR
1337 * at its normal offset. Please pass me that bucket.
1338 */
1339 *base += 0xf000;
1340 cpuif_res.start += 0xf000;
1341 pr_warn("GIC: Adjusting CPU interface base to %pa\n",
1342 &cpuif_res.start);
1343 }
1344
1345 return true;
1346}
1347
1348static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1349{
1350 if (!gic || !node)
1351 return -EINVAL;
1352
1353 gic->raw_dist_base = of_iomap(node, 0);
1354 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1355 goto error;
1356
1357 gic->raw_cpu_base = of_iomap(node, 1);
1358 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1359 goto error;
1360
1361 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1362 gic->percpu_offset = 0;
1363
1364 return 0;
1365
1366error:
1367 gic_teardown(gic);
1368
1369 return -ENOMEM;
1370}
1371
1372int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1373{
1374 int ret;
1375
1376 if (!dev || !dev->of_node || !gic || !irq)
1377 return -EINVAL;
1378
1379 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1380 if (!*gic)
1381 return -ENOMEM;
1382
1383 gic_init_chip(*gic, dev, dev->of_node->name, false);
1384
1385 ret = gic_of_setup(*gic, dev->of_node);
1386 if (ret)
1387 return ret;
1388
1389 ret = gic_init_bases(*gic, &dev->of_node->fwnode);
1390 if (ret) {
1391 gic_teardown(*gic);
1392 return ret;
1393 }
1394
1395 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1396
1397 return 0;
1398}
1399
1400static void __init gic_of_setup_kvm_info(struct device_node *node)
1401{
1402 int ret;
1403 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1404 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1405
1406 gic_v2_kvm_info.type = GIC_V2;
1407
1408 gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1409 if (!gic_v2_kvm_info.maint_irq)
1410 return;
1411
1412 ret = of_address_to_resource(node, 2, vctrl_res);
1413 if (ret)
1414 return;
1415
1416 ret = of_address_to_resource(node, 3, vcpu_res);
1417 if (ret)
1418 return;
1419
1420 if (static_branch_likely(&supports_deactivate_key))
1421 gic_set_kvm_info(&gic_v2_kvm_info);
1422}
1423
1424int __init
1425gic_of_init(struct device_node *node, struct device_node *parent)
1426{
1427 struct gic_chip_data *gic;
1428 int irq, ret;
1429
1430 if (WARN_ON(!node))
1431 return -ENODEV;
1432
1433 if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
1434 return -EINVAL;
1435
1436 gic = &gic_data[gic_cnt];
1437
1438 ret = gic_of_setup(gic, node);
1439 if (ret)
1440 return ret;
1441
1442 /*
1443 * Disable split EOI/Deactivate if either HYP is not available
1444 * or the CPU interface is too small.
1445 */
1446 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
1447 static_branch_disable(&supports_deactivate_key);
1448
1449 ret = __gic_init_bases(gic, &node->fwnode);
1450 if (ret) {
1451 gic_teardown(gic);
1452 return ret;
1453 }
1454
1455 if (!gic_cnt) {
1456 gic_init_physaddr(node);
1457 gic_of_setup_kvm_info(node);
1458 }
1459
1460 if (parent) {
1461 irq = irq_of_parse_and_map(node, 0);
1462 gic_cascade_irq(gic_cnt, irq);
1463 }
1464
1465 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1466 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
1467
1468 gic_cnt++;
1469 return 0;
1470}
1471IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1472IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1473IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1474IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1475IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1476IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1477IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1478IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1479IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
1480#else
1481int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1482{
1483 return -ENOTSUPP;
1484}
1485#endif
1486
1487#ifdef CONFIG_ACPI
1488static struct
1489{
1490 phys_addr_t cpu_phys_base;
1491 u32 maint_irq;
1492 int maint_irq_mode;
1493 phys_addr_t vctrl_base;
1494 phys_addr_t vcpu_base;
1495} acpi_data __initdata;
1496
1497static int __init
1498gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
1499 const unsigned long end)
1500{
1501 struct acpi_madt_generic_interrupt *processor;
1502 phys_addr_t gic_cpu_base;
1503 static int cpu_base_assigned;
1504
1505 processor = (struct acpi_madt_generic_interrupt *)header;
1506
1507 if (BAD_MADT_GICC_ENTRY(processor, end))
1508 return -EINVAL;
1509
1510 /*
1511 * There is no support for non-banked GICv1/2 register in ACPI spec.
1512 * All CPU interface addresses have to be the same.
1513 */
1514 gic_cpu_base = processor->base_address;
1515 if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base)
1516 return -EINVAL;
1517
1518 acpi_data.cpu_phys_base = gic_cpu_base;
1519 acpi_data.maint_irq = processor->vgic_interrupt;
1520 acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1521 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1522 acpi_data.vctrl_base = processor->gich_base_address;
1523 acpi_data.vcpu_base = processor->gicv_base_address;
1524
1525 cpu_base_assigned = 1;
1526 return 0;
1527}
1528
1529/* The things you have to do to just *count* something... */
1530static int __init acpi_dummy_func(struct acpi_subtable_header *header,
1531 const unsigned long end)
1532{
1533 return 0;
1534}
1535
1536static bool __init acpi_gic_redist_is_present(void)
1537{
1538 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1539 acpi_dummy_func, 0) > 0;
1540}
1541
1542static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1543 struct acpi_probe_entry *ape)
1544{
1545 struct acpi_madt_generic_distributor *dist;
1546 dist = (struct acpi_madt_generic_distributor *)header;
1547
1548 return (dist->version == ape->driver_data &&
1549 (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1550 !acpi_gic_redist_is_present()));
1551}
1552
1553#define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
1554#define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
1555#define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
1556#define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
1557
1558static void __init gic_acpi_setup_kvm_info(void)
1559{
1560 int irq;
1561 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1562 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1563
1564 gic_v2_kvm_info.type = GIC_V2;
1565
1566 if (!acpi_data.vctrl_base)
1567 return;
1568
1569 vctrl_res->flags = IORESOURCE_MEM;
1570 vctrl_res->start = acpi_data.vctrl_base;
1571 vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;
1572
1573 if (!acpi_data.vcpu_base)
1574 return;
1575
1576 vcpu_res->flags = IORESOURCE_MEM;
1577 vcpu_res->start = acpi_data.vcpu_base;
1578 vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1579
1580 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1581 acpi_data.maint_irq_mode,
1582 ACPI_ACTIVE_HIGH);
1583 if (irq <= 0)
1584 return;
1585
1586 gic_v2_kvm_info.maint_irq = irq;
1587
1588 gic_set_kvm_info(&gic_v2_kvm_info);
1589}
1590
1591static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
1592 const unsigned long end)
1593{
1594 struct acpi_madt_generic_distributor *dist;
1595 struct fwnode_handle *domain_handle;
1596 struct gic_chip_data *gic = &gic_data[0];
1597 int count, ret;
1598
1599 /* Collect CPU base addresses */
1600 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1601 gic_acpi_parse_madt_cpu, 0);
1602 if (count <= 0) {
1603 pr_err("No valid GICC entries exist\n");
1604 return -EINVAL;
1605 }
1606
1607 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1608 if (!gic->raw_cpu_base) {
1609 pr_err("Unable to map GICC registers\n");
1610 return -ENOMEM;
1611 }
1612
1613 dist = (struct acpi_madt_generic_distributor *)header;
1614 gic->raw_dist_base = ioremap(dist->base_address,
1615 ACPI_GICV2_DIST_MEM_SIZE);
1616 if (!gic->raw_dist_base) {
1617 pr_err("Unable to map GICD registers\n");
1618 gic_teardown(gic);
1619 return -ENOMEM;
1620 }
1621
1622 /*
1623 * Disable split EOI/Deactivate if HYP is not available. ACPI
1624 * guarantees that we'll always have a GICv2, so the CPU
1625 * interface will always be the right size.
1626 */
1627 if (!is_hyp_mode_available())
1628 static_branch_disable(&supports_deactivate_key);
1629
1630 /*
1631 * Initialize GIC instance zero (no multi-GIC support).
1632 */
1633 domain_handle = irq_domain_alloc_fwnode(gic->raw_dist_base);
1634 if (!domain_handle) {
1635 pr_err("Unable to allocate domain handle\n");
1636 gic_teardown(gic);
1637 return -ENOMEM;
1638 }
1639
1640 ret = __gic_init_bases(gic, domain_handle);
1641 if (ret) {
1642 pr_err("Failed to initialise GIC\n");
1643 irq_domain_free_fwnode(domain_handle);
1644 gic_teardown(gic);
1645 return ret;
1646 }
1647
1648 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1649
1650 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1651 gicv2m_init(NULL, gic_data[0].domain);
1652
1653 if (static_branch_likely(&supports_deactivate_key))
1654 gic_acpi_setup_kvm_info();
1655
1656 return 0;
1657}
1658IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1659 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1660 gic_v2_acpi_init);
1661IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1662 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
1663 gic_v2_acpi_init);
1664#endif
1665

Warning: That file was not part of the compilation database. It may have many parsing errors.