1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2015 Endless Mobile, Inc. |
4 | * Author: Carlo Caione <carlo@endlessm.com> |
5 | * Copyright (c) 2016 BayLibre, SAS. |
6 | * Author: Jerome Brunet <jbrunet@baylibre.com> |
7 | */ |
8 | |
9 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
10 | |
11 | #include <linux/io.h> |
12 | #include <linux/module.h> |
13 | #include <linux/irq.h> |
14 | #include <linux/irqdomain.h> |
15 | #include <linux/irqchip.h> |
16 | #include <linux/of.h> |
17 | #include <linux/of_address.h> |
18 | |
19 | #define MAX_NUM_CHANNEL 64 |
20 | #define MAX_INPUT_MUX 256 |
21 | |
22 | #define REG_EDGE_POL 0x00 |
23 | #define REG_PIN_03_SEL 0x04 |
24 | #define REG_PIN_47_SEL 0x08 |
25 | #define REG_FILTER_SEL 0x0c |
26 | |
27 | /* use for A1 like chips */ |
28 | #define REG_PIN_A1_SEL 0x04 |
29 | /* Used for s4 chips */ |
30 | #define REG_EDGE_POL_S4 0x1c |
31 | |
32 | /* |
33 | * Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by |
34 | * bits 24 to 31. Tests on the actual HW show that these bits are |
35 | * stuck at 0. Bits 8 to 15 are responsive and have the expected |
36 | * effect. |
37 | */ |
38 | #define REG_EDGE_POL_EDGE(params, x) BIT((params)->edge_single_offset + (x)) |
39 | #define REG_EDGE_POL_LOW(params, x) BIT((params)->pol_low_offset + (x)) |
40 | #define REG_BOTH_EDGE(params, x) BIT((params)->edge_both_offset + (x)) |
41 | #define REG_EDGE_POL_MASK(params, x) ( \ |
42 | REG_EDGE_POL_EDGE(params, x) | \ |
43 | REG_EDGE_POL_LOW(params, x) | \ |
44 | REG_BOTH_EDGE(params, x)) |
45 | #define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8) |
46 | #define REG_FILTER_SEL_SHIFT(x) ((x) * 4) |
47 | |
48 | struct meson_gpio_irq_controller; |
49 | static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, |
50 | unsigned int channel, unsigned long hwirq); |
51 | static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl); |
52 | static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, |
53 | unsigned int channel, |
54 | unsigned long hwirq); |
55 | static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl); |
56 | static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, |
57 | unsigned int type, u32 *channel_hwirq); |
58 | static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, |
59 | unsigned int type, u32 *channel_hwirq); |
60 | |
61 | struct irq_ctl_ops { |
62 | void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl, |
63 | unsigned int channel, unsigned long hwirq); |
64 | void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl); |
65 | int (*gpio_irq_set_type)(struct meson_gpio_irq_controller *ctl, |
66 | unsigned int type, u32 *channel_hwirq); |
67 | }; |
68 | |
69 | struct meson_gpio_irq_params { |
70 | unsigned int nr_hwirq; |
71 | unsigned int nr_channels; |
72 | bool support_edge_both; |
73 | unsigned int edge_both_offset; |
74 | unsigned int edge_single_offset; |
75 | unsigned int pol_low_offset; |
76 | unsigned int pin_sel_mask; |
77 | struct irq_ctl_ops ops; |
78 | }; |
79 | |
80 | #define INIT_MESON_COMMON(irqs, init, sel, type) \ |
81 | .nr_hwirq = irqs, \ |
82 | .ops = { \ |
83 | .gpio_irq_init = init, \ |
84 | .gpio_irq_sel_pin = sel, \ |
85 | .gpio_irq_set_type = type, \ |
86 | }, |
87 | |
88 | #define INIT_MESON8_COMMON_DATA(irqs) \ |
89 | INIT_MESON_COMMON(irqs, meson_gpio_irq_init_dummy, \ |
90 | meson8_gpio_irq_sel_pin, \ |
91 | meson8_gpio_irq_set_type) \ |
92 | .edge_single_offset = 0, \ |
93 | .pol_low_offset = 16, \ |
94 | .pin_sel_mask = 0xff, \ |
95 | .nr_channels = 8, \ |
96 | |
97 | #define INIT_MESON_A1_COMMON_DATA(irqs) \ |
98 | INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ |
99 | meson_a1_gpio_irq_sel_pin, \ |
100 | meson8_gpio_irq_set_type) \ |
101 | .support_edge_both = true, \ |
102 | .edge_both_offset = 16, \ |
103 | .edge_single_offset = 8, \ |
104 | .pol_low_offset = 0, \ |
105 | .pin_sel_mask = 0x7f, \ |
106 | .nr_channels = 8, \ |
107 | |
108 | #define INIT_MESON_S4_COMMON_DATA(irqs) \ |
109 | INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \ |
110 | meson_a1_gpio_irq_sel_pin, \ |
111 | meson_s4_gpio_irq_set_type) \ |
112 | .support_edge_both = true, \ |
113 | .edge_both_offset = 0, \ |
114 | .edge_single_offset = 12, \ |
115 | .pol_low_offset = 0, \ |
116 | .pin_sel_mask = 0xff, \ |
117 | .nr_channels = 12, \ |
118 | |
119 | static const struct meson_gpio_irq_params meson8_params = { |
120 | INIT_MESON8_COMMON_DATA(134) |
121 | }; |
122 | |
123 | static const struct meson_gpio_irq_params meson8b_params = { |
124 | INIT_MESON8_COMMON_DATA(119) |
125 | }; |
126 | |
127 | static const struct meson_gpio_irq_params gxbb_params = { |
128 | INIT_MESON8_COMMON_DATA(133) |
129 | }; |
130 | |
131 | static const struct meson_gpio_irq_params gxl_params = { |
132 | INIT_MESON8_COMMON_DATA(110) |
133 | }; |
134 | |
135 | static const struct meson_gpio_irq_params axg_params = { |
136 | INIT_MESON8_COMMON_DATA(100) |
137 | }; |
138 | |
139 | static const struct meson_gpio_irq_params sm1_params = { |
140 | INIT_MESON8_COMMON_DATA(100) |
141 | .support_edge_both = true, |
142 | .edge_both_offset = 8, |
143 | }; |
144 | |
145 | static const struct meson_gpio_irq_params a1_params = { |
146 | INIT_MESON_A1_COMMON_DATA(62) |
147 | }; |
148 | |
149 | static const struct meson_gpio_irq_params s4_params = { |
150 | INIT_MESON_S4_COMMON_DATA(82) |
151 | }; |
152 | |
153 | static const struct meson_gpio_irq_params c3_params = { |
154 | INIT_MESON_S4_COMMON_DATA(55) |
155 | }; |
156 | |
157 | static const struct of_device_id meson_irq_gpio_matches[] __maybe_unused = { |
158 | { .compatible = "amlogic,meson8-gpio-intc" , .data = &meson8_params }, |
159 | { .compatible = "amlogic,meson8b-gpio-intc" , .data = &meson8b_params }, |
160 | { .compatible = "amlogic,meson-gxbb-gpio-intc" , .data = &gxbb_params }, |
161 | { .compatible = "amlogic,meson-gxl-gpio-intc" , .data = &gxl_params }, |
162 | { .compatible = "amlogic,meson-axg-gpio-intc" , .data = &axg_params }, |
163 | { .compatible = "amlogic,meson-g12a-gpio-intc" , .data = &axg_params }, |
164 | { .compatible = "amlogic,meson-sm1-gpio-intc" , .data = &sm1_params }, |
165 | { .compatible = "amlogic,meson-a1-gpio-intc" , .data = &a1_params }, |
166 | { .compatible = "amlogic,meson-s4-gpio-intc" , .data = &s4_params }, |
167 | { .compatible = "amlogic,c3-gpio-intc" , .data = &c3_params }, |
168 | { } |
169 | }; |
170 | |
171 | struct meson_gpio_irq_controller { |
172 | const struct meson_gpio_irq_params *params; |
173 | void __iomem *base; |
174 | u32 channel_irqs[MAX_NUM_CHANNEL]; |
175 | DECLARE_BITMAP(channel_map, MAX_NUM_CHANNEL); |
176 | spinlock_t lock; |
177 | }; |
178 | |
179 | static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl, |
180 | unsigned int reg, u32 mask, u32 val) |
181 | { |
182 | unsigned long flags; |
183 | u32 tmp; |
184 | |
185 | spin_lock_irqsave(&ctl->lock, flags); |
186 | |
187 | tmp = readl_relaxed(ctl->base + reg); |
188 | tmp &= ~mask; |
189 | tmp |= val; |
190 | writel_relaxed(tmp, ctl->base + reg); |
191 | |
192 | spin_unlock_irqrestore(lock: &ctl->lock, flags); |
193 | } |
194 | |
195 | static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl) |
196 | { |
197 | } |
198 | |
199 | static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, |
200 | unsigned int channel, unsigned long hwirq) |
201 | { |
202 | unsigned int reg_offset; |
203 | unsigned int bit_offset; |
204 | |
205 | reg_offset = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL; |
206 | bit_offset = REG_PIN_SEL_SHIFT(channel); |
207 | |
208 | meson_gpio_irq_update_bits(ctl, reg: reg_offset, |
209 | mask: ctl->params->pin_sel_mask << bit_offset, |
210 | val: hwirq << bit_offset); |
211 | } |
212 | |
213 | static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, |
214 | unsigned int channel, |
215 | unsigned long hwirq) |
216 | { |
217 | unsigned int reg_offset; |
218 | unsigned int bit_offset; |
219 | |
220 | bit_offset = ((channel % 2) == 0) ? 0 : 16; |
221 | reg_offset = REG_PIN_A1_SEL + ((channel / 2) << 2); |
222 | |
223 | meson_gpio_irq_update_bits(ctl, reg: reg_offset, |
224 | mask: ctl->params->pin_sel_mask << bit_offset, |
225 | val: hwirq << bit_offset); |
226 | } |
227 | |
228 | /* For a1 or later chips like a1 there is a switch to enable/disable irq */ |
229 | static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl) |
230 | { |
231 | meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31)); |
232 | } |
233 | |
234 | static int |
235 | meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl, |
236 | unsigned long hwirq, |
237 | u32 **channel_hwirq) |
238 | { |
239 | unsigned long flags; |
240 | unsigned int idx; |
241 | |
242 | spin_lock_irqsave(&ctl->lock, flags); |
243 | |
244 | /* Find a free channel */ |
245 | idx = find_first_zero_bit(addr: ctl->channel_map, size: ctl->params->nr_channels); |
246 | if (idx >= ctl->params->nr_channels) { |
247 | spin_unlock_irqrestore(lock: &ctl->lock, flags); |
248 | pr_err("No channel available\n" ); |
249 | return -ENOSPC; |
250 | } |
251 | |
252 | /* Mark the channel as used */ |
253 | set_bit(nr: idx, addr: ctl->channel_map); |
254 | |
255 | spin_unlock_irqrestore(lock: &ctl->lock, flags); |
256 | |
257 | /* |
258 | * Setup the mux of the channel to route the signal of the pad |
259 | * to the appropriate input of the GIC |
260 | */ |
261 | ctl->params->ops.gpio_irq_sel_pin(ctl, idx, hwirq); |
262 | |
263 | /* |
264 | * Get the hwirq number assigned to this channel through |
265 | * a pointer the channel_irq table. The added benefit of this |
266 | * method is that we can also retrieve the channel index with |
267 | * it, using the table base. |
268 | */ |
269 | *channel_hwirq = &(ctl->channel_irqs[idx]); |
270 | |
271 | pr_debug("hwirq %lu assigned to channel %d - irq %u\n" , |
272 | hwirq, idx, **channel_hwirq); |
273 | |
274 | return 0; |
275 | } |
276 | |
277 | static unsigned int |
278 | meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl, |
279 | u32 *channel_hwirq) |
280 | { |
281 | return channel_hwirq - ctl->channel_irqs; |
282 | } |
283 | |
284 | static void |
285 | meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl, |
286 | u32 *channel_hwirq) |
287 | { |
288 | unsigned int idx; |
289 | |
290 | idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq); |
291 | clear_bit(nr: idx, addr: ctl->channel_map); |
292 | } |
293 | |
294 | static int meson8_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, |
295 | unsigned int type, u32 *channel_hwirq) |
296 | { |
297 | u32 val = 0; |
298 | unsigned int idx; |
299 | const struct meson_gpio_irq_params *params; |
300 | |
301 | params = ctl->params; |
302 | idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq); |
303 | |
304 | /* |
305 | * The controller has a filter block to operate in either LEVEL or |
306 | * EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and |
307 | * EDGE_FALLING support (which the GIC does not support), the filter |
308 | * block is also able to invert the input signal it gets before |
309 | * providing it to the GIC. |
310 | */ |
311 | type &= IRQ_TYPE_SENSE_MASK; |
312 | |
313 | /* |
314 | * New controller support EDGE_BOTH trigger. This setting takes |
315 | * precedence over the other edge/polarity settings |
316 | */ |
317 | if (type == IRQ_TYPE_EDGE_BOTH) { |
318 | if (!params->support_edge_both) |
319 | return -EINVAL; |
320 | |
321 | val |= REG_BOTH_EDGE(params, idx); |
322 | } else { |
323 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
324 | val |= REG_EDGE_POL_EDGE(params, idx); |
325 | |
326 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) |
327 | val |= REG_EDGE_POL_LOW(params, idx); |
328 | } |
329 | |
330 | meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, |
331 | REG_EDGE_POL_MASK(params, idx), val); |
332 | |
333 | return 0; |
334 | } |
335 | |
336 | /* |
337 | * gpio irq relative registers for s4 |
338 | * -PADCTRL_GPIO_IRQ_CTRL0 |
339 | * bit[31]: enable/disable all the irq lines |
340 | * bit[12-23]: single edge trigger |
341 | * bit[0-11]: polarity trigger |
342 | * |
343 | * -PADCTRL_GPIO_IRQ_CTRL[X] |
344 | * bit[0-16]: 7 bits to choose gpio source for irq line 2*[X] - 2 |
345 | * bit[16-22]:7 bits to choose gpio source for irq line 2*[X] - 1 |
346 | * where X = 1-6 |
347 | * |
348 | * -PADCTRL_GPIO_IRQ_CTRL[7] |
349 | * bit[0-11]: both edge trigger |
350 | */ |
351 | static int meson_s4_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl, |
352 | unsigned int type, u32 *channel_hwirq) |
353 | { |
354 | u32 val = 0; |
355 | unsigned int idx; |
356 | |
357 | idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq); |
358 | |
359 | type &= IRQ_TYPE_SENSE_MASK; |
360 | |
361 | meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4, BIT(idx), val: 0); |
362 | |
363 | if (type == IRQ_TYPE_EDGE_BOTH) { |
364 | val |= BIT(ctl->params->edge_both_offset + idx); |
365 | meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4, |
366 | BIT(ctl->params->edge_both_offset + idx), val); |
367 | return 0; |
368 | } |
369 | |
370 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) |
371 | val |= BIT(ctl->params->pol_low_offset + idx); |
372 | |
373 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
374 | val |= BIT(ctl->params->edge_single_offset + idx); |
375 | |
376 | meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, |
377 | BIT(idx) | BIT(12 + idx), val); |
378 | return 0; |
379 | }; |
380 | |
381 | static unsigned int meson_gpio_irq_type_output(unsigned int type) |
382 | { |
383 | unsigned int sense = type & IRQ_TYPE_SENSE_MASK; |
384 | |
385 | type &= ~IRQ_TYPE_SENSE_MASK; |
386 | |
387 | /* |
388 | * The polarity of the signal provided to the GIC should always |
389 | * be high. |
390 | */ |
391 | if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) |
392 | type |= IRQ_TYPE_LEVEL_HIGH; |
393 | else |
394 | type |= IRQ_TYPE_EDGE_RISING; |
395 | |
396 | return type; |
397 | } |
398 | |
399 | static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type) |
400 | { |
401 | struct meson_gpio_irq_controller *ctl = data->domain->host_data; |
402 | u32 *channel_hwirq = irq_data_get_irq_chip_data(d: data); |
403 | int ret; |
404 | |
405 | ret = ctl->params->ops.gpio_irq_set_type(ctl, type, channel_hwirq); |
406 | if (ret) |
407 | return ret; |
408 | |
409 | return irq_chip_set_type_parent(data, |
410 | type: meson_gpio_irq_type_output(type)); |
411 | } |
412 | |
413 | static struct irq_chip meson_gpio_irq_chip = { |
414 | .name = "meson-gpio-irqchip" , |
415 | .irq_mask = irq_chip_mask_parent, |
416 | .irq_unmask = irq_chip_unmask_parent, |
417 | .irq_eoi = irq_chip_eoi_parent, |
418 | .irq_set_type = meson_gpio_irq_set_type, |
419 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
420 | #ifdef CONFIG_SMP |
421 | .irq_set_affinity = irq_chip_set_affinity_parent, |
422 | #endif |
423 | .flags = IRQCHIP_SET_TYPE_MASKED, |
424 | }; |
425 | |
426 | static int meson_gpio_irq_domain_translate(struct irq_domain *domain, |
427 | struct irq_fwspec *fwspec, |
428 | unsigned long *hwirq, |
429 | unsigned int *type) |
430 | { |
431 | if (is_of_node(fwnode: fwspec->fwnode) && fwspec->param_count == 2) { |
432 | *hwirq = fwspec->param[0]; |
433 | *type = fwspec->param[1]; |
434 | return 0; |
435 | } |
436 | |
437 | return -EINVAL; |
438 | } |
439 | |
440 | static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain, |
441 | unsigned int virq, |
442 | u32 hwirq, |
443 | unsigned int type) |
444 | { |
445 | struct irq_fwspec fwspec; |
446 | |
447 | fwspec.fwnode = domain->parent->fwnode; |
448 | fwspec.param_count = 3; |
449 | fwspec.param[0] = 0; /* SPI */ |
450 | fwspec.param[1] = hwirq; |
451 | fwspec.param[2] = meson_gpio_irq_type_output(type); |
452 | |
453 | return irq_domain_alloc_irqs_parent(domain, irq_base: virq, nr_irqs: 1, arg: &fwspec); |
454 | } |
455 | |
456 | static int meson_gpio_irq_domain_alloc(struct irq_domain *domain, |
457 | unsigned int virq, |
458 | unsigned int nr_irqs, |
459 | void *data) |
460 | { |
461 | struct irq_fwspec *fwspec = data; |
462 | struct meson_gpio_irq_controller *ctl = domain->host_data; |
463 | unsigned long hwirq; |
464 | u32 *channel_hwirq; |
465 | unsigned int type; |
466 | int ret; |
467 | |
468 | if (WARN_ON(nr_irqs != 1)) |
469 | return -EINVAL; |
470 | |
471 | ret = meson_gpio_irq_domain_translate(domain, fwspec, hwirq: &hwirq, type: &type); |
472 | if (ret) |
473 | return ret; |
474 | |
475 | ret = meson_gpio_irq_request_channel(ctl, hwirq, channel_hwirq: &channel_hwirq); |
476 | if (ret) |
477 | return ret; |
478 | |
479 | ret = meson_gpio_irq_allocate_gic_irq(domain, virq, |
480 | hwirq: *channel_hwirq, type); |
481 | if (ret < 0) { |
482 | pr_err("failed to allocate gic irq %u\n" , *channel_hwirq); |
483 | meson_gpio_irq_release_channel(ctl, channel_hwirq); |
484 | return ret; |
485 | } |
486 | |
487 | irq_domain_set_hwirq_and_chip(domain, virq, hwirq, |
488 | chip: &meson_gpio_irq_chip, chip_data: channel_hwirq); |
489 | |
490 | return 0; |
491 | } |
492 | |
493 | static void meson_gpio_irq_domain_free(struct irq_domain *domain, |
494 | unsigned int virq, |
495 | unsigned int nr_irqs) |
496 | { |
497 | struct meson_gpio_irq_controller *ctl = domain->host_data; |
498 | struct irq_data *irq_data; |
499 | u32 *channel_hwirq; |
500 | |
501 | if (WARN_ON(nr_irqs != 1)) |
502 | return; |
503 | |
504 | irq_domain_free_irqs_parent(domain, irq_base: virq, nr_irqs: 1); |
505 | |
506 | irq_data = irq_domain_get_irq_data(domain, virq); |
507 | channel_hwirq = irq_data_get_irq_chip_data(d: irq_data); |
508 | |
509 | meson_gpio_irq_release_channel(ctl, channel_hwirq); |
510 | } |
511 | |
512 | static const struct irq_domain_ops meson_gpio_irq_domain_ops = { |
513 | .alloc = meson_gpio_irq_domain_alloc, |
514 | .free = meson_gpio_irq_domain_free, |
515 | .translate = meson_gpio_irq_domain_translate, |
516 | }; |
517 | |
518 | static int meson_gpio_irq_parse_dt(struct device_node *node, struct meson_gpio_irq_controller *ctl) |
519 | { |
520 | const struct of_device_id *match; |
521 | int ret; |
522 | |
523 | match = of_match_node(matches: meson_irq_gpio_matches, node); |
524 | if (!match) |
525 | return -ENODEV; |
526 | |
527 | ctl->params = match->data; |
528 | |
529 | ret = of_property_read_variable_u32_array(np: node, |
530 | propname: "amlogic,channel-interrupts" , |
531 | out_values: ctl->channel_irqs, |
532 | sz_min: ctl->params->nr_channels, |
533 | sz_max: ctl->params->nr_channels); |
534 | if (ret < 0) { |
535 | pr_err("can't get %d channel interrupts\n" , ctl->params->nr_channels); |
536 | return ret; |
537 | } |
538 | |
539 | ctl->params->ops.gpio_irq_init(ctl); |
540 | |
541 | return 0; |
542 | } |
543 | |
544 | static int meson_gpio_irq_of_init(struct device_node *node, struct device_node *parent) |
545 | { |
546 | struct irq_domain *domain, *parent_domain; |
547 | struct meson_gpio_irq_controller *ctl; |
548 | int ret; |
549 | |
550 | if (!parent) { |
551 | pr_err("missing parent interrupt node\n" ); |
552 | return -ENODEV; |
553 | } |
554 | |
555 | parent_domain = irq_find_host(node: parent); |
556 | if (!parent_domain) { |
557 | pr_err("unable to obtain parent domain\n" ); |
558 | return -ENXIO; |
559 | } |
560 | |
561 | ctl = kzalloc(size: sizeof(*ctl), GFP_KERNEL); |
562 | if (!ctl) |
563 | return -ENOMEM; |
564 | |
565 | spin_lock_init(&ctl->lock); |
566 | |
567 | ctl->base = of_iomap(node, index: 0); |
568 | if (!ctl->base) { |
569 | ret = -ENOMEM; |
570 | goto free_ctl; |
571 | } |
572 | |
573 | ret = meson_gpio_irq_parse_dt(node, ctl); |
574 | if (ret) |
575 | goto free_channel_irqs; |
576 | |
577 | domain = irq_domain_create_hierarchy(parent: parent_domain, flags: 0, |
578 | size: ctl->params->nr_hwirq, |
579 | fwnode: of_node_to_fwnode(node), |
580 | ops: &meson_gpio_irq_domain_ops, |
581 | host_data: ctl); |
582 | if (!domain) { |
583 | pr_err("failed to add domain\n" ); |
584 | ret = -ENODEV; |
585 | goto free_channel_irqs; |
586 | } |
587 | |
588 | pr_info("%d to %d gpio interrupt mux initialized\n" , |
589 | ctl->params->nr_hwirq, ctl->params->nr_channels); |
590 | |
591 | return 0; |
592 | |
593 | free_channel_irqs: |
594 | iounmap(addr: ctl->base); |
595 | free_ctl: |
596 | kfree(objp: ctl); |
597 | |
598 | return ret; |
599 | } |
600 | |
601 | IRQCHIP_PLATFORM_DRIVER_BEGIN(meson_gpio_intc) |
602 | IRQCHIP_MATCH("amlogic,meson-gpio-intc" , meson_gpio_irq_of_init) |
603 | IRQCHIP_PLATFORM_DRIVER_END(meson_gpio_intc) |
604 | |
605 | MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>" ); |
606 | MODULE_LICENSE("GPL v2" ); |
607 | MODULE_ALIAS("platform:meson-gpio-intc" ); |
608 | |