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1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
4 * Add Alphascale ASM9260 support.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/irq.h>
24#include <linux/irqchip.h>
25#include <linux/irqdomain.h>
26#include <linux/io.h>
27#include <linux/of.h>
28#include <linux/of_address.h>
29#include <linux/of_irq.h>
30#include <linux/stmp_device.h>
31#include <asm/exception.h>
32
33#include "alphascale_asm9260-icoll.h"
34
35/*
36 * this device provide 4 offsets for each register:
37 * 0x0 - plain read write mode
38 * 0x4 - set mode, OR logic.
39 * 0x8 - clr mode, XOR logic.
40 * 0xc - togle mode.
41 */
42#define SET_REG 4
43#define CLR_REG 8
44
45#define HW_ICOLL_VECTOR 0x0000
46#define HW_ICOLL_LEVELACK 0x0010
47#define HW_ICOLL_CTRL 0x0020
48#define HW_ICOLL_STAT_OFFSET 0x0070
49#define HW_ICOLL_INTERRUPT0 0x0120
50#define HW_ICOLL_INTERRUPTn(n) ((n) * 0x10)
51#define BM_ICOLL_INTR_ENABLE BIT(2)
52#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1
53
54#define ICOLL_NUM_IRQS 128
55
56enum icoll_type {
57 ICOLL,
58 ASM9260_ICOLL,
59};
60
61struct icoll_priv {
62 void __iomem *vector;
63 void __iomem *levelack;
64 void __iomem *ctrl;
65 void __iomem *stat;
66 void __iomem *intr;
67 void __iomem *clear;
68 enum icoll_type type;
69};
70
71static struct icoll_priv icoll_priv;
72static struct irq_domain *icoll_domain;
73
74/* calculate bit offset depending on number of intterupt per register */
75static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit)
76{
77 /*
78 * mask lower part of hwirq to convert it
79 * in 0, 1, 2 or 3 and then multiply it by 8 (or shift by 3)
80 */
81 return bit << ((d->hwirq & 3) << 3);
82}
83
84/* calculate mem offset depending on number of intterupt per register */
85static void __iomem *icoll_intr_reg(struct irq_data *d)
86{
87 /* offset = hwirq / intr_per_reg * 0x10 */
88 return icoll_priv.intr + ((d->hwirq >> 2) * 0x10);
89}
90
91static void icoll_ack_irq(struct irq_data *d)
92{
93 /*
94 * The Interrupt Collector is able to prioritize irqs.
95 * Currently only level 0 is used. So acking can use
96 * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally.
97 */
98 __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
99 icoll_priv.levelack);
100}
101
102static void icoll_mask_irq(struct irq_data *d)
103{
104 __raw_writel(BM_ICOLL_INTR_ENABLE,
105 icoll_priv.intr + CLR_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
106}
107
108static void icoll_unmask_irq(struct irq_data *d)
109{
110 __raw_writel(BM_ICOLL_INTR_ENABLE,
111 icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
112}
113
114static void asm9260_mask_irq(struct irq_data *d)
115{
116 __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
117 icoll_intr_reg(d) + CLR_REG);
118}
119
120static void asm9260_unmask_irq(struct irq_data *d)
121{
122 __raw_writel(ASM9260_BM_CLEAR_BIT(d->hwirq),
123 icoll_priv.clear +
124 ASM9260_HW_ICOLL_CLEARn(d->hwirq));
125
126 __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
127 icoll_intr_reg(d) + SET_REG);
128}
129
130static struct irq_chip mxs_icoll_chip = {
131 .irq_ack = icoll_ack_irq,
132 .irq_mask = icoll_mask_irq,
133 .irq_unmask = icoll_unmask_irq,
134 .flags = IRQCHIP_MASK_ON_SUSPEND |
135 IRQCHIP_SKIP_SET_WAKE,
136};
137
138static struct irq_chip asm9260_icoll_chip = {
139 .irq_ack = icoll_ack_irq,
140 .irq_mask = asm9260_mask_irq,
141 .irq_unmask = asm9260_unmask_irq,
142 .flags = IRQCHIP_MASK_ON_SUSPEND |
143 IRQCHIP_SKIP_SET_WAKE,
144};
145
146asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
147{
148 u32 irqnr;
149
150 irqnr = __raw_readl(icoll_priv.stat);
151 __raw_writel(irqnr, icoll_priv.vector);
152 handle_domain_irq(icoll_domain, irqnr, regs);
153}
154
155static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
156 irq_hw_number_t hw)
157{
158 struct irq_chip *chip;
159
160 if (icoll_priv.type == ICOLL)
161 chip = &mxs_icoll_chip;
162 else
163 chip = &asm9260_icoll_chip;
164
165 irq_set_chip_and_handler(virq, chip, handle_level_irq);
166
167 return 0;
168}
169
170static const struct irq_domain_ops icoll_irq_domain_ops = {
171 .map = icoll_irq_domain_map,
172 .xlate = irq_domain_xlate_onecell,
173};
174
175static void __init icoll_add_domain(struct device_node *np,
176 int num)
177{
178 icoll_domain = irq_domain_add_linear(np, num,
179 &icoll_irq_domain_ops, NULL);
180
181 if (!icoll_domain)
182 panic("%pOF: unable to create irq domain", np);
183}
184
185static void __iomem * __init icoll_init_iobase(struct device_node *np)
186{
187 void __iomem *icoll_base;
188
189 icoll_base = of_io_request_and_map(np, 0, np->name);
190 if (IS_ERR(icoll_base))
191 panic("%pOF: unable to map resource", np);
192 return icoll_base;
193}
194
195static int __init icoll_of_init(struct device_node *np,
196 struct device_node *interrupt_parent)
197{
198 void __iomem *icoll_base;
199
200 icoll_priv.type = ICOLL;
201
202 icoll_base = icoll_init_iobase(np);
203 icoll_priv.vector = icoll_base + HW_ICOLL_VECTOR;
204 icoll_priv.levelack = icoll_base + HW_ICOLL_LEVELACK;
205 icoll_priv.ctrl = icoll_base + HW_ICOLL_CTRL;
206 icoll_priv.stat = icoll_base + HW_ICOLL_STAT_OFFSET;
207 icoll_priv.intr = icoll_base + HW_ICOLL_INTERRUPT0;
208 icoll_priv.clear = NULL;
209
210 /*
211 * Interrupt Collector reset, which initializes the priority
212 * for each irq to level 0.
213 */
214 stmp_reset_block(icoll_priv.ctrl);
215
216 icoll_add_domain(np, ICOLL_NUM_IRQS);
217
218 return 0;
219}
220IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init);
221
222static int __init asm9260_of_init(struct device_node *np,
223 struct device_node *interrupt_parent)
224{
225 void __iomem *icoll_base;
226 int i;
227
228 icoll_priv.type = ASM9260_ICOLL;
229
230 icoll_base = icoll_init_iobase(np);
231 icoll_priv.vector = icoll_base + ASM9260_HW_ICOLL_VECTOR;
232 icoll_priv.levelack = icoll_base + ASM9260_HW_ICOLL_LEVELACK;
233 icoll_priv.ctrl = icoll_base + ASM9260_HW_ICOLL_CTRL;
234 icoll_priv.stat = icoll_base + ASM9260_HW_ICOLL_STAT_OFFSET;
235 icoll_priv.intr = icoll_base + ASM9260_HW_ICOLL_INTERRUPT0;
236 icoll_priv.clear = icoll_base + ASM9260_HW_ICOLL_CLEAR0;
237
238 writel_relaxed(ASM9260_BM_CTRL_IRQ_ENABLE,
239 icoll_priv.ctrl);
240 /*
241 * ASM9260 don't provide reset bit. So, we need to set level 0
242 * manually.
243 */
244 for (i = 0; i < 16 * 0x10; i += 0x10)
245 writel(0, icoll_priv.intr + i);
246
247 icoll_add_domain(np, ASM9260_NUM_IRQS);
248 set_handle_irq(icoll_handle_irq);
249
250 return 0;
251}
252IRQCHIP_DECLARE(asm9260, "alphascale,asm9260-icoll", asm9260_of_init);
253

Warning: That file was not part of the compilation database. It may have many parsing errors.