1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * linux/arch/arm/common/vic.c |
4 | * |
5 | * Copyright (C) 1999 - 2003 ARM Limited |
6 | * Copyright (C) 2000 Deep Blue Solutions Ltd |
7 | */ |
8 | |
9 | #include <linux/export.h> |
10 | #include <linux/init.h> |
11 | #include <linux/list.h> |
12 | #include <linux/io.h> |
13 | #include <linux/irq.h> |
14 | #include <linux/irqchip.h> |
15 | #include <linux/irqchip/chained_irq.h> |
16 | #include <linux/irqdomain.h> |
17 | #include <linux/of.h> |
18 | #include <linux/of_address.h> |
19 | #include <linux/of_irq.h> |
20 | #include <linux/syscore_ops.h> |
21 | #include <linux/device.h> |
22 | #include <linux/amba/bus.h> |
23 | #include <linux/irqchip/arm-vic.h> |
24 | |
25 | #include <asm/exception.h> |
26 | #include <asm/irq.h> |
27 | |
28 | #define VIC_IRQ_STATUS 0x00 |
29 | #define VIC_FIQ_STATUS 0x04 |
30 | #define VIC_RAW_STATUS 0x08 |
31 | #define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */ |
32 | #define VIC_INT_ENABLE 0x10 /* 1 = enable, 0 = disable */ |
33 | #define VIC_INT_ENABLE_CLEAR 0x14 |
34 | #define VIC_INT_SOFT 0x18 |
35 | #define VIC_INT_SOFT_CLEAR 0x1c |
36 | #define VIC_PROTECT 0x20 |
37 | #define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */ |
38 | #define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */ |
39 | |
40 | #define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */ |
41 | #define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */ |
42 | #define VIC_ITCR 0x300 /* VIC test control register */ |
43 | |
44 | #define VIC_VECT_CNTL_ENABLE (1 << 5) |
45 | |
46 | #define VIC_PL192_VECT_ADDR 0xF00 |
47 | |
48 | /** |
49 | * struct vic_device - VIC PM device |
50 | * @parent_irq: The parent IRQ number of the VIC if cascaded, or 0. |
51 | * @irq: The IRQ number for the base of the VIC. |
52 | * @base: The register base for the VIC. |
53 | * @valid_sources: A bitmask of valid interrupts |
54 | * @resume_sources: A bitmask of interrupts for resume. |
55 | * @resume_irqs: The IRQs enabled for resume. |
56 | * @int_select: Save for VIC_INT_SELECT. |
57 | * @int_enable: Save for VIC_INT_ENABLE. |
58 | * @soft_int: Save for VIC_INT_SOFT. |
59 | * @protect: Save for VIC_PROTECT. |
60 | * @domain: The IRQ domain for the VIC. |
61 | */ |
62 | struct vic_device { |
63 | void __iomem *base; |
64 | int irq; |
65 | u32 valid_sources; |
66 | u32 resume_sources; |
67 | u32 resume_irqs; |
68 | u32 int_select; |
69 | u32 int_enable; |
70 | u32 soft_int; |
71 | u32 protect; |
72 | struct irq_domain *domain; |
73 | }; |
74 | |
75 | /* we cannot allocate memory when VICs are initially registered */ |
76 | static struct vic_device vic_devices[CONFIG_ARM_VIC_NR]; |
77 | |
78 | static int vic_id; |
79 | |
80 | static void vic_handle_irq(struct pt_regs *regs); |
81 | |
82 | /** |
83 | * vic_init2 - common initialisation code |
84 | * @base: Base of the VIC. |
85 | * |
86 | * Common initialisation code for registration |
87 | * and resume. |
88 | */ |
89 | static void vic_init2(void __iomem *base) |
90 | { |
91 | int i; |
92 | |
93 | for (i = 0; i < 16; i++) { |
94 | void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); |
95 | writel(VIC_VECT_CNTL_ENABLE | i, addr: reg); |
96 | } |
97 | |
98 | writel(val: 32, addr: base + VIC_PL190_DEF_VECT_ADDR); |
99 | } |
100 | |
101 | #ifdef CONFIG_PM |
102 | static void resume_one_vic(struct vic_device *vic) |
103 | { |
104 | void __iomem *base = vic->base; |
105 | |
106 | printk(KERN_DEBUG "%s: resuming vic at %p\n" , __func__, base); |
107 | |
108 | /* re-initialise static settings */ |
109 | vic_init2(base); |
110 | |
111 | writel(val: vic->int_select, addr: base + VIC_INT_SELECT); |
112 | writel(val: vic->protect, addr: base + VIC_PROTECT); |
113 | |
114 | /* set the enabled ints and then clear the non-enabled */ |
115 | writel(val: vic->int_enable, addr: base + VIC_INT_ENABLE); |
116 | writel(val: ~vic->int_enable, addr: base + VIC_INT_ENABLE_CLEAR); |
117 | |
118 | /* and the same for the soft-int register */ |
119 | |
120 | writel(val: vic->soft_int, addr: base + VIC_INT_SOFT); |
121 | writel(val: ~vic->soft_int, addr: base + VIC_INT_SOFT_CLEAR); |
122 | } |
123 | |
124 | static void vic_resume(void) |
125 | { |
126 | int id; |
127 | |
128 | for (id = vic_id - 1; id >= 0; id--) |
129 | resume_one_vic(vic: vic_devices + id); |
130 | } |
131 | |
132 | static void suspend_one_vic(struct vic_device *vic) |
133 | { |
134 | void __iomem *base = vic->base; |
135 | |
136 | printk(KERN_DEBUG "%s: suspending vic at %p\n" , __func__, base); |
137 | |
138 | vic->int_select = readl(addr: base + VIC_INT_SELECT); |
139 | vic->int_enable = readl(addr: base + VIC_INT_ENABLE); |
140 | vic->soft_int = readl(addr: base + VIC_INT_SOFT); |
141 | vic->protect = readl(addr: base + VIC_PROTECT); |
142 | |
143 | /* set the interrupts (if any) that are used for |
144 | * resuming the system */ |
145 | |
146 | writel(val: vic->resume_irqs, addr: base + VIC_INT_ENABLE); |
147 | writel(val: ~vic->resume_irqs, addr: base + VIC_INT_ENABLE_CLEAR); |
148 | } |
149 | |
150 | static int vic_suspend(void) |
151 | { |
152 | int id; |
153 | |
154 | for (id = 0; id < vic_id; id++) |
155 | suspend_one_vic(vic: vic_devices + id); |
156 | |
157 | return 0; |
158 | } |
159 | |
160 | static struct syscore_ops vic_syscore_ops = { |
161 | .suspend = vic_suspend, |
162 | .resume = vic_resume, |
163 | }; |
164 | |
165 | /** |
166 | * vic_pm_init - initcall to register VIC pm |
167 | * |
168 | * This is called via late_initcall() to register |
169 | * the resources for the VICs due to the early |
170 | * nature of the VIC's registration. |
171 | */ |
172 | static int __init vic_pm_init(void) |
173 | { |
174 | if (vic_id > 0) |
175 | register_syscore_ops(ops: &vic_syscore_ops); |
176 | |
177 | return 0; |
178 | } |
179 | late_initcall(vic_pm_init); |
180 | #endif /* CONFIG_PM */ |
181 | |
182 | static struct irq_chip vic_chip; |
183 | |
184 | static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq, |
185 | irq_hw_number_t hwirq) |
186 | { |
187 | struct vic_device *v = d->host_data; |
188 | |
189 | /* Skip invalid IRQs, only register handlers for the real ones */ |
190 | if (!(v->valid_sources & (1 << hwirq))) |
191 | return -EPERM; |
192 | irq_set_chip_and_handler(irq, chip: &vic_chip, handle: handle_level_irq); |
193 | irq_set_chip_data(irq, data: v->base); |
194 | irq_set_probe(irq); |
195 | return 0; |
196 | } |
197 | |
198 | /* |
199 | * Handle each interrupt in a single VIC. Returns non-zero if we've |
200 | * handled at least one interrupt. This reads the status register |
201 | * before handling each interrupt, which is necessary given that |
202 | * handle_IRQ may briefly re-enable interrupts for soft IRQ handling. |
203 | */ |
204 | static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs) |
205 | { |
206 | u32 stat, irq; |
207 | int handled = 0; |
208 | |
209 | while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { |
210 | irq = ffs(stat) - 1; |
211 | generic_handle_domain_irq(domain: vic->domain, hwirq: irq); |
212 | handled = 1; |
213 | } |
214 | |
215 | return handled; |
216 | } |
217 | |
218 | static void vic_handle_irq_cascaded(struct irq_desc *desc) |
219 | { |
220 | u32 stat, hwirq; |
221 | struct irq_chip *host_chip = irq_desc_get_chip(desc); |
222 | struct vic_device *vic = irq_desc_get_handler_data(desc); |
223 | |
224 | chained_irq_enter(chip: host_chip, desc); |
225 | |
226 | while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { |
227 | hwirq = ffs(stat) - 1; |
228 | generic_handle_domain_irq(domain: vic->domain, hwirq); |
229 | } |
230 | |
231 | chained_irq_exit(chip: host_chip, desc); |
232 | } |
233 | |
234 | /* |
235 | * Keep iterating over all registered VIC's until there are no pending |
236 | * interrupts. |
237 | */ |
238 | static void __exception_irq_entry vic_handle_irq(struct pt_regs *regs) |
239 | { |
240 | int i, handled; |
241 | |
242 | do { |
243 | for (i = 0, handled = 0; i < vic_id; ++i) |
244 | handled |= handle_one_vic(&vic_devices[i], regs); |
245 | } while (handled); |
246 | } |
247 | |
248 | static const struct irq_domain_ops vic_irqdomain_ops = { |
249 | .map = vic_irqdomain_map, |
250 | .xlate = irq_domain_xlate_onetwocell, |
251 | }; |
252 | |
253 | /** |
254 | * vic_register() - Register a VIC. |
255 | * @base: The base address of the VIC. |
256 | * @parent_irq: The parent IRQ if cascaded, else 0. |
257 | * @irq: The base IRQ for the VIC. |
258 | * @valid_sources: bitmask of valid interrupts |
259 | * @resume_sources: bitmask of interrupts allowed for resume sources. |
260 | * @node: The device tree node associated with the VIC. |
261 | * |
262 | * Register the VIC with the system device tree so that it can be notified |
263 | * of suspend and resume requests and ensure that the correct actions are |
264 | * taken to re-instate the settings on resume. |
265 | * |
266 | * This also configures the IRQ domain for the VIC. |
267 | */ |
268 | static void __init vic_register(void __iomem *base, unsigned int parent_irq, |
269 | unsigned int irq, |
270 | u32 valid_sources, u32 resume_sources, |
271 | struct device_node *node) |
272 | { |
273 | struct vic_device *v; |
274 | int i; |
275 | |
276 | if (vic_id >= ARRAY_SIZE(vic_devices)) { |
277 | printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n" , __func__); |
278 | return; |
279 | } |
280 | |
281 | v = &vic_devices[vic_id]; |
282 | v->base = base; |
283 | v->valid_sources = valid_sources; |
284 | v->resume_sources = resume_sources; |
285 | set_handle_irq(vic_handle_irq); |
286 | vic_id++; |
287 | |
288 | if (parent_irq) { |
289 | irq_set_chained_handler_and_data(irq: parent_irq, |
290 | handle: vic_handle_irq_cascaded, data: v); |
291 | } |
292 | |
293 | v->domain = irq_domain_add_simple(of_node: node, size: fls(x: valid_sources), first_irq: irq, |
294 | ops: &vic_irqdomain_ops, host_data: v); |
295 | /* create an IRQ mapping for each valid IRQ */ |
296 | for (i = 0; i < fls(x: valid_sources); i++) |
297 | if (valid_sources & (1 << i)) |
298 | irq_create_mapping(host: v->domain, hwirq: i); |
299 | /* If no base IRQ was passed, figure out our allocated base */ |
300 | if (irq) |
301 | v->irq = irq; |
302 | else |
303 | v->irq = irq_find_mapping(domain: v->domain, hwirq: 0); |
304 | } |
305 | |
306 | static void vic_ack_irq(struct irq_data *d) |
307 | { |
308 | void __iomem *base = irq_data_get_irq_chip_data(d); |
309 | unsigned int irq = d->hwirq; |
310 | writel(val: 1 << irq, addr: base + VIC_INT_ENABLE_CLEAR); |
311 | /* moreover, clear the soft-triggered, in case it was the reason */ |
312 | writel(val: 1 << irq, addr: base + VIC_INT_SOFT_CLEAR); |
313 | } |
314 | |
315 | static void vic_mask_irq(struct irq_data *d) |
316 | { |
317 | void __iomem *base = irq_data_get_irq_chip_data(d); |
318 | unsigned int irq = d->hwirq; |
319 | writel(val: 1 << irq, addr: base + VIC_INT_ENABLE_CLEAR); |
320 | } |
321 | |
322 | static void vic_unmask_irq(struct irq_data *d) |
323 | { |
324 | void __iomem *base = irq_data_get_irq_chip_data(d); |
325 | unsigned int irq = d->hwirq; |
326 | writel(val: 1 << irq, addr: base + VIC_INT_ENABLE); |
327 | } |
328 | |
329 | #if defined(CONFIG_PM) |
330 | static struct vic_device *vic_from_irq(unsigned int irq) |
331 | { |
332 | struct vic_device *v = vic_devices; |
333 | unsigned int base_irq = irq & ~31; |
334 | int id; |
335 | |
336 | for (id = 0; id < vic_id; id++, v++) { |
337 | if (v->irq == base_irq) |
338 | return v; |
339 | } |
340 | |
341 | return NULL; |
342 | } |
343 | |
344 | static int vic_set_wake(struct irq_data *d, unsigned int on) |
345 | { |
346 | struct vic_device *v = vic_from_irq(irq: d->irq); |
347 | unsigned int off = d->hwirq; |
348 | u32 bit = 1 << off; |
349 | |
350 | if (!v) |
351 | return -EINVAL; |
352 | |
353 | if (!(bit & v->resume_sources)) |
354 | return -EINVAL; |
355 | |
356 | if (on) |
357 | v->resume_irqs |= bit; |
358 | else |
359 | v->resume_irqs &= ~bit; |
360 | |
361 | return 0; |
362 | } |
363 | #else |
364 | #define vic_set_wake NULL |
365 | #endif /* CONFIG_PM */ |
366 | |
367 | static struct irq_chip vic_chip = { |
368 | .name = "VIC" , |
369 | .irq_ack = vic_ack_irq, |
370 | .irq_mask = vic_mask_irq, |
371 | .irq_unmask = vic_unmask_irq, |
372 | .irq_set_wake = vic_set_wake, |
373 | }; |
374 | |
375 | static void __init vic_disable(void __iomem *base) |
376 | { |
377 | writel(val: 0, addr: base + VIC_INT_SELECT); |
378 | writel(val: 0, addr: base + VIC_INT_ENABLE); |
379 | writel(val: ~0, addr: base + VIC_INT_ENABLE_CLEAR); |
380 | writel(val: 0, addr: base + VIC_ITCR); |
381 | writel(val: ~0, addr: base + VIC_INT_SOFT_CLEAR); |
382 | } |
383 | |
384 | static void __init vic_clear_interrupts(void __iomem *base) |
385 | { |
386 | unsigned int i; |
387 | |
388 | writel(val: 0, addr: base + VIC_PL190_VECT_ADDR); |
389 | for (i = 0; i < 19; i++) { |
390 | unsigned int value; |
391 | |
392 | value = readl(addr: base + VIC_PL190_VECT_ADDR); |
393 | writel(val: value, addr: base + VIC_PL190_VECT_ADDR); |
394 | } |
395 | } |
396 | |
397 | /* |
398 | * The PL190 cell from ARM has been modified by ST to handle 64 interrupts. |
399 | * The original cell has 32 interrupts, while the modified one has 64, |
400 | * replicating two blocks 0x00..0x1f in 0x20..0x3f. In that case |
401 | * the probe function is called twice, with base set to offset 000 |
402 | * and 020 within the page. We call this "second block". |
403 | */ |
404 | static void __init vic_init_st(void __iomem *base, unsigned int irq_start, |
405 | u32 vic_sources, struct device_node *node) |
406 | { |
407 | unsigned int i; |
408 | int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0; |
409 | |
410 | /* Disable all interrupts initially. */ |
411 | vic_disable(base); |
412 | |
413 | /* |
414 | * Make sure we clear all existing interrupts. The vector registers |
415 | * in this cell are after the second block of general registers, |
416 | * so we can address them using standard offsets, but only from |
417 | * the second base address, which is 0x20 in the page |
418 | */ |
419 | if (vic_2nd_block) { |
420 | vic_clear_interrupts(base); |
421 | |
422 | /* ST has 16 vectors as well, but we don't enable them by now */ |
423 | for (i = 0; i < 16; i++) { |
424 | void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); |
425 | writel(val: 0, addr: reg); |
426 | } |
427 | |
428 | writel(val: 32, addr: base + VIC_PL190_DEF_VECT_ADDR); |
429 | } |
430 | |
431 | vic_register(base, parent_irq: 0, irq: irq_start, valid_sources: vic_sources, resume_sources: 0, node); |
432 | } |
433 | |
434 | static void __init __vic_init(void __iomem *base, int parent_irq, int irq_start, |
435 | u32 vic_sources, u32 resume_sources, |
436 | struct device_node *node) |
437 | { |
438 | unsigned int i; |
439 | u32 cellid = 0; |
440 | enum amba_vendor vendor; |
441 | |
442 | /* Identify which VIC cell this one is, by reading the ID */ |
443 | for (i = 0; i < 4; i++) { |
444 | void __iomem *addr; |
445 | addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4); |
446 | cellid |= (readl(addr) & 0xff) << (8 * i); |
447 | } |
448 | vendor = (cellid >> 12) & 0xff; |
449 | printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n" , |
450 | base, cellid, vendor); |
451 | |
452 | switch(vendor) { |
453 | case AMBA_VENDOR_ST: |
454 | vic_init_st(base, irq_start, vic_sources, node); |
455 | return; |
456 | default: |
457 | printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n" ); |
458 | fallthrough; |
459 | case AMBA_VENDOR_ARM: |
460 | break; |
461 | } |
462 | |
463 | /* Disable all interrupts initially. */ |
464 | vic_disable(base); |
465 | |
466 | /* Make sure we clear all existing interrupts */ |
467 | vic_clear_interrupts(base); |
468 | |
469 | vic_init2(base); |
470 | |
471 | vic_register(base, parent_irq, irq: irq_start, valid_sources: vic_sources, resume_sources, node); |
472 | } |
473 | |
474 | /** |
475 | * vic_init() - initialise a vectored interrupt controller |
476 | * @base: iomem base address |
477 | * @irq_start: starting interrupt number, must be muliple of 32 |
478 | * @vic_sources: bitmask of interrupt sources to allow |
479 | * @resume_sources: bitmask of interrupt sources to allow for resume |
480 | */ |
481 | void __init vic_init(void __iomem *base, unsigned int irq_start, |
482 | u32 vic_sources, u32 resume_sources) |
483 | { |
484 | __vic_init(base, parent_irq: 0, irq_start, vic_sources, resume_sources, NULL); |
485 | } |
486 | |
487 | #ifdef CONFIG_OF |
488 | static int __init vic_of_init(struct device_node *node, |
489 | struct device_node *parent) |
490 | { |
491 | void __iomem *regs; |
492 | u32 interrupt_mask = ~0; |
493 | u32 wakeup_mask = ~0; |
494 | int parent_irq; |
495 | |
496 | regs = of_iomap(node, index: 0); |
497 | if (WARN_ON(!regs)) |
498 | return -EIO; |
499 | |
500 | of_property_read_u32(np: node, propname: "valid-mask" , out_value: &interrupt_mask); |
501 | of_property_read_u32(np: node, propname: "valid-wakeup-mask" , out_value: &wakeup_mask); |
502 | parent_irq = of_irq_get(dev: node, index: 0); |
503 | if (parent_irq < 0) |
504 | parent_irq = 0; |
505 | |
506 | /* |
507 | * Passing 0 as first IRQ makes the simple domain allocate descriptors |
508 | */ |
509 | __vic_init(base: regs, parent_irq, irq_start: 0, vic_sources: interrupt_mask, resume_sources: wakeup_mask, node); |
510 | |
511 | return 0; |
512 | } |
513 | IRQCHIP_DECLARE(arm_pl190_vic, "arm,pl190-vic" , vic_of_init); |
514 | IRQCHIP_DECLARE(arm_pl192_vic, "arm,pl192-vic" , vic_of_init); |
515 | IRQCHIP_DECLARE(arm_versatile_vic, "arm,versatile-vic" , vic_of_init); |
516 | #endif /* CONFIG OF */ |
517 | |