1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. |
4 | */ |
5 | |
6 | #include <linux/err.h> |
7 | #include <linux/init.h> |
8 | #include <linux/interrupt.h> |
9 | #include <linux/irq.h> |
10 | #include <linux/irqchip.h> |
11 | #include <linux/irqdomain.h> |
12 | #include <linux/io.h> |
13 | #include <linux/kernel.h> |
14 | #include <linux/module.h> |
15 | #include <linux/of.h> |
16 | #include <linux/of_address.h> |
17 | #include <linux/of_irq.h> |
18 | #include <linux/soc/qcom/irq.h> |
19 | #include <linux/spinlock.h> |
20 | #include <linux/slab.h> |
21 | #include <linux/types.h> |
22 | |
23 | #define PDC_MAX_GPIO_IRQS 256 |
24 | |
25 | /* Valid only on HW version < 3.2 */ |
26 | #define IRQ_ENABLE_BANK 0x10 |
27 | #define IRQ_i_CFG 0x110 |
28 | |
29 | /* Valid only on HW version >= 3.2 */ |
30 | #define IRQ_i_CFG_IRQ_ENABLE 3 |
31 | |
32 | #define IRQ_i_CFG_TYPE_MASK GENMASK(2, 0) |
33 | |
34 | #define PDC_VERSION_REG 0x1000 |
35 | |
36 | /* Notable PDC versions */ |
37 | #define PDC_VERSION_3_2 0x30200 |
38 | |
39 | struct pdc_pin_region { |
40 | u32 pin_base; |
41 | u32 parent_base; |
42 | u32 cnt; |
43 | }; |
44 | |
45 | #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base) |
46 | |
47 | static DEFINE_RAW_SPINLOCK(pdc_lock); |
48 | static void __iomem *pdc_base; |
49 | static struct pdc_pin_region *pdc_region; |
50 | static int pdc_region_cnt; |
51 | static unsigned int pdc_version; |
52 | |
53 | static void pdc_reg_write(int reg, u32 i, u32 val) |
54 | { |
55 | writel_relaxed(val, pdc_base + reg + i * sizeof(u32)); |
56 | } |
57 | |
58 | static u32 pdc_reg_read(int reg, u32 i) |
59 | { |
60 | return readl_relaxed(pdc_base + reg + i * sizeof(u32)); |
61 | } |
62 | |
63 | static void __pdc_enable_intr(int pin_out, bool on) |
64 | { |
65 | unsigned long enable; |
66 | |
67 | if (pdc_version < PDC_VERSION_3_2) { |
68 | u32 index, mask; |
69 | |
70 | index = pin_out / 32; |
71 | mask = pin_out % 32; |
72 | |
73 | enable = pdc_reg_read(IRQ_ENABLE_BANK, i: index); |
74 | __assign_bit(nr: mask, addr: &enable, value: on); |
75 | pdc_reg_write(IRQ_ENABLE_BANK, i: index, val: enable); |
76 | } else { |
77 | enable = pdc_reg_read(IRQ_i_CFG, i: pin_out); |
78 | __assign_bit(IRQ_i_CFG_IRQ_ENABLE, addr: &enable, value: on); |
79 | pdc_reg_write(IRQ_i_CFG, i: pin_out, val: enable); |
80 | } |
81 | } |
82 | |
83 | static void pdc_enable_intr(struct irq_data *d, bool on) |
84 | { |
85 | unsigned long flags; |
86 | |
87 | raw_spin_lock_irqsave(&pdc_lock, flags); |
88 | __pdc_enable_intr(pin_out: d->hwirq, on); |
89 | raw_spin_unlock_irqrestore(&pdc_lock, flags); |
90 | } |
91 | |
92 | static void qcom_pdc_gic_disable(struct irq_data *d) |
93 | { |
94 | pdc_enable_intr(d, on: false); |
95 | irq_chip_disable_parent(data: d); |
96 | } |
97 | |
98 | static void qcom_pdc_gic_enable(struct irq_data *d) |
99 | { |
100 | pdc_enable_intr(d, on: true); |
101 | irq_chip_enable_parent(data: d); |
102 | } |
103 | |
104 | /* |
105 | * GIC does not handle falling edge or active low. To allow falling edge and |
106 | * active low interrupts to be handled at GIC, PDC has an inverter that inverts |
107 | * falling edge into a rising edge and active low into an active high. |
108 | * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to |
109 | * set as per the table below. |
110 | * Level sensitive active low LOW |
111 | * Rising edge sensitive NOT USED |
112 | * Falling edge sensitive LOW |
113 | * Dual Edge sensitive NOT USED |
114 | * Level sensitive active High HIGH |
115 | * Falling Edge sensitive NOT USED |
116 | * Rising edge sensitive HIGH |
117 | * Dual Edge sensitive HIGH |
118 | */ |
119 | enum pdc_irq_config_bits { |
120 | PDC_LEVEL_LOW = 0b000, |
121 | PDC_EDGE_FALLING = 0b010, |
122 | PDC_LEVEL_HIGH = 0b100, |
123 | PDC_EDGE_RISING = 0b110, |
124 | PDC_EDGE_DUAL = 0b111, |
125 | }; |
126 | |
127 | /** |
128 | * qcom_pdc_gic_set_type: Configure PDC for the interrupt |
129 | * |
130 | * @d: the interrupt data |
131 | * @type: the interrupt type |
132 | * |
133 | * If @type is edge triggered, forward that as Rising edge as PDC |
134 | * takes care of converting falling edge to rising edge signal |
135 | * If @type is level, then forward that as level high as PDC |
136 | * takes care of converting falling edge to rising edge signal |
137 | */ |
138 | static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) |
139 | { |
140 | enum pdc_irq_config_bits pdc_type; |
141 | enum pdc_irq_config_bits old_pdc_type; |
142 | int ret; |
143 | |
144 | switch (type) { |
145 | case IRQ_TYPE_EDGE_RISING: |
146 | pdc_type = PDC_EDGE_RISING; |
147 | break; |
148 | case IRQ_TYPE_EDGE_FALLING: |
149 | pdc_type = PDC_EDGE_FALLING; |
150 | type = IRQ_TYPE_EDGE_RISING; |
151 | break; |
152 | case IRQ_TYPE_EDGE_BOTH: |
153 | pdc_type = PDC_EDGE_DUAL; |
154 | type = IRQ_TYPE_EDGE_RISING; |
155 | break; |
156 | case IRQ_TYPE_LEVEL_HIGH: |
157 | pdc_type = PDC_LEVEL_HIGH; |
158 | break; |
159 | case IRQ_TYPE_LEVEL_LOW: |
160 | pdc_type = PDC_LEVEL_LOW; |
161 | type = IRQ_TYPE_LEVEL_HIGH; |
162 | break; |
163 | default: |
164 | WARN_ON(1); |
165 | return -EINVAL; |
166 | } |
167 | |
168 | old_pdc_type = pdc_reg_read(IRQ_i_CFG, i: d->hwirq); |
169 | pdc_type |= (old_pdc_type & ~IRQ_i_CFG_TYPE_MASK); |
170 | pdc_reg_write(IRQ_i_CFG, i: d->hwirq, val: pdc_type); |
171 | |
172 | ret = irq_chip_set_type_parent(data: d, type); |
173 | if (ret) |
174 | return ret; |
175 | |
176 | /* |
177 | * When we change types the PDC can give a phantom interrupt. |
178 | * Clear it. Specifically the phantom shows up when reconfiguring |
179 | * polarity of interrupt without changing the state of the signal |
180 | * but let's be consistent and clear it always. |
181 | * |
182 | * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the |
183 | * interrupt will be cleared before the rest of the system sees it. |
184 | */ |
185 | if (old_pdc_type != pdc_type) |
186 | irq_chip_set_parent_state(data: d, which: IRQCHIP_STATE_PENDING, val: false); |
187 | |
188 | return 0; |
189 | } |
190 | |
191 | static struct irq_chip qcom_pdc_gic_chip = { |
192 | .name = "PDC" , |
193 | .irq_eoi = irq_chip_eoi_parent, |
194 | .irq_mask = irq_chip_mask_parent, |
195 | .irq_unmask = irq_chip_unmask_parent, |
196 | .irq_disable = qcom_pdc_gic_disable, |
197 | .irq_enable = qcom_pdc_gic_enable, |
198 | .irq_get_irqchip_state = irq_chip_get_parent_state, |
199 | .irq_set_irqchip_state = irq_chip_set_parent_state, |
200 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
201 | .irq_set_type = qcom_pdc_gic_set_type, |
202 | .flags = IRQCHIP_MASK_ON_SUSPEND | |
203 | IRQCHIP_SET_TYPE_MASKED | |
204 | IRQCHIP_SKIP_SET_WAKE | |
205 | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND, |
206 | .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, |
207 | .irq_set_affinity = irq_chip_set_affinity_parent, |
208 | }; |
209 | |
210 | static struct pdc_pin_region *get_pin_region(int pin) |
211 | { |
212 | int i; |
213 | |
214 | for (i = 0; i < pdc_region_cnt; i++) { |
215 | if (pin >= pdc_region[i].pin_base && |
216 | pin < pdc_region[i].pin_base + pdc_region[i].cnt) |
217 | return &pdc_region[i]; |
218 | } |
219 | |
220 | return NULL; |
221 | } |
222 | |
223 | static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq, |
224 | unsigned int nr_irqs, void *data) |
225 | { |
226 | struct irq_fwspec *fwspec = data; |
227 | struct irq_fwspec parent_fwspec; |
228 | struct pdc_pin_region *region; |
229 | irq_hw_number_t hwirq; |
230 | unsigned int type; |
231 | int ret; |
232 | |
233 | ret = irq_domain_translate_twocell(d: domain, fwspec, out_hwirq: &hwirq, out_type: &type); |
234 | if (ret) |
235 | return ret; |
236 | |
237 | if (hwirq == GPIO_NO_WAKE_IRQ) |
238 | return irq_domain_disconnect_hierarchy(domain, virq); |
239 | |
240 | ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, |
241 | chip: &qcom_pdc_gic_chip, NULL); |
242 | if (ret) |
243 | return ret; |
244 | |
245 | region = get_pin_region(pin: hwirq); |
246 | if (!region) |
247 | return irq_domain_disconnect_hierarchy(domain: domain->parent, virq); |
248 | |
249 | if (type & IRQ_TYPE_EDGE_BOTH) |
250 | type = IRQ_TYPE_EDGE_RISING; |
251 | |
252 | if (type & IRQ_TYPE_LEVEL_MASK) |
253 | type = IRQ_TYPE_LEVEL_HIGH; |
254 | |
255 | parent_fwspec.fwnode = domain->parent->fwnode; |
256 | parent_fwspec.param_count = 3; |
257 | parent_fwspec.param[0] = 0; |
258 | parent_fwspec.param[1] = pin_to_hwirq(region, hwirq); |
259 | parent_fwspec.param[2] = type; |
260 | |
261 | return irq_domain_alloc_irqs_parent(domain, irq_base: virq, nr_irqs, |
262 | arg: &parent_fwspec); |
263 | } |
264 | |
265 | static const struct irq_domain_ops qcom_pdc_ops = { |
266 | .translate = irq_domain_translate_twocell, |
267 | .alloc = qcom_pdc_alloc, |
268 | .free = irq_domain_free_irqs_common, |
269 | }; |
270 | |
271 | static int pdc_setup_pin_mapping(struct device_node *np) |
272 | { |
273 | int ret, n, i; |
274 | |
275 | n = of_property_count_elems_of_size(np, propname: "qcom,pdc-ranges" , elem_size: sizeof(u32)); |
276 | if (n <= 0 || n % 3) |
277 | return -EINVAL; |
278 | |
279 | pdc_region_cnt = n / 3; |
280 | pdc_region = kcalloc(n: pdc_region_cnt, size: sizeof(*pdc_region), GFP_KERNEL); |
281 | if (!pdc_region) { |
282 | pdc_region_cnt = 0; |
283 | return -ENOMEM; |
284 | } |
285 | |
286 | for (n = 0; n < pdc_region_cnt; n++) { |
287 | ret = of_property_read_u32_index(np, propname: "qcom,pdc-ranges" , |
288 | index: n * 3 + 0, |
289 | out_value: &pdc_region[n].pin_base); |
290 | if (ret) |
291 | return ret; |
292 | ret = of_property_read_u32_index(np, propname: "qcom,pdc-ranges" , |
293 | index: n * 3 + 1, |
294 | out_value: &pdc_region[n].parent_base); |
295 | if (ret) |
296 | return ret; |
297 | ret = of_property_read_u32_index(np, propname: "qcom,pdc-ranges" , |
298 | index: n * 3 + 2, |
299 | out_value: &pdc_region[n].cnt); |
300 | if (ret) |
301 | return ret; |
302 | |
303 | for (i = 0; i < pdc_region[n].cnt; i++) |
304 | __pdc_enable_intr(pin_out: i + pdc_region[n].pin_base, on: 0); |
305 | } |
306 | |
307 | return 0; |
308 | } |
309 | |
310 | #define QCOM_PDC_SIZE 0x30000 |
311 | |
312 | static int qcom_pdc_init(struct device_node *node, struct device_node *parent) |
313 | { |
314 | struct irq_domain *parent_domain, *pdc_domain; |
315 | resource_size_t res_size; |
316 | struct resource res; |
317 | int ret; |
318 | |
319 | /* compat with old sm8150 DT which had very small region for PDC */ |
320 | if (of_address_to_resource(dev: node, index: 0, r: &res)) |
321 | return -EINVAL; |
322 | |
323 | res_size = max_t(resource_size_t, resource_size(&res), QCOM_PDC_SIZE); |
324 | if (res_size > resource_size(res: &res)) |
325 | pr_warn("%pOF: invalid reg size, please fix DT\n" , node); |
326 | |
327 | pdc_base = ioremap(offset: res.start, size: res_size); |
328 | if (!pdc_base) { |
329 | pr_err("%pOF: unable to map PDC registers\n" , node); |
330 | return -ENXIO; |
331 | } |
332 | |
333 | pdc_version = pdc_reg_read(PDC_VERSION_REG, i: 0); |
334 | |
335 | parent_domain = irq_find_host(node: parent); |
336 | if (!parent_domain) { |
337 | pr_err("%pOF: unable to find PDC's parent domain\n" , node); |
338 | ret = -ENXIO; |
339 | goto fail; |
340 | } |
341 | |
342 | ret = pdc_setup_pin_mapping(np: node); |
343 | if (ret) { |
344 | pr_err("%pOF: failed to init PDC pin-hwirq mapping\n" , node); |
345 | goto fail; |
346 | } |
347 | |
348 | pdc_domain = irq_domain_create_hierarchy(parent: parent_domain, |
349 | IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, |
350 | PDC_MAX_GPIO_IRQS, |
351 | of_fwnode_handle(node), |
352 | ops: &qcom_pdc_ops, NULL); |
353 | if (!pdc_domain) { |
354 | pr_err("%pOF: PDC domain add failed\n" , node); |
355 | ret = -ENOMEM; |
356 | goto fail; |
357 | } |
358 | |
359 | irq_domain_update_bus_token(domain: pdc_domain, bus_token: DOMAIN_BUS_WAKEUP); |
360 | |
361 | return 0; |
362 | |
363 | fail: |
364 | kfree(objp: pdc_region); |
365 | iounmap(addr: pdc_base); |
366 | return ret; |
367 | } |
368 | |
369 | IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc) |
370 | IRQCHIP_MATCH("qcom,pdc" , qcom_pdc_init) |
371 | IRQCHIP_PLATFORM_DRIVER_END(qcom_pdc) |
372 | MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller" ); |
373 | MODULE_LICENSE("GPL v2" ); |
374 | |