1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Copyright (c) 2000-2008 LSI Corporation. |
4 | * |
5 | * |
6 | * Name: mpi_init.h |
7 | * Title: MPI initiator mode messages and structures |
8 | * Creation Date: June 8, 2000 |
9 | * |
10 | * mpi_init.h Version: 01.05.09 |
11 | * |
12 | * Version History |
13 | * --------------- |
14 | * |
15 | * Date Version Description |
16 | * -------- -------- ------------------------------------------------------ |
17 | * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. |
18 | * 05-24-00 00.10.02 Added SenseBufferLength to _MSG_SCSI_IO_REPLY. |
19 | * 06-06-00 01.00.01 Update version number for 1.0 release. |
20 | * 06-08-00 01.00.02 Added MPI_SCSI_RSP_INFO_ definitions. |
21 | * 11-02-00 01.01.01 Original release for post 1.0 work. |
22 | * 12-04-00 01.01.02 Added MPI_SCSIIO_CONTROL_NO_DISCONNECT. |
23 | * 02-20-01 01.01.03 Started using MPI_POINTER. |
24 | * 03-27-01 01.01.04 Added structure offset comments. |
25 | * 04-10-01 01.01.05 Added new MsgFlag for MSG_SCSI_TASK_MGMT. |
26 | * 08-08-01 01.02.01 Original release for v1.2 work. |
27 | * 08-29-01 01.02.02 Added MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET. |
28 | * Added MPI_SCSI_STATE_QUEUE_TAG_REJECTED for |
29 | * MSG_SCSI_IO_REPLY. |
30 | * 09-28-01 01.02.03 Added structures and defines for SCSI Enclosure |
31 | * Processor messages. |
32 | * 10-04-01 01.02.04 Added defines for SEP request Action field. |
33 | * 05-31-02 01.02.05 Added MPI_SCSIIO_MSGFLGS_CMD_DETERMINES_DATA_DIR define |
34 | * for SCSI IO requests. |
35 | * 11-15-02 01.02.06 Added special extended SCSI Status defines for FCP. |
36 | * 06-26-03 01.02.07 Added MPI_SCSI_STATUS_FCPEXT_UNASSIGNED define. |
37 | * 05-11-04 01.03.01 Original release for MPI v1.3. |
38 | * 08-19-04 01.05.01 Added MsgFlags defines for EEDP to SCSI IO request. |
39 | * Added new word to MSG_SCSI_IO_REPLY to add TaskTag field |
40 | * and a reserved U16. |
41 | * Added new MSG_SCSI_IO32_REQUEST structure. |
42 | * Added a TaskType of Clear Task Set to SCSI |
43 | * Task Management request. |
44 | * 12-07-04 01.05.02 Added support for Task Management Query Task. |
45 | * 01-15-05 01.05.03 Modified SCSI Enclosure Processor Request to support |
46 | * WWID addressing. |
47 | * 03-11-05 01.05.04 Removed EEDP flags from SCSI IO Request. |
48 | * Removed SCSI IO 32 Request. |
49 | * Modified SCSI Enclosure Processor Request and Reply to |
50 | * support Enclosure/Slot addressing rather than WWID |
51 | * addressing. |
52 | * 06-24-05 01.05.05 Added SCSI IO 32 structures and defines. |
53 | * Added four new defines for SEP SlotStatus. |
54 | * 08-03-05 01.05.06 Fixed some MPI_SCSIIO32_MSGFLGS_ defines to make them |
55 | * unique in the first 32 characters. |
56 | * 03-27-06 01.05.07 Added Task Management type of Clear ACA. |
57 | * 10-11-06 01.05.08 Shortened define for Task Management type of Clear ACA. |
58 | * 02-28-07 01.05.09 Defined two new MsgFlags bits for SCSI Task Management |
59 | * Request: Do Not Send Task IU and Soft Reset Option. |
60 | * -------------------------------------------------------------------------- |
61 | */ |
62 | |
63 | #ifndef MPI_INIT_H |
64 | #define MPI_INIT_H |
65 | |
66 | |
67 | /***************************************************************************** |
68 | * |
69 | * S C S I I n i t i a t o r M e s s a g e s |
70 | * |
71 | *****************************************************************************/ |
72 | |
73 | /****************************************************************************/ |
74 | /* SCSI IO messages and associated structures */ |
75 | /****************************************************************************/ |
76 | |
77 | typedef struct _MSG_SCSI_IO_REQUEST |
78 | { |
79 | U8 TargetID; /* 00h */ |
80 | U8 Bus; /* 01h */ |
81 | U8 ChainOffset; /* 02h */ |
82 | U8 Function; /* 03h */ |
83 | U8 CDBLength; /* 04h */ |
84 | U8 SenseBufferLength; /* 05h */ |
85 | U8 Reserved; /* 06h */ |
86 | U8 MsgFlags; /* 07h */ |
87 | U32 MsgContext; /* 08h */ |
88 | U8 LUN[8]; /* 0Ch */ |
89 | U32 Control; /* 14h */ |
90 | U8 CDB[16]; /* 18h */ |
91 | U32 DataLength; /* 28h */ |
92 | U32 SenseBufferLowAddr; /* 2Ch */ |
93 | SGE_IO_UNION SGL; /* 30h */ |
94 | } MSG_SCSI_IO_REQUEST, MPI_POINTER PTR_MSG_SCSI_IO_REQUEST, |
95 | SCSIIORequest_t, MPI_POINTER pSCSIIORequest_t; |
96 | |
97 | |
98 | /* SCSI IO MsgFlags bits */ |
99 | |
100 | #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH (0x01) |
101 | #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_32 (0x00) |
102 | #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_64 (0x01) |
103 | |
104 | #define MPI_SCSIIO_MSGFLGS_SENSE_LOCATION (0x02) |
105 | #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_HOST (0x00) |
106 | #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_IOC (0x02) |
107 | |
108 | #define MPI_SCSIIO_MSGFLGS_CMD_DETERMINES_DATA_DIR (0x04) |
109 | |
110 | /* SCSI IO LUN fields */ |
111 | |
112 | #define MPI_SCSIIO_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) |
113 | #define MPI_SCSIIO_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) |
114 | #define MPI_SCSIIO_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) |
115 | #define MPI_SCSIIO_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) |
116 | #define MPI_SCSIIO_LUN_LEVEL_1_WORD (0xFF00) |
117 | #define MPI_SCSIIO_LUN_LEVEL_1_DWORD (0x0000FF00) |
118 | |
119 | /* SCSI IO Control bits */ |
120 | |
121 | #define MPI_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) |
122 | #define MPI_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) |
123 | #define MPI_SCSIIO_CONTROL_WRITE (0x01000000) |
124 | #define MPI_SCSIIO_CONTROL_READ (0x02000000) |
125 | |
126 | #define MPI_SCSIIO_CONTROL_ADDCDBLEN_MASK (0x3C000000) |
127 | #define MPI_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) |
128 | |
129 | #define MPI_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) |
130 | #define MPI_SCSIIO_CONTROL_SIMPLEQ (0x00000000) |
131 | #define MPI_SCSIIO_CONTROL_HEADOFQ (0x00000100) |
132 | #define MPI_SCSIIO_CONTROL_ORDEREDQ (0x00000200) |
133 | #define MPI_SCSIIO_CONTROL_ACAQ (0x00000400) |
134 | #define MPI_SCSIIO_CONTROL_UNTAGGED (0x00000500) |
135 | #define MPI_SCSIIO_CONTROL_NO_DISCONNECT (0x00000700) |
136 | |
137 | #define MPI_SCSIIO_CONTROL_TASKMANAGE_MASK (0x00FF0000) |
138 | #define MPI_SCSIIO_CONTROL_OBSOLETE (0x00800000) |
139 | #define MPI_SCSIIO_CONTROL_CLEAR_ACA_RSV (0x00400000) |
140 | #define MPI_SCSIIO_CONTROL_TARGET_RESET (0x00200000) |
141 | #define MPI_SCSIIO_CONTROL_LUN_RESET_RSV (0x00100000) |
142 | #define MPI_SCSIIO_CONTROL_RESERVED (0x00080000) |
143 | #define MPI_SCSIIO_CONTROL_CLR_TASK_SET_RSV (0x00040000) |
144 | #define MPI_SCSIIO_CONTROL_ABORT_TASK_SET (0x00020000) |
145 | #define MPI_SCSIIO_CONTROL_RESERVED2 (0x00010000) |
146 | |
147 | |
148 | /* SCSI IO reply structure */ |
149 | typedef struct _MSG_SCSI_IO_REPLY |
150 | { |
151 | U8 TargetID; /* 00h */ |
152 | U8 Bus; /* 01h */ |
153 | U8 MsgLength; /* 02h */ |
154 | U8 Function; /* 03h */ |
155 | U8 CDBLength; /* 04h */ |
156 | U8 SenseBufferLength; /* 05h */ |
157 | U8 Reserved; /* 06h */ |
158 | U8 MsgFlags; /* 07h */ |
159 | U32 MsgContext; /* 08h */ |
160 | U8 SCSIStatus; /* 0Ch */ |
161 | U8 SCSIState; /* 0Dh */ |
162 | U16 IOCStatus; /* 0Eh */ |
163 | U32 IOCLogInfo; /* 10h */ |
164 | U32 TransferCount; /* 14h */ |
165 | U32 SenseCount; /* 18h */ |
166 | U32 ResponseInfo; /* 1Ch */ |
167 | U16 TaskTag; /* 20h */ |
168 | U16 Reserved1; /* 22h */ |
169 | } MSG_SCSI_IO_REPLY, MPI_POINTER PTR_MSG_SCSI_IO_REPLY, |
170 | SCSIIOReply_t, MPI_POINTER pSCSIIOReply_t; |
171 | |
172 | |
173 | /* SCSI IO Reply SCSIStatus values (SAM-2 status codes) */ |
174 | |
175 | #define MPI_SCSI_STATUS_SUCCESS (0x00) |
176 | #define MPI_SCSI_STATUS_CHECK_CONDITION (0x02) |
177 | #define MPI_SCSI_STATUS_CONDITION_MET (0x04) |
178 | #define MPI_SCSI_STATUS_BUSY (0x08) |
179 | #define MPI_SCSI_STATUS_INTERMEDIATE (0x10) |
180 | #define MPI_SCSI_STATUS_INTERMEDIATE_CONDMET (0x14) |
181 | #define MPI_SCSI_STATUS_RESERVATION_CONFLICT (0x18) |
182 | #define MPI_SCSI_STATUS_COMMAND_TERMINATED (0x22) |
183 | #define MPI_SCSI_STATUS_TASK_SET_FULL (0x28) |
184 | #define MPI_SCSI_STATUS_ACA_ACTIVE (0x30) |
185 | |
186 | #define MPI_SCSI_STATUS_FCPEXT_DEVICE_LOGGED_OUT (0x80) |
187 | #define MPI_SCSI_STATUS_FCPEXT_NO_LINK (0x81) |
188 | #define MPI_SCSI_STATUS_FCPEXT_UNASSIGNED (0x82) |
189 | |
190 | |
191 | /* SCSI IO Reply SCSIState values */ |
192 | |
193 | #define MPI_SCSI_STATE_AUTOSENSE_VALID (0x01) |
194 | #define MPI_SCSI_STATE_AUTOSENSE_FAILED (0x02) |
195 | #define MPI_SCSI_STATE_NO_SCSI_STATUS (0x04) |
196 | #define MPI_SCSI_STATE_TERMINATED (0x08) |
197 | #define MPI_SCSI_STATE_RESPONSE_INFO_VALID (0x10) |
198 | #define MPI_SCSI_STATE_QUEUE_TAG_REJECTED (0x20) |
199 | |
200 | /* SCSI IO Reply ResponseInfo values */ |
201 | /* (FCP-1 RSP_CODE values and SPI-3 Packetized Failure codes) */ |
202 | |
203 | #define MPI_SCSI_RSP_INFO_FUNCTION_COMPLETE (0x00000000) |
204 | #define MPI_SCSI_RSP_INFO_FCP_BURST_LEN_ERROR (0x01000000) |
205 | #define MPI_SCSI_RSP_INFO_CMND_FIELDS_INVALID (0x02000000) |
206 | #define MPI_SCSI_RSP_INFO_FCP_DATA_RO_ERROR (0x03000000) |
207 | #define MPI_SCSI_RSP_INFO_TASK_MGMT_UNSUPPORTED (0x04000000) |
208 | #define MPI_SCSI_RSP_INFO_TASK_MGMT_FAILED (0x05000000) |
209 | #define MPI_SCSI_RSP_INFO_SPI_LQ_INVALID_TYPE (0x06000000) |
210 | |
211 | #define MPI_SCSI_TASKTAG_UNKNOWN (0xFFFF) |
212 | |
213 | |
214 | /****************************************************************************/ |
215 | /* SCSI IO 32 messages and associated structures */ |
216 | /****************************************************************************/ |
217 | |
218 | typedef struct |
219 | { |
220 | U8 CDB[20]; /* 00h */ |
221 | U32 PrimaryReferenceTag; /* 14h */ |
222 | U16 PrimaryApplicationTag; /* 18h */ |
223 | U16 PrimaryApplicationTagMask; /* 1Ah */ |
224 | U32 TransferLength; /* 1Ch */ |
225 | } MPI_SCSI_IO32_CDB_EEDP32, MPI_POINTER PTR_MPI_SCSI_IO32_CDB_EEDP32, |
226 | MpiScsiIo32CdbEedp32_t, MPI_POINTER pMpiScsiIo32CdbEedp32_t; |
227 | |
228 | typedef struct |
229 | { |
230 | U8 CDB[16]; /* 00h */ |
231 | U32 DataLength; /* 10h */ |
232 | U32 PrimaryReferenceTag; /* 14h */ |
233 | U16 PrimaryApplicationTag; /* 18h */ |
234 | U16 PrimaryApplicationTagMask; /* 1Ah */ |
235 | U32 TransferLength; /* 1Ch */ |
236 | } MPI_SCSI_IO32_CDB_EEDP16, MPI_POINTER PTR_MPI_SCSI_IO32_CDB_EEDP16, |
237 | MpiScsiIo32CdbEedp16_t, MPI_POINTER pMpiScsiIo32CdbEedp16_t; |
238 | |
239 | typedef union |
240 | { |
241 | U8 CDB32[32]; |
242 | MPI_SCSI_IO32_CDB_EEDP32 EEDP32; |
243 | MPI_SCSI_IO32_CDB_EEDP16 EEDP16; |
244 | SGE_SIMPLE_UNION SGE; |
245 | } MPI_SCSI_IO32_CDB_UNION, MPI_POINTER PTR_MPI_SCSI_IO32_CDB_UNION, |
246 | MpiScsiIo32Cdb_t, MPI_POINTER pMpiScsiIo32Cdb_t; |
247 | |
248 | typedef struct |
249 | { |
250 | U8 TargetID; /* 00h */ |
251 | U8 Bus; /* 01h */ |
252 | U16 Reserved1; /* 02h */ |
253 | U32 Reserved2; /* 04h */ |
254 | } MPI_SCSI_IO32_BUS_TARGET_ID_FORM, MPI_POINTER PTR_MPI_SCSI_IO32_BUS_TARGET_ID_FORM, |
255 | MpiScsiIo32BusTargetIdForm_t, MPI_POINTER pMpiScsiIo32BusTargetIdForm_t; |
256 | |
257 | typedef union |
258 | { |
259 | MPI_SCSI_IO32_BUS_TARGET_ID_FORM SCSIID; |
260 | U64 WWID; |
261 | } MPI_SCSI_IO32_ADDRESS, MPI_POINTER PTR_MPI_SCSI_IO32_ADDRESS, |
262 | MpiScsiIo32Address_t, MPI_POINTER pMpiScsiIo32Address_t; |
263 | |
264 | typedef struct _MSG_SCSI_IO32_REQUEST |
265 | { |
266 | U8 Port; /* 00h */ |
267 | U8 Reserved1; /* 01h */ |
268 | U8 ChainOffset; /* 02h */ |
269 | U8 Function; /* 03h */ |
270 | U8 CDBLength; /* 04h */ |
271 | U8 SenseBufferLength; /* 05h */ |
272 | U8 Flags; /* 06h */ |
273 | U8 MsgFlags; /* 07h */ |
274 | U32 MsgContext; /* 08h */ |
275 | U8 LUN[8]; /* 0Ch */ |
276 | U32 Control; /* 14h */ |
277 | MPI_SCSI_IO32_CDB_UNION CDB; /* 18h */ |
278 | U32 DataLength; /* 38h */ |
279 | U32 BidirectionalDataLength; /* 3Ch */ |
280 | U32 SecondaryReferenceTag; /* 40h */ |
281 | U16 SecondaryApplicationTag; /* 44h */ |
282 | U16 Reserved2; /* 46h */ |
283 | U16 EEDPFlags; /* 48h */ |
284 | U16 ApplicationTagTranslationMask; /* 4Ah */ |
285 | U32 EEDPBlockSize; /* 4Ch */ |
286 | MPI_SCSI_IO32_ADDRESS DeviceAddress; /* 50h */ |
287 | U8 SGLOffset0; /* 58h */ |
288 | U8 SGLOffset1; /* 59h */ |
289 | U8 SGLOffset2; /* 5Ah */ |
290 | U8 SGLOffset3; /* 5Bh */ |
291 | U32 Reserved3; /* 5Ch */ |
292 | U32 Reserved4; /* 60h */ |
293 | U32 SenseBufferLowAddr; /* 64h */ |
294 | SGE_IO_UNION SGL; /* 68h */ |
295 | } MSG_SCSI_IO32_REQUEST, MPI_POINTER PTR_MSG_SCSI_IO32_REQUEST, |
296 | SCSIIO32Request_t, MPI_POINTER pSCSIIO32Request_t; |
297 | |
298 | /* SCSI IO 32 MsgFlags bits */ |
299 | #define MPI_SCSIIO32_MSGFLGS_SENSE_WIDTH (0x01) |
300 | #define MPI_SCSIIO32_MSGFLGS_32_SENSE_WIDTH (0x00) |
301 | #define MPI_SCSIIO32_MSGFLGS_64_SENSE_WIDTH (0x01) |
302 | |
303 | #define MPI_SCSIIO32_MSGFLGS_SENSE_LOCATION (0x02) |
304 | #define MPI_SCSIIO32_MSGFLGS_SENSE_LOC_HOST (0x00) |
305 | #define MPI_SCSIIO32_MSGFLGS_SENSE_LOC_IOC (0x02) |
306 | |
307 | #define MPI_SCSIIO32_MSGFLGS_CMD_DETERMINES_DATA_DIR (0x04) |
308 | #define MPI_SCSIIO32_MSGFLGS_SGL_OFFSETS_CHAINS (0x08) |
309 | #define MPI_SCSIIO32_MSGFLGS_MULTICAST (0x10) |
310 | #define MPI_SCSIIO32_MSGFLGS_BIDIRECTIONAL (0x20) |
311 | #define MPI_SCSIIO32_MSGFLGS_LARGE_CDB (0x40) |
312 | |
313 | /* SCSI IO 32 Flags bits */ |
314 | #define MPI_SCSIIO32_FLAGS_FORM_MASK (0x03) |
315 | #define MPI_SCSIIO32_FLAGS_FORM_SCSIID (0x00) |
316 | #define MPI_SCSIIO32_FLAGS_FORM_WWID (0x01) |
317 | |
318 | /* SCSI IO 32 LUN fields */ |
319 | #define MPI_SCSIIO32_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) |
320 | #define MPI_SCSIIO32_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) |
321 | #define MPI_SCSIIO32_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) |
322 | #define MPI_SCSIIO32_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) |
323 | #define MPI_SCSIIO32_LUN_LEVEL_1_WORD (0xFF00) |
324 | #define MPI_SCSIIO32_LUN_LEVEL_1_DWORD (0x0000FF00) |
325 | |
326 | /* SCSI IO 32 Control bits */ |
327 | #define MPI_SCSIIO32_CONTROL_DATADIRECTION_MASK (0x03000000) |
328 | #define MPI_SCSIIO32_CONTROL_NODATATRANSFER (0x00000000) |
329 | #define MPI_SCSIIO32_CONTROL_WRITE (0x01000000) |
330 | #define MPI_SCSIIO32_CONTROL_READ (0x02000000) |
331 | #define MPI_SCSIIO32_CONTROL_BIDIRECTIONAL (0x03000000) |
332 | |
333 | #define MPI_SCSIIO32_CONTROL_ADDCDBLEN_MASK (0xFC000000) |
334 | #define MPI_SCSIIO32_CONTROL_ADDCDBLEN_SHIFT (26) |
335 | |
336 | #define MPI_SCSIIO32_CONTROL_TASKATTRIBUTE_MASK (0x00000700) |
337 | #define MPI_SCSIIO32_CONTROL_SIMPLEQ (0x00000000) |
338 | #define MPI_SCSIIO32_CONTROL_HEADOFQ (0x00000100) |
339 | #define MPI_SCSIIO32_CONTROL_ORDEREDQ (0x00000200) |
340 | #define MPI_SCSIIO32_CONTROL_ACAQ (0x00000400) |
341 | #define MPI_SCSIIO32_CONTROL_UNTAGGED (0x00000500) |
342 | #define MPI_SCSIIO32_CONTROL_NO_DISCONNECT (0x00000700) |
343 | |
344 | #define MPI_SCSIIO32_CONTROL_TASKMANAGE_MASK (0x00FF0000) |
345 | #define MPI_SCSIIO32_CONTROL_OBSOLETE (0x00800000) |
346 | #define MPI_SCSIIO32_CONTROL_CLEAR_ACA_RSV (0x00400000) |
347 | #define MPI_SCSIIO32_CONTROL_TARGET_RESET (0x00200000) |
348 | #define MPI_SCSIIO32_CONTROL_LUN_RESET_RSV (0x00100000) |
349 | #define MPI_SCSIIO32_CONTROL_RESERVED (0x00080000) |
350 | #define MPI_SCSIIO32_CONTROL_CLR_TASK_SET_RSV (0x00040000) |
351 | #define MPI_SCSIIO32_CONTROL_ABORT_TASK_SET (0x00020000) |
352 | #define MPI_SCSIIO32_CONTROL_RESERVED2 (0x00010000) |
353 | |
354 | /* SCSI IO 32 EEDPFlags */ |
355 | #define MPI_SCSIIO32_EEDPFLAGS_MASK_OP (0x0007) |
356 | #define MPI_SCSIIO32_EEDPFLAGS_NOOP_OP (0x0000) |
357 | #define MPI_SCSIIO32_EEDPFLAGS_CHK_OP (0x0001) |
358 | #define MPI_SCSIIO32_EEDPFLAGS_STRIP_OP (0x0002) |
359 | #define MPI_SCSIIO32_EEDPFLAGS_CHKRM_OP (0x0003) |
360 | #define MPI_SCSIIO32_EEDPFLAGS_INSERT_OP (0x0004) |
361 | #define MPI_SCSIIO32_EEDPFLAGS_REPLACE_OP (0x0006) |
362 | #define MPI_SCSIIO32_EEDPFLAGS_CHKREGEN_OP (0x0007) |
363 | |
364 | #define MPI_SCSIIO32_EEDPFLAGS_PASS_REF_TAG (0x0008) |
365 | #define MPI_SCSIIO32_EEDPFLAGS_8_9THS_MODE (0x0010) |
366 | |
367 | #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_MASK (0x0700) |
368 | #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_GUARD (0x0100) |
369 | #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_REFTAG (0x0200) |
370 | #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_LBATAG (0x0400) |
371 | #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_SHIFT (8) |
372 | |
373 | #define MPI_SCSIIO32_EEDPFLAGS_INC_SEC_APPTAG (0x1000) |
374 | #define MPI_SCSIIO32_EEDPFLAGS_INC_PRI_APPTAG (0x2000) |
375 | #define MPI_SCSIIO32_EEDPFLAGS_INC_SEC_REFTAG (0x4000) |
376 | #define MPI_SCSIIO32_EEDPFLAGS_INC_PRI_REFTAG (0x8000) |
377 | |
378 | |
379 | /* SCSIIO32 IO reply structure */ |
380 | typedef struct _MSG_SCSIIO32_IO_REPLY |
381 | { |
382 | U8 Port; /* 00h */ |
383 | U8 Reserved1; /* 01h */ |
384 | U8 MsgLength; /* 02h */ |
385 | U8 Function; /* 03h */ |
386 | U8 CDBLength; /* 04h */ |
387 | U8 SenseBufferLength; /* 05h */ |
388 | U8 Flags; /* 06h */ |
389 | U8 MsgFlags; /* 07h */ |
390 | U32 MsgContext; /* 08h */ |
391 | U8 SCSIStatus; /* 0Ch */ |
392 | U8 SCSIState; /* 0Dh */ |
393 | U16 IOCStatus; /* 0Eh */ |
394 | U32 IOCLogInfo; /* 10h */ |
395 | U32 TransferCount; /* 14h */ |
396 | U32 SenseCount; /* 18h */ |
397 | U32 ResponseInfo; /* 1Ch */ |
398 | U16 TaskTag; /* 20h */ |
399 | U16 Reserved2; /* 22h */ |
400 | U32 BidirectionalTransferCount; /* 24h */ |
401 | } MSG_SCSIIO32_IO_REPLY, MPI_POINTER PTR_MSG_SCSIIO32_IO_REPLY, |
402 | SCSIIO32Reply_t, MPI_POINTER pSCSIIO32Reply_t; |
403 | |
404 | |
405 | /****************************************************************************/ |
406 | /* SCSI Task Management messages */ |
407 | /****************************************************************************/ |
408 | |
409 | typedef struct _MSG_SCSI_TASK_MGMT |
410 | { |
411 | U8 TargetID; /* 00h */ |
412 | U8 Bus; /* 01h */ |
413 | U8 ChainOffset; /* 02h */ |
414 | U8 Function; /* 03h */ |
415 | U8 Reserved; /* 04h */ |
416 | U8 TaskType; /* 05h */ |
417 | U8 Reserved1; /* 06h */ |
418 | U8 MsgFlags; /* 07h */ |
419 | U32 MsgContext; /* 08h */ |
420 | U8 LUN[8]; /* 0Ch */ |
421 | U32 Reserved2[7]; /* 14h */ |
422 | U32 TaskMsgContext; /* 30h */ |
423 | } MSG_SCSI_TASK_MGMT, MPI_POINTER PTR_SCSI_TASK_MGMT, |
424 | SCSITaskMgmt_t, MPI_POINTER pSCSITaskMgmt_t; |
425 | |
426 | /* TaskType values */ |
427 | |
428 | #define MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) |
429 | #define MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02) |
430 | #define MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) |
431 | #define MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS (0x04) |
432 | #define MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) |
433 | #define MPI_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06) |
434 | #define MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07) |
435 | #define MPI_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08) |
436 | |
437 | /* MsgFlags bits */ |
438 | #define MPI_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x01) |
439 | |
440 | #define MPI_SCSITASKMGMT_MSGFLAGS_TARGET_RESET_OPTION (0x00) |
441 | #define MPI_SCSITASKMGMT_MSGFLAGS_LIP_RESET_OPTION (0x02) |
442 | #define MPI_SCSITASKMGMT_MSGFLAGS_LIPRESET_RESET_OPTION (0x04) |
443 | |
444 | #define MPI_SCSITASKMGMT_MSGFLAGS_SOFT_RESET_OPTION (0x08) |
445 | |
446 | /* SCSI Task Management Reply */ |
447 | typedef struct _MSG_SCSI_TASK_MGMT_REPLY |
448 | { |
449 | U8 TargetID; /* 00h */ |
450 | U8 Bus; /* 01h */ |
451 | U8 MsgLength; /* 02h */ |
452 | U8 Function; /* 03h */ |
453 | U8 ResponseCode; /* 04h */ |
454 | U8 TaskType; /* 05h */ |
455 | U8 Reserved1; /* 06h */ |
456 | U8 MsgFlags; /* 07h */ |
457 | U32 MsgContext; /* 08h */ |
458 | U8 Reserved2[2]; /* 0Ch */ |
459 | U16 IOCStatus; /* 0Eh */ |
460 | U32 IOCLogInfo; /* 10h */ |
461 | U32 TerminationCount; /* 14h */ |
462 | } MSG_SCSI_TASK_MGMT_REPLY, MPI_POINTER PTR_MSG_SCSI_TASK_MGMT_REPLY, |
463 | SCSITaskMgmtReply_t, MPI_POINTER pSCSITaskMgmtReply_t; |
464 | |
465 | /* ResponseCode values */ |
466 | #define MPI_SCSITASKMGMT_RSP_TM_COMPLETE (0x00) |
467 | #define MPI_SCSITASKMGMT_RSP_INVALID_FRAME (0x02) |
468 | #define MPI_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04) |
469 | #define MPI_SCSITASKMGMT_RSP_TM_FAILED (0x05) |
470 | #define MPI_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08) |
471 | #define MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09) |
472 | #define MPI_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80) |
473 | |
474 | |
475 | /****************************************************************************/ |
476 | /* SCSI Enclosure Processor messages */ |
477 | /****************************************************************************/ |
478 | |
479 | typedef struct _MSG_SEP_REQUEST |
480 | { |
481 | U8 TargetID; /* 00h */ |
482 | U8 Bus; /* 01h */ |
483 | U8 ChainOffset; /* 02h */ |
484 | U8 Function; /* 03h */ |
485 | U8 Action; /* 04h */ |
486 | U8 Flags; /* 05h */ |
487 | U8 Reserved1; /* 06h */ |
488 | U8 MsgFlags; /* 07h */ |
489 | U32 MsgContext; /* 08h */ |
490 | U32 SlotStatus; /* 0Ch */ |
491 | U32 Reserved2; /* 10h */ |
492 | U32 Reserved3; /* 14h */ |
493 | U32 Reserved4; /* 18h */ |
494 | U16 Slot; /* 1Ch */ |
495 | U16 EnclosureHandle; /* 1Eh */ |
496 | } MSG_SEP_REQUEST, MPI_POINTER PTR_MSG_SEP_REQUEST, |
497 | SEPRequest_t, MPI_POINTER pSEPRequest_t; |
498 | |
499 | /* Action defines */ |
500 | #define MPI_SEP_REQ_ACTION_WRITE_STATUS (0x00) |
501 | #define MPI_SEP_REQ_ACTION_READ_STATUS (0x01) |
502 | |
503 | /* Flags defines */ |
504 | #define MPI_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS (0x01) |
505 | #define MPI_SEP_REQ_FLAGS_BUS_TARGETID_ADDRESS (0x00) |
506 | |
507 | /* SlotStatus bits for MSG_SEP_REQUEST */ |
508 | #define MPI_SEP_REQ_SLOTSTATUS_NO_ERROR (0x00000001) |
509 | #define MPI_SEP_REQ_SLOTSTATUS_DEV_FAULTY (0x00000002) |
510 | #define MPI_SEP_REQ_SLOTSTATUS_DEV_REBUILDING (0x00000004) |
511 | #define MPI_SEP_REQ_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008) |
512 | #define MPI_SEP_REQ_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010) |
513 | #define MPI_SEP_REQ_SLOTSTATUS_PARITY_CHECK (0x00000020) |
514 | #define MPI_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT (0x00000040) |
515 | #define MPI_SEP_REQ_SLOTSTATUS_UNCONFIGURED (0x00000080) |
516 | #define MPI_SEP_REQ_SLOTSTATUS_HOT_SPARE (0x00000100) |
517 | #define MPI_SEP_REQ_SLOTSTATUS_REBUILD_STOPPED (0x00000200) |
518 | #define MPI_SEP_REQ_SLOTSTATUS_REQ_CONSISTENCY_CHECK (0x00001000) |
519 | #define MPI_SEP_REQ_SLOTSTATUS_DISABLE (0x00002000) |
520 | #define MPI_SEP_REQ_SLOTSTATUS_REQ_RESERVED_DEVICE (0x00004000) |
521 | #define MPI_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) |
522 | #define MPI_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE (0x00040000) |
523 | #define MPI_SEP_REQ_SLOTSTATUS_REQUEST_INSERT (0x00080000) |
524 | #define MPI_SEP_REQ_SLOTSTATUS_DO_NOT_MOVE (0x00400000) |
525 | #define MPI_SEP_REQ_SLOTSTATUS_ACTIVE (0x00800000) |
526 | #define MPI_SEP_REQ_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000) |
527 | #define MPI_SEP_REQ_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000) |
528 | #define MPI_SEP_REQ_SLOTSTATUS_DEV_OFF (0x10000000) |
529 | #define MPI_SEP_REQ_SLOTSTATUS_SWAP_RESET (0x80000000) |
530 | |
531 | |
532 | typedef struct _MSG_SEP_REPLY |
533 | { |
534 | U8 TargetID; /* 00h */ |
535 | U8 Bus; /* 01h */ |
536 | U8 MsgLength; /* 02h */ |
537 | U8 Function; /* 03h */ |
538 | U8 Action; /* 04h */ |
539 | U8 Reserved1; /* 05h */ |
540 | U8 Reserved2; /* 06h */ |
541 | U8 MsgFlags; /* 07h */ |
542 | U32 MsgContext; /* 08h */ |
543 | U16 Reserved3; /* 0Ch */ |
544 | U16 IOCStatus; /* 0Eh */ |
545 | U32 IOCLogInfo; /* 10h */ |
546 | U32 SlotStatus; /* 14h */ |
547 | U32 Reserved4; /* 18h */ |
548 | U16 Slot; /* 1Ch */ |
549 | U16 EnclosureHandle; /* 1Eh */ |
550 | } MSG_SEP_REPLY, MPI_POINTER PTR_MSG_SEP_REPLY, |
551 | SEPReply_t, MPI_POINTER pSEPReply_t; |
552 | |
553 | /* SlotStatus bits for MSG_SEP_REPLY */ |
554 | #define MPI_SEP_REPLY_SLOTSTATUS_NO_ERROR (0x00000001) |
555 | #define MPI_SEP_REPLY_SLOTSTATUS_DEV_FAULTY (0x00000002) |
556 | #define MPI_SEP_REPLY_SLOTSTATUS_DEV_REBUILDING (0x00000004) |
557 | #define MPI_SEP_REPLY_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008) |
558 | #define MPI_SEP_REPLY_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010) |
559 | #define MPI_SEP_REPLY_SLOTSTATUS_PARITY_CHECK (0x00000020) |
560 | #define MPI_SEP_REPLY_SLOTSTATUS_PREDICTED_FAULT (0x00000040) |
561 | #define MPI_SEP_REPLY_SLOTSTATUS_UNCONFIGURED (0x00000080) |
562 | #define MPI_SEP_REPLY_SLOTSTATUS_HOT_SPARE (0x00000100) |
563 | #define MPI_SEP_REPLY_SLOTSTATUS_REBUILD_STOPPED (0x00000200) |
564 | #define MPI_SEP_REPLY_SLOTSTATUS_CONSISTENCY_CHECK (0x00001000) |
565 | #define MPI_SEP_REPLY_SLOTSTATUS_DISABLE (0x00002000) |
566 | #define MPI_SEP_REPLY_SLOTSTATUS_RESERVED_DEVICE (0x00004000) |
567 | #define MPI_SEP_REPLY_SLOTSTATUS_REPORT (0x00010000) |
568 | #define MPI_SEP_REPLY_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) |
569 | #define MPI_SEP_REPLY_SLOTSTATUS_REMOVE_READY (0x00040000) |
570 | #define MPI_SEP_REPLY_SLOTSTATUS_INSERT_READY (0x00080000) |
571 | #define MPI_SEP_REPLY_SLOTSTATUS_DO_NOT_REMOVE (0x00400000) |
572 | #define MPI_SEP_REPLY_SLOTSTATUS_ACTIVE (0x00800000) |
573 | #define MPI_SEP_REPLY_SLOTSTATUS_B_BYPASS_ENABLED (0x01000000) |
574 | #define MPI_SEP_REPLY_SLOTSTATUS_A_BYPASS_ENABLED (0x02000000) |
575 | #define MPI_SEP_REPLY_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000) |
576 | #define MPI_SEP_REPLY_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000) |
577 | #define MPI_SEP_REPLY_SLOTSTATUS_DEV_OFF (0x10000000) |
578 | #define MPI_SEP_REPLY_SLOTSTATUS_FAULT_SENSED (0x40000000) |
579 | #define MPI_SEP_REPLY_SLOTSTATUS_SWAPPED (0x80000000) |
580 | |
581 | #endif |
582 | |