1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device access for Crystal Cove PMIC
4 *
5 * Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
6 *
7 * Author: Yang, Bin <bin.yang@intel.com>
8 * Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
9 */
10
11#include <linux/interrupt.h>
12#include <linux/regmap.h>
13#include <linux/mfd/core.h>
14#include <linux/mfd/intel_soc_pmic.h>
15
16#include "intel_soc_pmic_core.h"
17
18#define CRYSTAL_COVE_MAX_REGISTER 0xC6
19
20#define CRYSTAL_COVE_REG_IRQLVL1 0x02
21#define CRYSTAL_COVE_REG_MIRQLVL1 0x0E
22
23#define CRYSTAL_COVE_IRQ_PWRSRC 0
24#define CRYSTAL_COVE_IRQ_THRM 1
25#define CRYSTAL_COVE_IRQ_BCU 2
26#define CRYSTAL_COVE_IRQ_ADC 3
27#define CRYSTAL_COVE_IRQ_CHGR 4
28#define CRYSTAL_COVE_IRQ_GPIO 5
29#define CRYSTAL_COVE_IRQ_VHDMIOCP 6
30
31static struct resource gpio_resources[] = {
32 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_GPIO, "GPIO"),
33};
34
35static struct resource pwrsrc_resources[] = {
36 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_PWRSRC, "PWRSRC"),
37};
38
39static struct resource adc_resources[] = {
40 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_ADC, "ADC"),
41};
42
43static struct resource thermal_resources[] = {
44 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_THRM, "THERMAL"),
45};
46
47static struct resource bcu_resources[] = {
48 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_BCU, "BCU"),
49};
50
51static struct mfd_cell crystal_cove_byt_dev[] = {
52 {
53 .name = "crystal_cove_pwrsrc",
54 .num_resources = ARRAY_SIZE(pwrsrc_resources),
55 .resources = pwrsrc_resources,
56 },
57 {
58 .name = "crystal_cove_adc",
59 .num_resources = ARRAY_SIZE(adc_resources),
60 .resources = adc_resources,
61 },
62 {
63 .name = "crystal_cove_thermal",
64 .num_resources = ARRAY_SIZE(thermal_resources),
65 .resources = thermal_resources,
66 },
67 {
68 .name = "crystal_cove_bcu",
69 .num_resources = ARRAY_SIZE(bcu_resources),
70 .resources = bcu_resources,
71 },
72 {
73 .name = "crystal_cove_gpio",
74 .num_resources = ARRAY_SIZE(gpio_resources),
75 .resources = gpio_resources,
76 },
77 {
78 .name = "crystal_cove_pmic",
79 },
80 {
81 .name = "crystal_cove_pwm",
82 },
83};
84
85static struct mfd_cell crystal_cove_cht_dev[] = {
86 {
87 .name = "crystal_cove_gpio",
88 .num_resources = ARRAY_SIZE(gpio_resources),
89 .resources = gpio_resources,
90 },
91 {
92 .name = "crystal_cove_pwm",
93 },
94};
95
96static const struct regmap_config crystal_cove_regmap_config = {
97 .reg_bits = 8,
98 .val_bits = 8,
99
100 .max_register = CRYSTAL_COVE_MAX_REGISTER,
101 .cache_type = REGCACHE_NONE,
102};
103
104static const struct regmap_irq crystal_cove_irqs[] = {
105 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_PWRSRC, 0, BIT(CRYSTAL_COVE_IRQ_PWRSRC)),
106 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_THRM, 0, BIT(CRYSTAL_COVE_IRQ_THRM)),
107 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_BCU, 0, BIT(CRYSTAL_COVE_IRQ_BCU)),
108 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_ADC, 0, BIT(CRYSTAL_COVE_IRQ_ADC)),
109 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_CHGR, 0, BIT(CRYSTAL_COVE_IRQ_CHGR)),
110 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_GPIO, 0, BIT(CRYSTAL_COVE_IRQ_GPIO)),
111 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_VHDMIOCP, 0, BIT(CRYSTAL_COVE_IRQ_VHDMIOCP)),
112};
113
114static const struct regmap_irq_chip crystal_cove_irq_chip = {
115 .name = "Crystal Cove",
116 .irqs = crystal_cove_irqs,
117 .num_irqs = ARRAY_SIZE(crystal_cove_irqs),
118 .num_regs = 1,
119 .status_base = CRYSTAL_COVE_REG_IRQLVL1,
120 .mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
121};
122
123struct intel_soc_pmic_config intel_soc_pmic_config_byt_crc = {
124 .irq_flags = IRQF_TRIGGER_RISING,
125 .cell_dev = crystal_cove_byt_dev,
126 .n_cell_devs = ARRAY_SIZE(crystal_cove_byt_dev),
127 .regmap_config = &crystal_cove_regmap_config,
128 .irq_chip = &crystal_cove_irq_chip,
129};
130
131struct intel_soc_pmic_config intel_soc_pmic_config_cht_crc = {
132 .irq_flags = IRQF_TRIGGER_RISING,
133 .cell_dev = crystal_cove_cht_dev,
134 .n_cell_devs = ARRAY_SIZE(crystal_cove_cht_dev),
135 .regmap_config = &crystal_cove_regmap_config,
136 .irq_chip = &crystal_cove_irq_chip,
137};
138