| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * timberdale.h timberdale FPGA MFD driver defines |
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| 4 | * Copyright (c) 2009 Intel Corporation |
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| 5 | */ |
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| 6 | |
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| 7 | /* Supports: |
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| 8 | * Timberdale FPGA |
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| 9 | */ |
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| 10 | |
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| 11 | #ifndef MFD_TIMBERDALE_H |
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| 12 | #define MFD_TIMBERDALE_H |
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| 13 | |
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| 14 | #define DRV_VERSION "0.3" |
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| 15 | |
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| 16 | /* This driver only support versions >= 3.8 and < 4.0 */ |
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| 17 | #define TIMB_SUPPORTED_MAJOR 3 |
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| 18 | |
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| 19 | /* This driver only support minor >= 8 */ |
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| 20 | #define TIMB_REQUIRED_MINOR 8 |
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| 21 | |
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| 22 | /* Registers of the control area */ |
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| 23 | #define TIMB_REV_MAJOR 0x00 |
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| 24 | #define TIMB_REV_MINOR 0x04 |
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| 25 | #define TIMB_HW_CONFIG 0x08 |
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| 26 | #define TIMB_SW_RST 0x40 |
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| 27 | |
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| 28 | /* bits in the TIMB_HW_CONFIG register */ |
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| 29 | #define TIMB_HW_CONFIG_SPI_8BIT 0x80 |
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| 30 | |
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| 31 | #define TIMB_HW_VER_MASK 0x0f |
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| 32 | #define TIMB_HW_VER0 0x00 |
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| 33 | #define TIMB_HW_VER1 0x01 |
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| 34 | #define TIMB_HW_VER2 0x02 |
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| 35 | #define TIMB_HW_VER3 0x03 |
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| 36 | |
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| 37 | #define OCORESOFFSET 0x0 |
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| 38 | #define OCORESEND 0x1f |
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| 39 | |
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| 40 | #define SPIOFFSET 0x80 |
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| 41 | #define SPIEND 0xff |
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| 42 | |
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| 43 | #define UARTLITEOFFSET 0x100 |
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| 44 | #define UARTLITEEND 0x10f |
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| 45 | |
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| 46 | #define RDSOFFSET 0x180 |
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| 47 | #define RDSEND 0x183 |
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| 48 | |
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| 49 | #define ETHOFFSET 0x300 |
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| 50 | #define ETHEND 0x3ff |
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| 51 | |
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| 52 | #define GPIOOFFSET 0x400 |
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| 53 | #define GPIOEND 0x7ff |
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| 54 | |
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| 55 | #define CHIPCTLOFFSET 0x800 |
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| 56 | #define CHIPCTLEND 0x8ff |
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| 57 | #define CHIPCTLSIZE (CHIPCTLEND - CHIPCTLOFFSET + 1) |
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| 58 | |
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| 59 | #define INTCOFFSET 0xc00 |
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| 60 | #define INTCEND 0xfff |
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| 61 | #define INTCSIZE (INTCEND - INTCOFFSET) |
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| 62 | |
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| 63 | #define MOSTOFFSET 0x1000 |
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| 64 | #define MOSTEND 0x13ff |
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| 65 | |
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| 66 | #define UARTOFFSET 0x1400 |
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| 67 | #define UARTEND 0x17ff |
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| 68 | |
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| 69 | #define XIICOFFSET 0x1800 |
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| 70 | #define XIICEND 0x19ff |
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| 71 | |
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| 72 | #define I2SOFFSET 0x1C00 |
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| 73 | #define I2SEND 0x1fff |
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| 74 | |
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| 75 | #define LOGIWOFFSET 0x30000 |
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| 76 | #define LOGIWEND 0x37fff |
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| 77 | |
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| 78 | #define MLCOREOFFSET 0x40000 |
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| 79 | #define MLCOREEND 0x43fff |
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| 80 | |
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| 81 | #define DMAOFFSET 0x01000000 |
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| 82 | #define DMAEND 0x013fffff |
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| 83 | |
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| 84 | /* SDHC0 is placed in PCI bar 1 */ |
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| 85 | #define SDHC0OFFSET 0x00 |
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| 86 | #define SDHC0END 0xff |
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| 87 | |
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| 88 | /* SDHC1 is placed in PCI bar 2 */ |
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| 89 | #define SDHC1OFFSET 0x00 |
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| 90 | #define SDHC1END 0xff |
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| 91 | |
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| 92 | #define PCI_VENDOR_ID_TIMB 0x10ee |
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| 93 | #define PCI_DEVICE_ID_TIMB 0xa123 |
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| 94 | |
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| 95 | #define IRQ_TIMBERDALE_INIC 0 |
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| 96 | #define IRQ_TIMBERDALE_MLB 1 |
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| 97 | #define IRQ_TIMBERDALE_GPIO 2 |
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| 98 | #define IRQ_TIMBERDALE_I2C 3 |
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| 99 | #define IRQ_TIMBERDALE_UART 4 |
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| 100 | #define IRQ_TIMBERDALE_DMA 5 |
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| 101 | #define IRQ_TIMBERDALE_I2S 6 |
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| 102 | #define IRQ_TIMBERDALE_TSC_INT 7 |
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| 103 | #define IRQ_TIMBERDALE_SDHC 8 |
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| 104 | #define IRQ_TIMBERDALE_ADV7180 9 |
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| 105 | #define IRQ_TIMBERDALE_ETHSW_IF 10 |
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| 106 | #define IRQ_TIMBERDALE_SPI 11 |
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| 107 | #define IRQ_TIMBERDALE_UARTLITE 12 |
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| 108 | #define IRQ_TIMBERDALE_MLCORE 13 |
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| 109 | #define IRQ_TIMBERDALE_MLCORE_BUF 14 |
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| 110 | #define IRQ_TIMBERDALE_RDS 15 |
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| 111 | #define TIMBERDALE_NR_IRQS 16 |
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| 112 | |
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| 113 | #define GPIO_PIN_ASCB 8 |
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| 114 | #define GPIO_PIN_INIC_RST 14 |
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| 115 | #define GPIO_PIN_BT_RST 15 |
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| 116 | #define GPIO_NR_PINS 16 |
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| 117 | |
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| 118 | /* DMA Channels */ |
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| 119 | #define DMA_UART_RX 0 |
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| 120 | #define DMA_UART_TX 1 |
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| 121 | #define DMA_MLB_RX 2 |
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| 122 | #define DMA_MLB_TX 3 |
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| 123 | #define DMA_VIDEO_RX 4 |
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| 124 | #define DMA_VIDEO_DROP 5 |
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| 125 | #define DMA_SDHCI_RX 6 |
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| 126 | #define DMA_SDHCI_TX 7 |
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| 127 | #define DMA_ETH_RX 8 |
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| 128 | #define DMA_ETH_TX 9 |
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| 129 | |
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| 130 | #endif |
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| 131 | |
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