1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * wm8994-regmap.c -- Register map data for WM8994 series devices |
4 | * |
5 | * Copyright 2011 Wolfson Microelectronics PLC. |
6 | * |
7 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> |
8 | */ |
9 | |
10 | #include <linux/mfd/wm8994/core.h> |
11 | #include <linux/mfd/wm8994/registers.h> |
12 | #include <linux/regmap.h> |
13 | #include <linux/device.h> |
14 | |
15 | #include "wm8994.h" |
16 | |
17 | static const struct reg_default wm1811_defaults[] = { |
18 | { 0x0001, 0x0000 }, /* R1 - Power Management (1) */ |
19 | { 0x0002, 0x6000 }, /* R2 - Power Management (2) */ |
20 | { 0x0003, 0x0000 }, /* R3 - Power Management (3) */ |
21 | { 0x0004, 0x0000 }, /* R4 - Power Management (4) */ |
22 | { 0x0005, 0x0000 }, /* R5 - Power Management (5) */ |
23 | { 0x0006, 0x0000 }, /* R6 - Power Management (6) */ |
24 | { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */ |
25 | { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */ |
26 | { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */ |
27 | { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */ |
28 | { 0x001B, 0x008B }, /* R27 - Right Line Input 3&4 Volume */ |
29 | { 0x001C, 0x006D }, /* R28 - Left Output Volume */ |
30 | { 0x001D, 0x006D }, /* R29 - Right Output Volume */ |
31 | { 0x001E, 0x0066 }, /* R30 - Line Outputs Volume */ |
32 | { 0x001F, 0x0020 }, /* R31 - HPOUT2 Volume */ |
33 | { 0x0020, 0x0079 }, /* R32 - Left OPGA Volume */ |
34 | { 0x0021, 0x0079 }, /* R33 - Right OPGA Volume */ |
35 | { 0x0022, 0x0003 }, /* R34 - SPKMIXL Attenuation */ |
36 | { 0x0023, 0x0003 }, /* R35 - SPKMIXR Attenuation */ |
37 | { 0x0024, 0x0011 }, /* R36 - SPKOUT Mixers */ |
38 | { 0x0025, 0x0140 }, /* R37 - ClassD */ |
39 | { 0x0026, 0x0079 }, /* R38 - Speaker Volume Left */ |
40 | { 0x0027, 0x0079 }, /* R39 - Speaker Volume Right */ |
41 | { 0x0028, 0x0000 }, /* R40 - Input Mixer (2) */ |
42 | { 0x0029, 0x0000 }, /* R41 - Input Mixer (3) */ |
43 | { 0x002A, 0x0000 }, /* R42 - Input Mixer (4) */ |
44 | { 0x002B, 0x0000 }, /* R43 - Input Mixer (5) */ |
45 | { 0x002C, 0x0000 }, /* R44 - Input Mixer (6) */ |
46 | { 0x002D, 0x0000 }, /* R45 - Output Mixer (1) */ |
47 | { 0x002E, 0x0000 }, /* R46 - Output Mixer (2) */ |
48 | { 0x002F, 0x0000 }, /* R47 - Output Mixer (3) */ |
49 | { 0x0030, 0x0000 }, /* R48 - Output Mixer (4) */ |
50 | { 0x0031, 0x0000 }, /* R49 - Output Mixer (5) */ |
51 | { 0x0032, 0x0000 }, /* R50 - Output Mixer (6) */ |
52 | { 0x0033, 0x0000 }, /* R51 - HPOUT2 Mixer */ |
53 | { 0x0034, 0x0000 }, /* R52 - Line Mixer (1) */ |
54 | { 0x0035, 0x0000 }, /* R53 - Line Mixer (2) */ |
55 | { 0x0036, 0x0000 }, /* R54 - Speaker Mixer */ |
56 | { 0x0037, 0x0000 }, /* R55 - Additional Control */ |
57 | { 0x0038, 0x0000 }, /* R56 - AntiPOP (1) */ |
58 | { 0x0039, 0x0000 }, /* R57 - AntiPOP (2) */ |
59 | { 0x003B, 0x000D }, /* R59 - LDO 1 */ |
60 | { 0x003C, 0x0003 }, /* R60 - LDO 2 */ |
61 | { 0x003D, 0x0039 }, /* R61 - MICBIAS1 */ |
62 | { 0x003E, 0x0039 }, /* R62 - MICBIAS2 */ |
63 | { 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */ |
64 | { 0x004D, 0xAB19 }, /* R77 - Charge Pump (2) */ |
65 | { 0x0051, 0x0004 }, /* R81 - Class W (1) */ |
66 | { 0x0055, 0x054A }, /* R85 - DC Servo (2) */ |
67 | { 0x0059, 0x0000 }, /* R89 - DC Servo (4) */ |
68 | { 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */ |
69 | { 0x00C5, 0x0000 }, /* R197 - Class D Test (5) */ |
70 | { 0x00D0, 0x7600 }, /* R208 - Mic Detect 1 */ |
71 | { 0x00D1, 0x007F }, /* R209 - Mic Detect 2 */ |
72 | { 0x0101, 0x8004 }, /* R257 - Control Interface */ |
73 | { 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */ |
74 | { 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */ |
75 | { 0x0204, 0x0000 }, /* R516 - AIF2 Clocking (1) */ |
76 | { 0x0205, 0x0000 }, /* R517 - AIF2 Clocking (2) */ |
77 | { 0x0208, 0x0000 }, /* R520 - Clocking (1) */ |
78 | { 0x0209, 0x0000 }, /* R521 - Clocking (2) */ |
79 | { 0x0210, 0x0083 }, /* R528 - AIF1 Rate */ |
80 | { 0x0211, 0x0083 }, /* R529 - AIF2 Rate */ |
81 | { 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */ |
82 | { 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */ |
83 | { 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */ |
84 | { 0x0223, 0x0000 }, /* R547 - FLL1 Control (4) */ |
85 | { 0x0224, 0x0C80 }, /* R548 - FLL1 Control (5) */ |
86 | { 0x0226, 0x0000 }, /* R550 - FLL1 EFS 1 */ |
87 | { 0x0227, 0x0006 }, /* R551 - FLL1 EFS 2 */ |
88 | { 0x0240, 0x0000 }, /* R576 - FLL2Control (1) */ |
89 | { 0x0241, 0x0000 }, /* R577 - FLL2Control (2) */ |
90 | { 0x0242, 0x0000 }, /* R578 - FLL2Control (3) */ |
91 | { 0x0243, 0x0000 }, /* R579 - FLL2 Control (4) */ |
92 | { 0x0244, 0x0C80 }, /* R580 - FLL2Control (5) */ |
93 | { 0x0246, 0x0000 }, /* R582 - FLL2 EFS 1 */ |
94 | { 0x0247, 0x0006 }, /* R583 - FLL2 EFS 2 */ |
95 | { 0x0300, 0x4050 }, /* R768 - AIF1 Control (1) */ |
96 | { 0x0301, 0x4000 }, /* R769 - AIF1 Control (2) */ |
97 | { 0x0302, 0x0000 }, /* R770 - AIF1 Master/Slave */ |
98 | { 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */ |
99 | { 0x0304, 0x0040 }, /* R772 - AIF1ADC LRCLK */ |
100 | { 0x0305, 0x0040 }, /* R773 - AIF1DAC LRCLK */ |
101 | { 0x0306, 0x0004 }, /* R774 - AIF1DAC Data */ |
102 | { 0x0307, 0x0100 }, /* R775 - AIF1ADC Data */ |
103 | { 0x0310, 0x4050 }, /* R784 - AIF2 Control (1) */ |
104 | { 0x0311, 0x4000 }, /* R785 - AIF2 Control (2) */ |
105 | { 0x0312, 0x0000 }, /* R786 - AIF2 Master/Slave */ |
106 | { 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */ |
107 | { 0x0314, 0x0040 }, /* R788 - AIF2ADC LRCLK */ |
108 | { 0x0315, 0x0040 }, /* R789 - AIF2DAC LRCLK */ |
109 | { 0x0316, 0x0000 }, /* R790 - AIF2DAC Data */ |
110 | { 0x0317, 0x0000 }, /* R791 - AIF2ADC Data */ |
111 | { 0x0318, 0x0003 }, /* R792 - AIF2TX Control */ |
112 | { 0x0320, 0x0040 }, /* R800 - AIF3 Control (1) */ |
113 | { 0x0321, 0x0000 }, /* R801 - AIF3 Control (2) */ |
114 | { 0x0322, 0x0000 }, /* R802 - AIF3DAC Data */ |
115 | { 0x0323, 0x0000 }, /* R803 - AIF3ADC Data */ |
116 | { 0x0400, 0x00C0 }, /* R1024 - AIF1 ADC1 Left Volume */ |
117 | { 0x0401, 0x00C0 }, /* R1025 - AIF1 ADC1 Right Volume */ |
118 | { 0x0402, 0x00C0 }, /* R1026 - AIF1 DAC1 Left Volume */ |
119 | { 0x0403, 0x00C0 }, /* R1027 - AIF1 DAC1 Right Volume */ |
120 | { 0x0410, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */ |
121 | { 0x0411, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */ |
122 | { 0x0420, 0x0200 }, /* R1056 - AIF1 DAC1 Filters (1) */ |
123 | { 0x0421, 0x0010 }, /* R1057 - AIF1 DAC1 Filters (2) */ |
124 | { 0x0422, 0x0200 }, /* R1058 - AIF1 DAC2 Filters (1) */ |
125 | { 0x0423, 0x0010 }, /* R1059 - AIF1 DAC2 Filters (2) */ |
126 | { 0x0430, 0x0068 }, /* R1072 - AIF1 DAC1 Noise Gate */ |
127 | { 0x0431, 0x0068 }, /* R1073 - AIF1 DAC2 Noise Gate */ |
128 | { 0x0440, 0x0098 }, /* R1088 - AIF1 DRC1 (1) */ |
129 | { 0x0441, 0x0845 }, /* R1089 - AIF1 DRC1 (2) */ |
130 | { 0x0442, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */ |
131 | { 0x0443, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */ |
132 | { 0x0444, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */ |
133 | { 0x0450, 0x0098 }, /* R1104 - AIF1 DRC2 (1) */ |
134 | { 0x0451, 0x0845 }, /* R1105 - AIF1 DRC2 (2) */ |
135 | { 0x0452, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */ |
136 | { 0x0453, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */ |
137 | { 0x0454, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */ |
138 | { 0x0480, 0x6318 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */ |
139 | { 0x0481, 0x6300 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */ |
140 | { 0x0482, 0x0FCA }, /* R1154 - AIF1 DAC1 EQ Band 1 A */ |
141 | { 0x0483, 0x0400 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */ |
142 | { 0x0484, 0x00D8 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */ |
143 | { 0x0485, 0x1EB5 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */ |
144 | { 0x0486, 0xF145 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */ |
145 | { 0x0487, 0x0B75 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */ |
146 | { 0x0488, 0x01C5 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */ |
147 | { 0x0489, 0x1C58 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */ |
148 | { 0x048A, 0xF373 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */ |
149 | { 0x048B, 0x0A54 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */ |
150 | { 0x048C, 0x0558 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */ |
151 | { 0x048D, 0x168E }, /* R1165 - AIF1 DAC1 EQ Band 4 A */ |
152 | { 0x048E, 0xF829 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */ |
153 | { 0x048F, 0x07AD }, /* R1167 - AIF1 DAC1 EQ Band 4 C */ |
154 | { 0x0490, 0x1103 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */ |
155 | { 0x0491, 0x0564 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */ |
156 | { 0x0492, 0x0559 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */ |
157 | { 0x0493, 0x4000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */ |
158 | { 0x0494, 0x0000 }, /* R1172 - AIF1 DAC1 EQ Band 1 C */ |
159 | { 0x04A0, 0x6318 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */ |
160 | { 0x04A1, 0x6300 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */ |
161 | { 0x04A2, 0x0FCA }, /* R1186 - AIF1 DAC2 EQ Band 1 A */ |
162 | { 0x04A3, 0x0400 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */ |
163 | { 0x04A4, 0x00D8 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */ |
164 | { 0x04A5, 0x1EB5 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */ |
165 | { 0x04A6, 0xF145 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */ |
166 | { 0x04A7, 0x0B75 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */ |
167 | { 0x04A8, 0x01C5 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */ |
168 | { 0x04A9, 0x1C58 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */ |
169 | { 0x04AA, 0xF373 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */ |
170 | { 0x04AB, 0x0A54 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */ |
171 | { 0x04AC, 0x0558 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */ |
172 | { 0x04AD, 0x168E }, /* R1197 - AIF1 DAC2 EQ Band 4 A */ |
173 | { 0x04AE, 0xF829 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */ |
174 | { 0x04AF, 0x07AD }, /* R1199 - AIF1 DAC2 EQ Band 4 C */ |
175 | { 0x04B0, 0x1103 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */ |
176 | { 0x04B1, 0x0564 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */ |
177 | { 0x04B2, 0x0559 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */ |
178 | { 0x04B3, 0x4000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */ |
179 | { 0x04B4, 0x0000 }, /* R1204 - AIF1 DAC2 EQ Band 1 C */ |
180 | { 0x0500, 0x00C0 }, /* R1280 - AIF2 ADC Left Volume */ |
181 | { 0x0501, 0x00C0 }, /* R1281 - AIF2 ADC Right Volume */ |
182 | { 0x0502, 0x00C0 }, /* R1282 - AIF2 DAC Left Volume */ |
183 | { 0x0503, 0x00C0 }, /* R1283 - AIF2 DAC Right Volume */ |
184 | { 0x0510, 0x0000 }, /* R1296 - AIF2 ADC Filters */ |
185 | { 0x0520, 0x0200 }, /* R1312 - AIF2 DAC Filters (1) */ |
186 | { 0x0521, 0x0010 }, /* R1313 - AIF2 DAC Filters (2) */ |
187 | { 0x0530, 0x0068 }, /* R1328 - AIF2 DAC Noise Gate */ |
188 | { 0x0540, 0x0098 }, /* R1344 - AIF2 DRC (1) */ |
189 | { 0x0541, 0x0845 }, /* R1345 - AIF2 DRC (2) */ |
190 | { 0x0542, 0x0000 }, /* R1346 - AIF2 DRC (3) */ |
191 | { 0x0543, 0x0000 }, /* R1347 - AIF2 DRC (4) */ |
192 | { 0x0544, 0x0000 }, /* R1348 - AIF2 DRC (5) */ |
193 | { 0x0580, 0x6318 }, /* R1408 - AIF2 EQ Gains (1) */ |
194 | { 0x0581, 0x6300 }, /* R1409 - AIF2 EQ Gains (2) */ |
195 | { 0x0582, 0x0FCA }, /* R1410 - AIF2 EQ Band 1 A */ |
196 | { 0x0583, 0x0400 }, /* R1411 - AIF2 EQ Band 1 B */ |
197 | { 0x0584, 0x00D8 }, /* R1412 - AIF2 EQ Band 1 PG */ |
198 | { 0x0585, 0x1EB5 }, /* R1413 - AIF2 EQ Band 2 A */ |
199 | { 0x0586, 0xF145 }, /* R1414 - AIF2 EQ Band 2 B */ |
200 | { 0x0587, 0x0B75 }, /* R1415 - AIF2 EQ Band 2 C */ |
201 | { 0x0588, 0x01C5 }, /* R1416 - AIF2 EQ Band 2 PG */ |
202 | { 0x0589, 0x1C58 }, /* R1417 - AIF2 EQ Band 3 A */ |
203 | { 0x058A, 0xF373 }, /* R1418 - AIF2 EQ Band 3 B */ |
204 | { 0x058B, 0x0A54 }, /* R1419 - AIF2 EQ Band 3 C */ |
205 | { 0x058C, 0x0558 }, /* R1420 - AIF2 EQ Band 3 PG */ |
206 | { 0x058D, 0x168E }, /* R1421 - AIF2 EQ Band 4 A */ |
207 | { 0x058E, 0xF829 }, /* R1422 - AIF2 EQ Band 4 B */ |
208 | { 0x058F, 0x07AD }, /* R1423 - AIF2 EQ Band 4 C */ |
209 | { 0x0590, 0x1103 }, /* R1424 - AIF2 EQ Band 4 PG */ |
210 | { 0x0591, 0x0564 }, /* R1425 - AIF2 EQ Band 5 A */ |
211 | { 0x0592, 0x0559 }, /* R1426 - AIF2 EQ Band 5 B */ |
212 | { 0x0593, 0x4000 }, /* R1427 - AIF2 EQ Band 5 PG */ |
213 | { 0x0594, 0x0000 }, /* R1428 - AIF2 EQ Band 1 C */ |
214 | { 0x0600, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */ |
215 | { 0x0601, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */ |
216 | { 0x0602, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */ |
217 | { 0x0603, 0x0000 }, /* R1539 - AIF2ADC Mixer Volumes */ |
218 | { 0x0604, 0x0000 }, /* R1540 - AIF2ADC Left Mixer Routing */ |
219 | { 0x0605, 0x0000 }, /* R1541 - AIF2ADC Right Mixer Routing */ |
220 | { 0x0606, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */ |
221 | { 0x0607, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */ |
222 | { 0x0608, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */ |
223 | { 0x0609, 0x0000 }, /* R1545 - AIF1 ADC2 Right Mixer Routing */ |
224 | { 0x0610, 0x02C0 }, /* R1552 - DAC1 Left Volume */ |
225 | { 0x0611, 0x02C0 }, /* R1553 - DAC1 Right Volume */ |
226 | { 0x0612, 0x02C0 }, /* R1554 - AIF2TX Left Volume */ |
227 | { 0x0613, 0x02C0 }, /* R1555 - AIF2TX Right Volume */ |
228 | { 0x0614, 0x0000 }, /* R1556 - DAC Softmute */ |
229 | { 0x0620, 0x0002 }, /* R1568 - Oversampling */ |
230 | { 0x0621, 0x0000 }, /* R1569 - Sidetone */ |
231 | { 0x0700, 0x8100 }, /* R1792 - GPIO 1 */ |
232 | { 0x0701, 0xA101 }, /* R1793 - Pull Control (MCLK2) */ |
233 | { 0x0702, 0xA101 }, /* R1794 - Pull Control (BCLK2) */ |
234 | { 0x0703, 0xA101 }, /* R1795 - Pull Control (DACLRCLK2) */ |
235 | { 0x0704, 0xA101 }, /* R1796 - Pull Control (DACDAT2) */ |
236 | { 0x0707, 0xA101 }, /* R1799 - GPIO 8 */ |
237 | { 0x0708, 0xA101 }, /* R1800 - GPIO 9 */ |
238 | { 0x0709, 0xA101 }, /* R1801 - GPIO 10 */ |
239 | { 0x070A, 0xA101 }, /* R1802 - GPIO 11 */ |
240 | { 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */ |
241 | { 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */ |
242 | { 0x0732, 0x0000 }, /* R1842 - Interrupt Raw Status 2 */ |
243 | { 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */ |
244 | { 0x0739, 0xDFEF }, /* R1849 - Interrupt Status 2 Mask */ |
245 | { 0x0740, 0x0000 }, /* R1856 - Interrupt Control */ |
246 | { 0x0748, 0x003F }, /* R1864 - IRQ Debounce */ |
247 | }; |
248 | |
249 | static const struct reg_default wm8994_defaults[] = { |
250 | { 0x0001, 0x0000 }, /* R1 - Power Management (1) */ |
251 | { 0x0002, 0x6000 }, /* R2 - Power Management (2) */ |
252 | { 0x0003, 0x0000 }, /* R3 - Power Management (3) */ |
253 | { 0x0004, 0x0000 }, /* R4 - Power Management (4) */ |
254 | { 0x0005, 0x0000 }, /* R5 - Power Management (5) */ |
255 | { 0x0006, 0x0000 }, /* R6 - Power Management (6) */ |
256 | { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */ |
257 | { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */ |
258 | { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */ |
259 | { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */ |
260 | { 0x001B, 0x008B }, /* R27 - Right Line Input 3&4 Volume */ |
261 | { 0x001C, 0x006D }, /* R28 - Left Output Volume */ |
262 | { 0x001D, 0x006D }, /* R29 - Right Output Volume */ |
263 | { 0x001E, 0x0066 }, /* R30 - Line Outputs Volume */ |
264 | { 0x001F, 0x0020 }, /* R31 - HPOUT2 Volume */ |
265 | { 0x0020, 0x0079 }, /* R32 - Left OPGA Volume */ |
266 | { 0x0021, 0x0079 }, /* R33 - Right OPGA Volume */ |
267 | { 0x0022, 0x0003 }, /* R34 - SPKMIXL Attenuation */ |
268 | { 0x0023, 0x0003 }, /* R35 - SPKMIXR Attenuation */ |
269 | { 0x0024, 0x0011 }, /* R36 - SPKOUT Mixers */ |
270 | { 0x0025, 0x0140 }, /* R37 - ClassD */ |
271 | { 0x0026, 0x0079 }, /* R38 - Speaker Volume Left */ |
272 | { 0x0027, 0x0079 }, /* R39 - Speaker Volume Right */ |
273 | { 0x0028, 0x0000 }, /* R40 - Input Mixer (2) */ |
274 | { 0x0029, 0x0000 }, /* R41 - Input Mixer (3) */ |
275 | { 0x002A, 0x0000 }, /* R42 - Input Mixer (4) */ |
276 | { 0x002B, 0x0000 }, /* R43 - Input Mixer (5) */ |
277 | { 0x002C, 0x0000 }, /* R44 - Input Mixer (6) */ |
278 | { 0x002D, 0x0000 }, /* R45 - Output Mixer (1) */ |
279 | { 0x002E, 0x0000 }, /* R46 - Output Mixer (2) */ |
280 | { 0x002F, 0x0000 }, /* R47 - Output Mixer (3) */ |
281 | { 0x0030, 0x0000 }, /* R48 - Output Mixer (4) */ |
282 | { 0x0031, 0x0000 }, /* R49 - Output Mixer (5) */ |
283 | { 0x0032, 0x0000 }, /* R50 - Output Mixer (6) */ |
284 | { 0x0033, 0x0000 }, /* R51 - HPOUT2 Mixer */ |
285 | { 0x0034, 0x0000 }, /* R52 - Line Mixer (1) */ |
286 | { 0x0035, 0x0000 }, /* R53 - Line Mixer (2) */ |
287 | { 0x0036, 0x0000 }, /* R54 - Speaker Mixer */ |
288 | { 0x0037, 0x0000 }, /* R55 - Additional Control */ |
289 | { 0x0038, 0x0000 }, /* R56 - AntiPOP (1) */ |
290 | { 0x0039, 0x0000 }, /* R57 - AntiPOP (2) */ |
291 | { 0x003A, 0x0000 }, /* R58 - MICBIAS */ |
292 | { 0x003B, 0x000D }, /* R59 - LDO 1 */ |
293 | { 0x003C, 0x0003 }, /* R60 - LDO 2 */ |
294 | { 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */ |
295 | { 0x0051, 0x0004 }, /* R81 - Class W (1) */ |
296 | { 0x0055, 0x054A }, /* R85 - DC Servo (2) */ |
297 | { 0x0057, 0x0000 }, /* R87 - DC Servo (4) */ |
298 | { 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */ |
299 | { 0x0101, 0x8004 }, /* R257 - Control Interface */ |
300 | { 0x0110, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */ |
301 | { 0x0111, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */ |
302 | { 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */ |
303 | { 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */ |
304 | { 0x0204, 0x0000 }, /* R516 - AIF2 Clocking (1) */ |
305 | { 0x0205, 0x0000 }, /* R517 - AIF2 Clocking (2) */ |
306 | { 0x0208, 0x0000 }, /* R520 - Clocking (1) */ |
307 | { 0x0209, 0x0000 }, /* R521 - Clocking (2) */ |
308 | { 0x0210, 0x0083 }, /* R528 - AIF1 Rate */ |
309 | { 0x0211, 0x0083 }, /* R529 - AIF2 Rate */ |
310 | { 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */ |
311 | { 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */ |
312 | { 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */ |
313 | { 0x0223, 0x0000 }, /* R547 - FLL1 Control (4) */ |
314 | { 0x0224, 0x0C80 }, /* R548 - FLL1 Control (5) */ |
315 | { 0x0240, 0x0000 }, /* R576 - FLL2 Control (1) */ |
316 | { 0x0241, 0x0000 }, /* R577 - FLL2 Control (2) */ |
317 | { 0x0242, 0x0000 }, /* R578 - FLL2 Control (3) */ |
318 | { 0x0243, 0x0000 }, /* R579 - FLL2 Control (4) */ |
319 | { 0x0244, 0x0C80 }, /* R580 - FLL2 Control (5) */ |
320 | { 0x0300, 0x4050 }, /* R768 - AIF1 Control (1) */ |
321 | { 0x0301, 0x4000 }, /* R769 - AIF1 Control (2) */ |
322 | { 0x0302, 0x0000 }, /* R770 - AIF1 Master/Slave */ |
323 | { 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */ |
324 | { 0x0304, 0x0040 }, /* R772 - AIF1ADC LRCLK */ |
325 | { 0x0305, 0x0040 }, /* R773 - AIF1DAC LRCLK */ |
326 | { 0x0306, 0x0004 }, /* R774 - AIF1DAC Data */ |
327 | { 0x0307, 0x0100 }, /* R775 - AIF1ADC Data */ |
328 | { 0x0310, 0x4050 }, /* R784 - AIF2 Control (1) */ |
329 | { 0x0311, 0x4000 }, /* R785 - AIF2 Control (2) */ |
330 | { 0x0312, 0x0000 }, /* R786 - AIF2 Master/Slave */ |
331 | { 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */ |
332 | { 0x0314, 0x0040 }, /* R788 - AIF2ADC LRCLK */ |
333 | { 0x0315, 0x0040 }, /* R789 - AIF2DAC LRCLK */ |
334 | { 0x0316, 0x0000 }, /* R790 - AIF2DAC Data */ |
335 | { 0x0317, 0x0000 }, /* R791 - AIF2ADC Data */ |
336 | { 0x0400, 0x00C0 }, /* R1024 - AIF1 ADC1 Left Volume */ |
337 | { 0x0401, 0x00C0 }, /* R1025 - AIF1 ADC1 Right Volume */ |
338 | { 0x0402, 0x00C0 }, /* R1026 - AIF1 DAC1 Left Volume */ |
339 | { 0x0403, 0x00C0 }, /* R1027 - AIF1 DAC1 Right Volume */ |
340 | { 0x0404, 0x00C0 }, /* R1028 - AIF1 ADC2 Left Volume */ |
341 | { 0x0405, 0x00C0 }, /* R1029 - AIF1 ADC2 Right Volume */ |
342 | { 0x0406, 0x00C0 }, /* R1030 - AIF1 DAC2 Left Volume */ |
343 | { 0x0407, 0x00C0 }, /* R1031 - AIF1 DAC2 Right Volume */ |
344 | { 0x0410, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */ |
345 | { 0x0411, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */ |
346 | { 0x0420, 0x0200 }, /* R1056 - AIF1 DAC1 Filters (1) */ |
347 | { 0x0421, 0x0010 }, /* R1057 - AIF1 DAC1 Filters (2) */ |
348 | { 0x0422, 0x0200 }, /* R1058 - AIF1 DAC2 Filters (1) */ |
349 | { 0x0423, 0x0010 }, /* R1059 - AIF1 DAC2 Filters (2) */ |
350 | { 0x0440, 0x0098 }, /* R1088 - AIF1 DRC1 (1) */ |
351 | { 0x0441, 0x0845 }, /* R1089 - AIF1 DRC1 (2) */ |
352 | { 0x0442, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */ |
353 | { 0x0443, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */ |
354 | { 0x0444, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */ |
355 | { 0x0450, 0x0098 }, /* R1104 - AIF1 DRC2 (1) */ |
356 | { 0x0451, 0x0845 }, /* R1105 - AIF1 DRC2 (2) */ |
357 | { 0x0452, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */ |
358 | { 0x0453, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */ |
359 | { 0x0454, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */ |
360 | { 0x0480, 0x6318 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */ |
361 | { 0x0481, 0x6300 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */ |
362 | { 0x0482, 0x0FCA }, /* R1154 - AIF1 DAC1 EQ Band 1 A */ |
363 | { 0x0483, 0x0400 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */ |
364 | { 0x0484, 0x00D8 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */ |
365 | { 0x0485, 0x1EB5 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */ |
366 | { 0x0486, 0xF145 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */ |
367 | { 0x0487, 0x0B75 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */ |
368 | { 0x0488, 0x01C5 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */ |
369 | { 0x0489, 0x1C58 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */ |
370 | { 0x048A, 0xF373 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */ |
371 | { 0x048B, 0x0A54 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */ |
372 | { 0x048C, 0x0558 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */ |
373 | { 0x048D, 0x168E }, /* R1165 - AIF1 DAC1 EQ Band 4 A */ |
374 | { 0x048E, 0xF829 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */ |
375 | { 0x048F, 0x07AD }, /* R1167 - AIF1 DAC1 EQ Band 4 C */ |
376 | { 0x0490, 0x1103 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */ |
377 | { 0x0491, 0x0564 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */ |
378 | { 0x0492, 0x0559 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */ |
379 | { 0x0493, 0x4000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */ |
380 | { 0x04A0, 0x6318 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */ |
381 | { 0x04A1, 0x6300 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */ |
382 | { 0x04A2, 0x0FCA }, /* R1186 - AIF1 DAC2 EQ Band 1 A */ |
383 | { 0x04A3, 0x0400 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */ |
384 | { 0x04A4, 0x00D8 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */ |
385 | { 0x04A5, 0x1EB5 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */ |
386 | { 0x04A6, 0xF145 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */ |
387 | { 0x04A7, 0x0B75 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */ |
388 | { 0x04A8, 0x01C5 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */ |
389 | { 0x04A9, 0x1C58 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */ |
390 | { 0x04AA, 0xF373 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */ |
391 | { 0x04AB, 0x0A54 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */ |
392 | { 0x04AC, 0x0558 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */ |
393 | { 0x04AD, 0x168E }, /* R1197 - AIF1 DAC2 EQ Band 4 A */ |
394 | { 0x04AE, 0xF829 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */ |
395 | { 0x04AF, 0x07AD }, /* R1199 - AIF1 DAC2 EQ Band 4 C */ |
396 | { 0x04B0, 0x1103 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */ |
397 | { 0x04B1, 0x0564 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */ |
398 | { 0x04B2, 0x0559 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */ |
399 | { 0x04B3, 0x4000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */ |
400 | { 0x0500, 0x00C0 }, /* R1280 - AIF2 ADC Left Volume */ |
401 | { 0x0501, 0x00C0 }, /* R1281 - AIF2 ADC Right Volume */ |
402 | { 0x0502, 0x00C0 }, /* R1282 - AIF2 DAC Left Volume */ |
403 | { 0x0503, 0x00C0 }, /* R1283 - AIF2 DAC Right Volume */ |
404 | { 0x0510, 0x0000 }, /* R1296 - AIF2 ADC Filters */ |
405 | { 0x0520, 0x0200 }, /* R1312 - AIF2 DAC Filters (1) */ |
406 | { 0x0521, 0x0010 }, /* R1313 - AIF2 DAC Filters (2) */ |
407 | { 0x0540, 0x0098 }, /* R1344 - AIF2 DRC (1) */ |
408 | { 0x0541, 0x0845 }, /* R1345 - AIF2 DRC (2) */ |
409 | { 0x0542, 0x0000 }, /* R1346 - AIF2 DRC (3) */ |
410 | { 0x0543, 0x0000 }, /* R1347 - AIF2 DRC (4) */ |
411 | { 0x0544, 0x0000 }, /* R1348 - AIF2 DRC (5) */ |
412 | { 0x0580, 0x6318 }, /* R1408 - AIF2 EQ Gains (1) */ |
413 | { 0x0581, 0x6300 }, /* R1409 - AIF2 EQ Gains (2) */ |
414 | { 0x0582, 0x0FCA }, /* R1410 - AIF2 EQ Band 1 A */ |
415 | { 0x0583, 0x0400 }, /* R1411 - AIF2 EQ Band 1 B */ |
416 | { 0x0584, 0x00D8 }, /* R1412 - AIF2 EQ Band 1 PG */ |
417 | { 0x0585, 0x1EB5 }, /* R1413 - AIF2 EQ Band 2 A */ |
418 | { 0x0586, 0xF145 }, /* R1414 - AIF2 EQ Band 2 B */ |
419 | { 0x0587, 0x0B75 }, /* R1415 - AIF2 EQ Band 2 C */ |
420 | { 0x0588, 0x01C5 }, /* R1416 - AIF2 EQ Band 2 PG */ |
421 | { 0x0589, 0x1C58 }, /* R1417 - AIF2 EQ Band 3 A */ |
422 | { 0x058A, 0xF373 }, /* R1418 - AIF2 EQ Band 3 B */ |
423 | { 0x058B, 0x0A54 }, /* R1419 - AIF2 EQ Band 3 C */ |
424 | { 0x058C, 0x0558 }, /* R1420 - AIF2 EQ Band 3 PG */ |
425 | { 0x058D, 0x168E }, /* R1421 - AIF2 EQ Band 4 A */ |
426 | { 0x058E, 0xF829 }, /* R1422 - AIF2 EQ Band 4 B */ |
427 | { 0x058F, 0x07AD }, /* R1423 - AIF2 EQ Band 4 C */ |
428 | { 0x0590, 0x1103 }, /* R1424 - AIF2 EQ Band 4 PG */ |
429 | { 0x0591, 0x0564 }, /* R1425 - AIF2 EQ Band 5 A */ |
430 | { 0x0592, 0x0559 }, /* R1426 - AIF2 EQ Band 5 B */ |
431 | { 0x0593, 0x4000 }, /* R1427 - AIF2 EQ Band 5 PG */ |
432 | { 0x0600, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */ |
433 | { 0x0601, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */ |
434 | { 0x0602, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */ |
435 | { 0x0603, 0x0000 }, /* R1539 - DAC2 Mixer Volumes */ |
436 | { 0x0604, 0x0000 }, /* R1540 - DAC2 Left Mixer Routing */ |
437 | { 0x0605, 0x0000 }, /* R1541 - DAC2 Right Mixer Routing */ |
438 | { 0x0606, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */ |
439 | { 0x0607, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */ |
440 | { 0x0608, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */ |
441 | { 0x0609, 0x0000 }, /* R1545 - AIF1 ADC2 Right mixer Routing */ |
442 | { 0x0610, 0x02C0 }, /* R1552 - DAC1 Left Volume */ |
443 | { 0x0611, 0x02C0 }, /* R1553 - DAC1 Right Volume */ |
444 | { 0x0612, 0x02C0 }, /* R1554 - DAC2 Left Volume */ |
445 | { 0x0613, 0x02C0 }, /* R1555 - DAC2 Right Volume */ |
446 | { 0x0614, 0x0000 }, /* R1556 - DAC Softmute */ |
447 | { 0x0620, 0x0002 }, /* R1568 - Oversampling */ |
448 | { 0x0621, 0x0000 }, /* R1569 - Sidetone */ |
449 | { 0x0700, 0x8100 }, /* R1792 - GPIO 1 */ |
450 | { 0x0701, 0xA101 }, /* R1793 - GPIO 2 */ |
451 | { 0x0702, 0xA101 }, /* R1794 - GPIO 3 */ |
452 | { 0x0703, 0xA101 }, /* R1795 - GPIO 4 */ |
453 | { 0x0704, 0xA101 }, /* R1796 - GPIO 5 */ |
454 | { 0x0705, 0xA101 }, /* R1797 - GPIO 6 */ |
455 | { 0x0706, 0xA101 }, /* R1798 - GPIO 7 */ |
456 | { 0x0707, 0xA101 }, /* R1799 - GPIO 8 */ |
457 | { 0x0708, 0xA101 }, /* R1800 - GPIO 9 */ |
458 | { 0x0709, 0xA101 }, /* R1801 - GPIO 10 */ |
459 | { 0x070A, 0xA101 }, /* R1802 - GPIO 11 */ |
460 | { 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */ |
461 | { 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */ |
462 | { 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */ |
463 | { 0x0739, 0xFFFF }, /* R1849 - Interrupt Status 2 Mask */ |
464 | { 0x0740, 0x0000 }, /* R1856 - Interrupt Control */ |
465 | { 0x0748, 0x003F }, /* R1864 - IRQ Debounce */ |
466 | }; |
467 | |
468 | static const struct reg_default wm8958_defaults[] = { |
469 | { 0x0001, 0x0000 }, /* R1 - Power Management (1) */ |
470 | { 0x0002, 0x6000 }, /* R2 - Power Management (2) */ |
471 | { 0x0003, 0x0000 }, /* R3 - Power Management (3) */ |
472 | { 0x0004, 0x0000 }, /* R4 - Power Management (4) */ |
473 | { 0x0005, 0x0000 }, /* R5 - Power Management (5) */ |
474 | { 0x0006, 0x0000 }, /* R6 - Power Management (6) */ |
475 | { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */ |
476 | { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */ |
477 | { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */ |
478 | { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */ |
479 | { 0x001B, 0x008B }, /* R27 - Right Line Input 3&4 Volume */ |
480 | { 0x001C, 0x006D }, /* R28 - Left Output Volume */ |
481 | { 0x001D, 0x006D }, /* R29 - Right Output Volume */ |
482 | { 0x001E, 0x0066 }, /* R30 - Line Outputs Volume */ |
483 | { 0x001F, 0x0020 }, /* R31 - HPOUT2 Volume */ |
484 | { 0x0020, 0x0079 }, /* R32 - Left OPGA Volume */ |
485 | { 0x0021, 0x0079 }, /* R33 - Right OPGA Volume */ |
486 | { 0x0022, 0x0003 }, /* R34 - SPKMIXL Attenuation */ |
487 | { 0x0023, 0x0003 }, /* R35 - SPKMIXR Attenuation */ |
488 | { 0x0024, 0x0011 }, /* R36 - SPKOUT Mixers */ |
489 | { 0x0025, 0x0140 }, /* R37 - ClassD */ |
490 | { 0x0026, 0x0079 }, /* R38 - Speaker Volume Left */ |
491 | { 0x0027, 0x0079 }, /* R39 - Speaker Volume Right */ |
492 | { 0x0028, 0x0000 }, /* R40 - Input Mixer (2) */ |
493 | { 0x0029, 0x0000 }, /* R41 - Input Mixer (3) */ |
494 | { 0x002A, 0x0000 }, /* R42 - Input Mixer (4) */ |
495 | { 0x002B, 0x0000 }, /* R43 - Input Mixer (5) */ |
496 | { 0x002C, 0x0000 }, /* R44 - Input Mixer (6) */ |
497 | { 0x002D, 0x0000 }, /* R45 - Output Mixer (1) */ |
498 | { 0x002E, 0x0000 }, /* R46 - Output Mixer (2) */ |
499 | { 0x002F, 0x0000 }, /* R47 - Output Mixer (3) */ |
500 | { 0x0030, 0x0000 }, /* R48 - Output Mixer (4) */ |
501 | { 0x0031, 0x0000 }, /* R49 - Output Mixer (5) */ |
502 | { 0x0032, 0x0000 }, /* R50 - Output Mixer (6) */ |
503 | { 0x0033, 0x0000 }, /* R51 - HPOUT2 Mixer */ |
504 | { 0x0034, 0x0000 }, /* R52 - Line Mixer (1) */ |
505 | { 0x0035, 0x0000 }, /* R53 - Line Mixer (2) */ |
506 | { 0x0036, 0x0000 }, /* R54 - Speaker Mixer */ |
507 | { 0x0037, 0x0000 }, /* R55 - Additional Control */ |
508 | { 0x0038, 0x0000 }, /* R56 - AntiPOP (1) */ |
509 | { 0x0039, 0x0180 }, /* R57 - AntiPOP (2) */ |
510 | { 0x003B, 0x000D }, /* R59 - LDO 1 */ |
511 | { 0x003C, 0x0005 }, /* R60 - LDO 2 */ |
512 | { 0x003D, 0x0039 }, /* R61 - MICBIAS1 */ |
513 | { 0x003E, 0x0039 }, /* R62 - MICBIAS2 */ |
514 | { 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */ |
515 | { 0x004D, 0xAB19 }, /* R77 - Charge Pump (2) */ |
516 | { 0x0051, 0x0004 }, /* R81 - Class W (1) */ |
517 | { 0x0055, 0x054A }, /* R85 - DC Servo (2) */ |
518 | { 0x0057, 0x0000 }, /* R87 - DC Servo (4) */ |
519 | { 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */ |
520 | { 0x00C5, 0x0000 }, /* R197 - Class D Test (5) */ |
521 | { 0x00D0, 0x5600 }, /* R208 - Mic Detect 1 */ |
522 | { 0x00D1, 0x007F }, /* R209 - Mic Detect 2 */ |
523 | { 0x0101, 0x8004 }, /* R257 - Control Interface */ |
524 | { 0x0110, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */ |
525 | { 0x0111, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */ |
526 | { 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */ |
527 | { 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */ |
528 | { 0x0204, 0x0000 }, /* R516 - AIF2 Clocking (1) */ |
529 | { 0x0205, 0x0000 }, /* R517 - AIF2 Clocking (2) */ |
530 | { 0x0208, 0x0000 }, /* R520 - Clocking (1) */ |
531 | { 0x0209, 0x0000 }, /* R521 - Clocking (2) */ |
532 | { 0x0210, 0x0083 }, /* R528 - AIF1 Rate */ |
533 | { 0x0211, 0x0083 }, /* R529 - AIF2 Rate */ |
534 | { 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */ |
535 | { 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */ |
536 | { 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */ |
537 | { 0x0223, 0x0000 }, /* R547 - FLL1 Control (4) */ |
538 | { 0x0224, 0x0C80 }, /* R548 - FLL1 Control (5) */ |
539 | { 0x0226, 0x0000 }, /* R550 - FLL1 EFS 1 */ |
540 | { 0x0227, 0x0006 }, /* R551 - FLL1 EFS 2 */ |
541 | { 0x0240, 0x0000 }, /* R576 - FLL2Control (1) */ |
542 | { 0x0241, 0x0000 }, /* R577 - FLL2Control (2) */ |
543 | { 0x0242, 0x0000 }, /* R578 - FLL2Control (3) */ |
544 | { 0x0243, 0x0000 }, /* R579 - FLL2 Control (4) */ |
545 | { 0x0244, 0x0C80 }, /* R580 - FLL2Control (5) */ |
546 | { 0x0246, 0x0000 }, /* R582 - FLL2 EFS 1 */ |
547 | { 0x0247, 0x0006 }, /* R583 - FLL2 EFS 2 */ |
548 | { 0x0300, 0x4050 }, /* R768 - AIF1 Control (1) */ |
549 | { 0x0301, 0x4000 }, /* R769 - AIF1 Control (2) */ |
550 | { 0x0302, 0x0000 }, /* R770 - AIF1 Master/Slave */ |
551 | { 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */ |
552 | { 0x0304, 0x0040 }, /* R772 - AIF1ADC LRCLK */ |
553 | { 0x0305, 0x0040 }, /* R773 - AIF1DAC LRCLK */ |
554 | { 0x0306, 0x0004 }, /* R774 - AIF1DAC Data */ |
555 | { 0x0307, 0x0100 }, /* R775 - AIF1ADC Data */ |
556 | { 0x0310, 0x4053 }, /* R784 - AIF2 Control (1) */ |
557 | { 0x0311, 0x4000 }, /* R785 - AIF2 Control (2) */ |
558 | { 0x0312, 0x0000 }, /* R786 - AIF2 Master/Slave */ |
559 | { 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */ |
560 | { 0x0314, 0x0040 }, /* R788 - AIF2ADC LRCLK */ |
561 | { 0x0315, 0x0040 }, /* R789 - AIF2DAC LRCLK */ |
562 | { 0x0316, 0x0000 }, /* R790 - AIF2DAC Data */ |
563 | { 0x0317, 0x0000 }, /* R791 - AIF2ADC Data */ |
564 | { 0x0320, 0x0040 }, /* R800 - AIF3 Control (1) */ |
565 | { 0x0321, 0x0000 }, /* R801 - AIF3 Control (2) */ |
566 | { 0x0322, 0x0000 }, /* R802 - AIF3DAC Data */ |
567 | { 0x0323, 0x0000 }, /* R803 - AIF3ADC Data */ |
568 | { 0x0400, 0x00C0 }, /* R1024 - AIF1 ADC1 Left Volume */ |
569 | { 0x0401, 0x00C0 }, /* R1025 - AIF1 ADC1 Right Volume */ |
570 | { 0x0402, 0x00C0 }, /* R1026 - AIF1 DAC1 Left Volume */ |
571 | { 0x0403, 0x00C0 }, /* R1027 - AIF1 DAC1 Right Volume */ |
572 | { 0x0404, 0x00C0 }, /* R1028 - AIF1 ADC2 Left Volume */ |
573 | { 0x0405, 0x00C0 }, /* R1029 - AIF1 ADC2 Right Volume */ |
574 | { 0x0406, 0x00C0 }, /* R1030 - AIF1 DAC2 Left Volume */ |
575 | { 0x0407, 0x00C0 }, /* R1031 - AIF1 DAC2 Right Volume */ |
576 | { 0x0410, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */ |
577 | { 0x0411, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */ |
578 | { 0x0420, 0x0200 }, /* R1056 - AIF1 DAC1 Filters (1) */ |
579 | { 0x0421, 0x0010 }, /* R1057 - AIF1 DAC1 Filters (2) */ |
580 | { 0x0422, 0x0200 }, /* R1058 - AIF1 DAC2 Filters (1) */ |
581 | { 0x0423, 0x0010 }, /* R1059 - AIF1 DAC2 Filters (2) */ |
582 | { 0x0430, 0x0068 }, /* R1072 - AIF1 DAC1 Noise Gate */ |
583 | { 0x0431, 0x0068 }, /* R1073 - AIF1 DAC2 Noise Gate */ |
584 | { 0x0440, 0x0098 }, /* R1088 - AIF1 DRC1 (1) */ |
585 | { 0x0441, 0x0845 }, /* R1089 - AIF1 DRC1 (2) */ |
586 | { 0x0442, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */ |
587 | { 0x0443, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */ |
588 | { 0x0444, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */ |
589 | { 0x0450, 0x0098 }, /* R1104 - AIF1 DRC2 (1) */ |
590 | { 0x0451, 0x0845 }, /* R1105 - AIF1 DRC2 (2) */ |
591 | { 0x0452, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */ |
592 | { 0x0453, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */ |
593 | { 0x0454, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */ |
594 | { 0x0480, 0x6318 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */ |
595 | { 0x0481, 0x6300 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */ |
596 | { 0x0482, 0x0FCA }, /* R1154 - AIF1 DAC1 EQ Band 1 A */ |
597 | { 0x0483, 0x0400 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */ |
598 | { 0x0484, 0x00D8 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */ |
599 | { 0x0485, 0x1EB5 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */ |
600 | { 0x0486, 0xF145 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */ |
601 | { 0x0487, 0x0B75 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */ |
602 | { 0x0488, 0x01C5 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */ |
603 | { 0x0489, 0x1C58 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */ |
604 | { 0x048A, 0xF373 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */ |
605 | { 0x048B, 0x0A54 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */ |
606 | { 0x048C, 0x0558 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */ |
607 | { 0x048D, 0x168E }, /* R1165 - AIF1 DAC1 EQ Band 4 A */ |
608 | { 0x048E, 0xF829 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */ |
609 | { 0x048F, 0x07AD }, /* R1167 - AIF1 DAC1 EQ Band 4 C */ |
610 | { 0x0490, 0x1103 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */ |
611 | { 0x0491, 0x0564 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */ |
612 | { 0x0492, 0x0559 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */ |
613 | { 0x0493, 0x4000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */ |
614 | { 0x0494, 0x0000 }, /* R1172 - AIF1 DAC1 EQ Band 1 C */ |
615 | { 0x04A0, 0x6318 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */ |
616 | { 0x04A1, 0x6300 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */ |
617 | { 0x04A2, 0x0FCA }, /* R1186 - AIF1 DAC2 EQ Band 1 A */ |
618 | { 0x04A3, 0x0400 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */ |
619 | { 0x04A4, 0x00D8 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */ |
620 | { 0x04A5, 0x1EB5 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */ |
621 | { 0x04A6, 0xF145 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */ |
622 | { 0x04A7, 0x0B75 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */ |
623 | { 0x04A8, 0x01C5 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */ |
624 | { 0x04A9, 0x1C58 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */ |
625 | { 0x04AA, 0xF373 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */ |
626 | { 0x04AB, 0x0A54 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */ |
627 | { 0x04AC, 0x0558 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */ |
628 | { 0x04AD, 0x168E }, /* R1197 - AIF1 DAC2 EQ Band 4 A */ |
629 | { 0x04AE, 0xF829 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */ |
630 | { 0x04AF, 0x07AD }, /* R1199 - AIF1 DAC2 EQ Band 4 C */ |
631 | { 0x04B0, 0x1103 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */ |
632 | { 0x04B1, 0x0564 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */ |
633 | { 0x04B2, 0x0559 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */ |
634 | { 0x04B3, 0x4000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */ |
635 | { 0x04B4, 0x0000 }, /* R1204 - AIF1 DAC2EQ Band 1 C */ |
636 | { 0x0500, 0x00C0 }, /* R1280 - AIF2 ADC Left Volume */ |
637 | { 0x0501, 0x00C0 }, /* R1281 - AIF2 ADC Right Volume */ |
638 | { 0x0502, 0x00C0 }, /* R1282 - AIF2 DAC Left Volume */ |
639 | { 0x0503, 0x00C0 }, /* R1283 - AIF2 DAC Right Volume */ |
640 | { 0x0510, 0x0000 }, /* R1296 - AIF2 ADC Filters */ |
641 | { 0x0520, 0x0200 }, /* R1312 - AIF2 DAC Filters (1) */ |
642 | { 0x0521, 0x0010 }, /* R1313 - AIF2 DAC Filters (2) */ |
643 | { 0x0530, 0x0068 }, /* R1328 - AIF2 DAC Noise Gate */ |
644 | { 0x0540, 0x0098 }, /* R1344 - AIF2 DRC (1) */ |
645 | { 0x0541, 0x0845 }, /* R1345 - AIF2 DRC (2) */ |
646 | { 0x0542, 0x0000 }, /* R1346 - AIF2 DRC (3) */ |
647 | { 0x0543, 0x0000 }, /* R1347 - AIF2 DRC (4) */ |
648 | { 0x0544, 0x0000 }, /* R1348 - AIF2 DRC (5) */ |
649 | { 0x0580, 0x6318 }, /* R1408 - AIF2 EQ Gains (1) */ |
650 | { 0x0581, 0x6300 }, /* R1409 - AIF2 EQ Gains (2) */ |
651 | { 0x0582, 0x0FCA }, /* R1410 - AIF2 EQ Band 1 A */ |
652 | { 0x0583, 0x0400 }, /* R1411 - AIF2 EQ Band 1 B */ |
653 | { 0x0584, 0x00D8 }, /* R1412 - AIF2 EQ Band 1 PG */ |
654 | { 0x0585, 0x1EB5 }, /* R1413 - AIF2 EQ Band 2 A */ |
655 | { 0x0586, 0xF145 }, /* R1414 - AIF2 EQ Band 2 B */ |
656 | { 0x0587, 0x0B75 }, /* R1415 - AIF2 EQ Band 2 C */ |
657 | { 0x0588, 0x01C5 }, /* R1416 - AIF2 EQ Band 2 PG */ |
658 | { 0x0589, 0x1C58 }, /* R1417 - AIF2 EQ Band 3 A */ |
659 | { 0x058A, 0xF373 }, /* R1418 - AIF2 EQ Band 3 B */ |
660 | { 0x058B, 0x0A54 }, /* R1419 - AIF2 EQ Band 3 C */ |
661 | { 0x058C, 0x0558 }, /* R1420 - AIF2 EQ Band 3 PG */ |
662 | { 0x058D, 0x168E }, /* R1421 - AIF2 EQ Band 4 A */ |
663 | { 0x058E, 0xF829 }, /* R1422 - AIF2 EQ Band 4 B */ |
664 | { 0x058F, 0x07AD }, /* R1423 - AIF2 EQ Band 4 C */ |
665 | { 0x0590, 0x1103 }, /* R1424 - AIF2 EQ Band 4 PG */ |
666 | { 0x0591, 0x0564 }, /* R1425 - AIF2 EQ Band 5 A */ |
667 | { 0x0592, 0x0559 }, /* R1426 - AIF2 EQ Band 5 B */ |
668 | { 0x0593, 0x4000 }, /* R1427 - AIF2 EQ Band 5 PG */ |
669 | { 0x0594, 0x0000 }, /* R1428 - AIF2 EQ Band 1 C */ |
670 | { 0x0600, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */ |
671 | { 0x0601, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */ |
672 | { 0x0602, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */ |
673 | { 0x0603, 0x0000 }, /* R1539 - DAC2 Mixer Volumes */ |
674 | { 0x0604, 0x0000 }, /* R1540 - DAC2 Left Mixer Routing */ |
675 | { 0x0605, 0x0000 }, /* R1541 - DAC2 Right Mixer Routing */ |
676 | { 0x0606, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */ |
677 | { 0x0607, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */ |
678 | { 0x0608, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */ |
679 | { 0x0609, 0x0000 }, /* R1545 - AIF1 ADC2 Right mixer Routing */ |
680 | { 0x0610, 0x02C0 }, /* R1552 - DAC1 Left Volume */ |
681 | { 0x0611, 0x02C0 }, /* R1553 - DAC1 Right Volume */ |
682 | { 0x0612, 0x02C0 }, /* R1554 - DAC2 Left Volume */ |
683 | { 0x0613, 0x02C0 }, /* R1555 - DAC2 Right Volume */ |
684 | { 0x0614, 0x0000 }, /* R1556 - DAC Softmute */ |
685 | { 0x0620, 0x0002 }, /* R1568 - Oversampling */ |
686 | { 0x0621, 0x0000 }, /* R1569 - Sidetone */ |
687 | { 0x0700, 0x8100 }, /* R1792 - GPIO 1 */ |
688 | { 0x0701, 0xA101 }, /* R1793 - Pull Control (MCLK2) */ |
689 | { 0x0702, 0xA101 }, /* R1794 - Pull Control (BCLK2) */ |
690 | { 0x0703, 0xA101 }, /* R1795 - Pull Control (DACLRCLK2) */ |
691 | { 0x0704, 0xA101 }, /* R1796 - Pull Control (DACDAT2) */ |
692 | { 0x0705, 0xA101 }, /* R1797 - GPIO 6 */ |
693 | { 0x0707, 0xA101 }, /* R1799 - GPIO 8 */ |
694 | { 0x0708, 0xA101 }, /* R1800 - GPIO 9 */ |
695 | { 0x0709, 0xA101 }, /* R1801 - GPIO 10 */ |
696 | { 0x070A, 0xA101 }, /* R1802 - GPIO 11 */ |
697 | { 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */ |
698 | { 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */ |
699 | { 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */ |
700 | { 0x0739, 0xFFEF }, /* R1849 - Interrupt Status 2 Mask */ |
701 | { 0x0740, 0x0000 }, /* R1856 - Interrupt Control */ |
702 | { 0x0748, 0x003F }, /* R1864 - IRQ Debounce */ |
703 | { 0x0900, 0x1C00 }, /* R2304 - DSP2_Program */ |
704 | { 0x0901, 0x0000 }, /* R2305 - DSP2_Config */ |
705 | { 0x0A0D, 0x0000 }, /* R2573 - DSP2_ExecControl */ |
706 | { 0x2400, 0x003F }, /* R9216 - MBC Band 1 K (1) */ |
707 | { 0x2401, 0x8BD8 }, /* R9217 - MBC Band 1 K (2) */ |
708 | { 0x2402, 0x0032 }, /* R9218 - MBC Band 1 N1 (1) */ |
709 | { 0x2403, 0xF52D }, /* R9219 - MBC Band 1 N1 (2) */ |
710 | { 0x2404, 0x0065 }, /* R9220 - MBC Band 1 N2 (1) */ |
711 | { 0x2405, 0xAC8C }, /* R9221 - MBC Band 1 N2 (2) */ |
712 | { 0x2406, 0x006B }, /* R9222 - MBC Band 1 N3 (1) */ |
713 | { 0x2407, 0xE087 }, /* R9223 - MBC Band 1 N3 (2) */ |
714 | { 0x2408, 0x0072 }, /* R9224 - MBC Band 1 N4 (1) */ |
715 | { 0x2409, 0x1483 }, /* R9225 - MBC Band 1 N4 (2) */ |
716 | { 0x240A, 0x0072 }, /* R9226 - MBC Band 1 N5 (1) */ |
717 | { 0x240B, 0x1483 }, /* R9227 - MBC Band 1 N5 (2) */ |
718 | { 0x240C, 0x0043 }, /* R9228 - MBC Band 1 X1 (1) */ |
719 | { 0x240D, 0x3525 }, /* R9229 - MBC Band 1 X1 (2) */ |
720 | { 0x240E, 0x0006 }, /* R9230 - MBC Band 1 X2 (1) */ |
721 | { 0x240F, 0x6A4A }, /* R9231 - MBC Band 1 X2 (2) */ |
722 | { 0x2410, 0x0043 }, /* R9232 - MBC Band 1 X3 (1) */ |
723 | { 0x2411, 0x6079 }, /* R9233 - MBC Band 1 X3 (2) */ |
724 | { 0x2412, 0x000C }, /* R9234 - MBC Band 1 Attack (1) */ |
725 | { 0x2413, 0xCCCD }, /* R9235 - MBC Band 1 Attack (2) */ |
726 | { 0x2414, 0x0000 }, /* R9236 - MBC Band 1 Decay (1) */ |
727 | { 0x2415, 0x0800 }, /* R9237 - MBC Band 1 Decay (2) */ |
728 | { 0x2416, 0x003F }, /* R9238 - MBC Band 2 K (1) */ |
729 | { 0x2417, 0x8BD8 }, /* R9239 - MBC Band 2 K (2) */ |
730 | { 0x2418, 0x0032 }, /* R9240 - MBC Band 2 N1 (1) */ |
731 | { 0x2419, 0xF52D }, /* R9241 - MBC Band 2 N1 (2) */ |
732 | { 0x241A, 0x0065 }, /* R9242 - MBC Band 2 N2 (1) */ |
733 | { 0x241B, 0xAC8C }, /* R9243 - MBC Band 2 N2 (2) */ |
734 | { 0x241C, 0x006B }, /* R9244 - MBC Band 2 N3 (1) */ |
735 | { 0x241D, 0xE087 }, /* R9245 - MBC Band 2 N3 (2) */ |
736 | { 0x241E, 0x0072 }, /* R9246 - MBC Band 2 N4 (1) */ |
737 | { 0x241F, 0x1483 }, /* R9247 - MBC Band 2 N4 (2) */ |
738 | { 0x2420, 0x0072 }, /* R9248 - MBC Band 2 N5 (1) */ |
739 | { 0x2421, 0x1483 }, /* R9249 - MBC Band 2 N5 (2) */ |
740 | { 0x2422, 0x0043 }, /* R9250 - MBC Band 2 X1 (1) */ |
741 | { 0x2423, 0x3525 }, /* R9251 - MBC Band 2 X1 (2) */ |
742 | { 0x2424, 0x0006 }, /* R9252 - MBC Band 2 X2 (1) */ |
743 | { 0x2425, 0x6A4A }, /* R9253 - MBC Band 2 X2 (2) */ |
744 | { 0x2426, 0x0043 }, /* R9254 - MBC Band 2 X3 (1) */ |
745 | { 0x2427, 0x6079 }, /* R9255 - MBC Band 2 X3 (2) */ |
746 | { 0x2428, 0x000C }, /* R9256 - MBC Band 2 Attack (1) */ |
747 | { 0x2429, 0xCCCD }, /* R9257 - MBC Band 2 Attack (2) */ |
748 | { 0x242A, 0x0000 }, /* R9258 - MBC Band 2 Decay (1) */ |
749 | { 0x242B, 0x0800 }, /* R9259 - MBC Band 2 Decay (2) */ |
750 | { 0x242C, 0x005A }, /* R9260 - MBC_B2_PG2 (1) */ |
751 | { 0x242D, 0x7EFA }, /* R9261 - MBC_B2_PG2 (2) */ |
752 | { 0x242E, 0x005A }, /* R9262 - MBC_B1_PG2 (1) */ |
753 | { 0x242F, 0x7EFA }, /* R9263 - MBC_B1_PG2 (2) */ |
754 | { 0x2600, 0x00A7 }, /* R9728 - MBC Crossover (1) */ |
755 | { 0x2601, 0x0D1C }, /* R9729 - MBC Crossover (2) */ |
756 | { 0x2602, 0x0083 }, /* R9730 - MBC HPF (1) */ |
757 | { 0x2603, 0x98AD }, /* R9731 - MBC HPF (2) */ |
758 | { 0x2606, 0x0008 }, /* R9734 - MBC LPF (1) */ |
759 | { 0x2607, 0xE7A2 }, /* R9735 - MBC LPF (2) */ |
760 | { 0x260A, 0x0055 }, /* R9738 - MBC RMS Limit (1) */ |
761 | { 0x260B, 0x8C4B }, /* R9739 - MBC RMS Limit (2) */ |
762 | }; |
763 | |
764 | static bool wm1811_readable_register(struct device *dev, unsigned int reg) |
765 | { |
766 | switch (reg) { |
767 | case WM8994_SOFTWARE_RESET: |
768 | case WM8994_POWER_MANAGEMENT_1: |
769 | case WM8994_POWER_MANAGEMENT_2: |
770 | case WM8994_POWER_MANAGEMENT_3: |
771 | case WM8994_POWER_MANAGEMENT_4: |
772 | case WM8994_POWER_MANAGEMENT_5: |
773 | case WM8994_POWER_MANAGEMENT_6: |
774 | case WM8994_INPUT_MIXER_1: |
775 | case WM8994_LEFT_LINE_INPUT_1_2_VOLUME: |
776 | case WM8994_LEFT_LINE_INPUT_3_4_VOLUME: |
777 | case WM8994_RIGHT_LINE_INPUT_1_2_VOLUME: |
778 | case WM8994_RIGHT_LINE_INPUT_3_4_VOLUME: |
779 | case WM8994_LEFT_OUTPUT_VOLUME: |
780 | case WM8994_RIGHT_OUTPUT_VOLUME: |
781 | case WM8994_LINE_OUTPUTS_VOLUME: |
782 | case WM8994_HPOUT2_VOLUME: |
783 | case WM8994_LEFT_OPGA_VOLUME: |
784 | case WM8994_RIGHT_OPGA_VOLUME: |
785 | case WM8994_SPKMIXL_ATTENUATION: |
786 | case WM8994_SPKMIXR_ATTENUATION: |
787 | case WM8994_SPKOUT_MIXERS: |
788 | case WM8994_CLASSD: |
789 | case WM8994_SPEAKER_VOLUME_LEFT: |
790 | case WM8994_SPEAKER_VOLUME_RIGHT: |
791 | case WM8994_INPUT_MIXER_2: |
792 | case WM8994_INPUT_MIXER_3: |
793 | case WM8994_INPUT_MIXER_4: |
794 | case WM8994_INPUT_MIXER_5: |
795 | case WM8994_INPUT_MIXER_6: |
796 | case WM8994_OUTPUT_MIXER_1: |
797 | case WM8994_OUTPUT_MIXER_2: |
798 | case WM8994_OUTPUT_MIXER_3: |
799 | case WM8994_OUTPUT_MIXER_4: |
800 | case WM8994_OUTPUT_MIXER_5: |
801 | case WM8994_OUTPUT_MIXER_6: |
802 | case WM8994_HPOUT2_MIXER: |
803 | case WM8994_LINE_MIXER_1: |
804 | case WM8994_LINE_MIXER_2: |
805 | case WM8994_SPEAKER_MIXER: |
806 | case WM8994_ADDITIONAL_CONTROL: |
807 | case WM8994_ANTIPOP_1: |
808 | case WM8994_ANTIPOP_2: |
809 | case WM8994_LDO_1: |
810 | case WM8994_LDO_2: |
811 | case WM8958_MICBIAS1: |
812 | case WM8958_MICBIAS2: |
813 | case WM8994_CHARGE_PUMP_1: |
814 | case WM8958_CHARGE_PUMP_2: |
815 | case WM8994_CLASS_W_1: |
816 | case WM8994_DC_SERVO_1: |
817 | case WM8994_DC_SERVO_2: |
818 | case WM8994_DC_SERVO_READBACK: |
819 | case WM8994_DC_SERVO_4: |
820 | case WM8994_DC_SERVO_4E: |
821 | case WM8994_ANALOGUE_HP_1: |
822 | case WM8958_MIC_DETECT_1: |
823 | case WM8958_MIC_DETECT_2: |
824 | case WM8958_MIC_DETECT_3: |
825 | case WM8994_CHIP_REVISION: |
826 | case WM8994_CONTROL_INTERFACE: |
827 | case WM8994_AIF1_CLOCKING_1: |
828 | case WM8994_AIF1_CLOCKING_2: |
829 | case WM8994_AIF2_CLOCKING_1: |
830 | case WM8994_AIF2_CLOCKING_2: |
831 | case WM8994_CLOCKING_1: |
832 | case WM8994_CLOCKING_2: |
833 | case WM8994_AIF1_RATE: |
834 | case WM8994_AIF2_RATE: |
835 | case WM8994_RATE_STATUS: |
836 | case WM8994_FLL1_CONTROL_1: |
837 | case WM8994_FLL1_CONTROL_2: |
838 | case WM8994_FLL1_CONTROL_3: |
839 | case WM8994_FLL1_CONTROL_4: |
840 | case WM8994_FLL1_CONTROL_5: |
841 | case WM8958_FLL1_EFS_1: |
842 | case WM8958_FLL1_EFS_2: |
843 | case WM8994_FLL2_CONTROL_1: |
844 | case WM8994_FLL2_CONTROL_2: |
845 | case WM8994_FLL2_CONTROL_3: |
846 | case WM8994_FLL2_CONTROL_4: |
847 | case WM8994_FLL2_CONTROL_5: |
848 | case WM8958_FLL2_EFS_1: |
849 | case WM8958_FLL2_EFS_2: |
850 | case WM8994_AIF1_CONTROL_1: |
851 | case WM8994_AIF1_CONTROL_2: |
852 | case WM8994_AIF1_MASTER_SLAVE: |
853 | case WM8994_AIF1_BCLK: |
854 | case WM8994_AIF1ADC_LRCLK: |
855 | case WM8994_AIF1DAC_LRCLK: |
856 | case WM8994_AIF1DAC_DATA: |
857 | case WM8994_AIF1ADC_DATA: |
858 | case WM8994_AIF2_CONTROL_1: |
859 | case WM8994_AIF2_CONTROL_2: |
860 | case WM8994_AIF2_MASTER_SLAVE: |
861 | case WM8994_AIF2_BCLK: |
862 | case WM8994_AIF2ADC_LRCLK: |
863 | case WM8994_AIF2DAC_LRCLK: |
864 | case WM8994_AIF2DAC_DATA: |
865 | case WM8994_AIF2ADC_DATA: |
866 | case WM1811_AIF2TX_CONTROL: |
867 | case WM8958_AIF3_CONTROL_1: |
868 | case WM8958_AIF3_CONTROL_2: |
869 | case WM8958_AIF3DAC_DATA: |
870 | case WM8958_AIF3ADC_DATA: |
871 | case WM8994_AIF1_ADC1_LEFT_VOLUME: |
872 | case WM8994_AIF1_ADC1_RIGHT_VOLUME: |
873 | case WM8994_AIF1_DAC1_LEFT_VOLUME: |
874 | case WM8994_AIF1_DAC1_RIGHT_VOLUME: |
875 | case WM8994_AIF1_ADC1_FILTERS: |
876 | case WM8994_AIF1_ADC2_FILTERS: |
877 | case WM8994_AIF1_DAC1_FILTERS_1: |
878 | case WM8994_AIF1_DAC1_FILTERS_2: |
879 | case WM8994_AIF1_DAC2_FILTERS_1: |
880 | case WM8994_AIF1_DAC2_FILTERS_2: |
881 | case WM8958_AIF1_DAC1_NOISE_GATE: |
882 | case WM8958_AIF1_DAC2_NOISE_GATE: |
883 | case WM8994_AIF1_DRC1_1: |
884 | case WM8994_AIF1_DRC1_2: |
885 | case WM8994_AIF1_DRC1_3: |
886 | case WM8994_AIF1_DRC1_4: |
887 | case WM8994_AIF1_DRC1_5: |
888 | case WM8994_AIF1_DRC2_1: |
889 | case WM8994_AIF1_DRC2_2: |
890 | case WM8994_AIF1_DRC2_3: |
891 | case WM8994_AIF1_DRC2_4: |
892 | case WM8994_AIF1_DRC2_5: |
893 | case WM8994_AIF1_DAC1_EQ_GAINS_1: |
894 | case WM8994_AIF1_DAC1_EQ_GAINS_2: |
895 | case WM8994_AIF1_DAC1_EQ_BAND_1_A: |
896 | case WM8994_AIF1_DAC1_EQ_BAND_1_B: |
897 | case WM8994_AIF1_DAC1_EQ_BAND_1_PG: |
898 | case WM8994_AIF1_DAC1_EQ_BAND_2_A: |
899 | case WM8994_AIF1_DAC1_EQ_BAND_2_B: |
900 | case WM8994_AIF1_DAC1_EQ_BAND_2_C: |
901 | case WM8994_AIF1_DAC1_EQ_BAND_2_PG: |
902 | case WM8994_AIF1_DAC1_EQ_BAND_3_A: |
903 | case WM8994_AIF1_DAC1_EQ_BAND_3_B: |
904 | case WM8994_AIF1_DAC1_EQ_BAND_3_C: |
905 | case WM8994_AIF1_DAC1_EQ_BAND_3_PG: |
906 | case WM8994_AIF1_DAC1_EQ_BAND_4_A: |
907 | case WM8994_AIF1_DAC1_EQ_BAND_4_B: |
908 | case WM8994_AIF1_DAC1_EQ_BAND_4_C: |
909 | case WM8994_AIF1_DAC1_EQ_BAND_4_PG: |
910 | case WM8994_AIF1_DAC1_EQ_BAND_5_A: |
911 | case WM8994_AIF1_DAC1_EQ_BAND_5_B: |
912 | case WM8994_AIF1_DAC1_EQ_BAND_5_PG: |
913 | case WM8994_AIF1_DAC1_EQ_BAND_1_C: |
914 | case WM8994_AIF1_DAC2_EQ_GAINS_1: |
915 | case WM8994_AIF1_DAC2_EQ_GAINS_2: |
916 | case WM8994_AIF1_DAC2_EQ_BAND_1_A: |
917 | case WM8994_AIF1_DAC2_EQ_BAND_1_B: |
918 | case WM8994_AIF1_DAC2_EQ_BAND_1_PG: |
919 | case WM8994_AIF1_DAC2_EQ_BAND_2_A: |
920 | case WM8994_AIF1_DAC2_EQ_BAND_2_B: |
921 | case WM8994_AIF1_DAC2_EQ_BAND_2_C: |
922 | case WM8994_AIF1_DAC2_EQ_BAND_2_PG: |
923 | case WM8994_AIF1_DAC2_EQ_BAND_3_A: |
924 | case WM8994_AIF1_DAC2_EQ_BAND_3_B: |
925 | case WM8994_AIF1_DAC2_EQ_BAND_3_C: |
926 | case WM8994_AIF1_DAC2_EQ_BAND_3_PG: |
927 | case WM8994_AIF1_DAC2_EQ_BAND_4_A: |
928 | case WM8994_AIF1_DAC2_EQ_BAND_4_B: |
929 | case WM8994_AIF1_DAC2_EQ_BAND_4_C: |
930 | case WM8994_AIF1_DAC2_EQ_BAND_4_PG: |
931 | case WM8994_AIF1_DAC2_EQ_BAND_5_A: |
932 | case WM8994_AIF1_DAC2_EQ_BAND_5_B: |
933 | case WM8994_AIF1_DAC2_EQ_BAND_5_PG: |
934 | case WM8994_AIF1_DAC2_EQ_BAND_1_C: |
935 | case WM8994_AIF2_ADC_LEFT_VOLUME: |
936 | case WM8994_AIF2_ADC_RIGHT_VOLUME: |
937 | case WM8994_AIF2_DAC_LEFT_VOLUME: |
938 | case WM8994_AIF2_DAC_RIGHT_VOLUME: |
939 | case WM8994_AIF2_ADC_FILTERS: |
940 | case WM8994_AIF2_DAC_FILTERS_1: |
941 | case WM8994_AIF2_DAC_FILTERS_2: |
942 | case WM8958_AIF2_DAC_NOISE_GATE: |
943 | case WM8994_AIF2_DRC_1: |
944 | case WM8994_AIF2_DRC_2: |
945 | case WM8994_AIF2_DRC_3: |
946 | case WM8994_AIF2_DRC_4: |
947 | case WM8994_AIF2_DRC_5: |
948 | case WM8994_AIF2_EQ_GAINS_1: |
949 | case WM8994_AIF2_EQ_GAINS_2: |
950 | case WM8994_AIF2_EQ_BAND_1_A: |
951 | case WM8994_AIF2_EQ_BAND_1_B: |
952 | case WM8994_AIF2_EQ_BAND_1_PG: |
953 | case WM8994_AIF2_EQ_BAND_2_A: |
954 | case WM8994_AIF2_EQ_BAND_2_B: |
955 | case WM8994_AIF2_EQ_BAND_2_C: |
956 | case WM8994_AIF2_EQ_BAND_2_PG: |
957 | case WM8994_AIF2_EQ_BAND_3_A: |
958 | case WM8994_AIF2_EQ_BAND_3_B: |
959 | case WM8994_AIF2_EQ_BAND_3_C: |
960 | case WM8994_AIF2_EQ_BAND_3_PG: |
961 | case WM8994_AIF2_EQ_BAND_4_A: |
962 | case WM8994_AIF2_EQ_BAND_4_B: |
963 | case WM8994_AIF2_EQ_BAND_4_C: |
964 | case WM8994_AIF2_EQ_BAND_4_PG: |
965 | case WM8994_AIF2_EQ_BAND_5_A: |
966 | case WM8994_AIF2_EQ_BAND_5_B: |
967 | case WM8994_AIF2_EQ_BAND_5_PG: |
968 | case WM8994_AIF2_EQ_BAND_1_C: |
969 | case WM8994_DAC1_MIXER_VOLUMES: |
970 | case WM8994_DAC1_LEFT_MIXER_ROUTING: |
971 | case WM8994_DAC1_RIGHT_MIXER_ROUTING: |
972 | case WM8994_DAC2_MIXER_VOLUMES: |
973 | case WM8994_DAC2_LEFT_MIXER_ROUTING: |
974 | case WM8994_DAC2_RIGHT_MIXER_ROUTING: |
975 | case WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING: |
976 | case WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING: |
977 | case WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING: |
978 | case WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING: |
979 | case WM8994_DAC1_LEFT_VOLUME: |
980 | case WM8994_DAC1_RIGHT_VOLUME: |
981 | case WM8994_DAC2_LEFT_VOLUME: |
982 | case WM8994_DAC2_RIGHT_VOLUME: |
983 | case WM8994_DAC_SOFTMUTE: |
984 | case WM8994_OVERSAMPLING: |
985 | case WM8994_SIDETONE: |
986 | case WM8994_GPIO_1: |
987 | case WM8994_GPIO_2: |
988 | case WM8994_GPIO_3: |
989 | case WM8994_GPIO_4: |
990 | case WM8994_GPIO_5: |
991 | case WM8994_GPIO_6: |
992 | case WM8994_GPIO_8: |
993 | case WM8994_GPIO_9: |
994 | case WM8994_GPIO_10: |
995 | case WM8994_GPIO_11: |
996 | case WM8994_PULL_CONTROL_1: |
997 | case WM8994_PULL_CONTROL_2: |
998 | case WM8994_INTERRUPT_STATUS_1: |
999 | case WM8994_INTERRUPT_STATUS_2: |
1000 | case WM8994_INTERRUPT_RAW_STATUS_2: |
1001 | case WM8994_INTERRUPT_STATUS_1_MASK: |
1002 | case WM8994_INTERRUPT_STATUS_2_MASK: |
1003 | case WM8994_INTERRUPT_CONTROL: |
1004 | case WM8994_IRQ_DEBOUNCE: |
1005 | return true; |
1006 | default: |
1007 | return false; |
1008 | } |
1009 | } |
1010 | |
1011 | static bool wm8994_readable_register(struct device *dev, unsigned int reg) |
1012 | { |
1013 | switch (reg) { |
1014 | case WM8994_DC_SERVO_READBACK: |
1015 | case WM8994_MICBIAS: |
1016 | case WM8994_WRITE_SEQUENCER_CTRL_1: |
1017 | case WM8994_WRITE_SEQUENCER_CTRL_2: |
1018 | case WM8994_AIF1_ADC2_LEFT_VOLUME: |
1019 | case WM8994_AIF1_ADC2_RIGHT_VOLUME: |
1020 | case WM8994_AIF1_DAC2_LEFT_VOLUME: |
1021 | case WM8994_AIF1_DAC2_RIGHT_VOLUME: |
1022 | case WM8994_AIF1_ADC2_FILTERS: |
1023 | case WM8994_AIF1_DAC2_FILTERS_1: |
1024 | case WM8994_AIF1_DAC2_FILTERS_2: |
1025 | case WM8958_AIF1_DAC2_NOISE_GATE: |
1026 | case WM8994_AIF1_DRC2_1: |
1027 | case WM8994_AIF1_DRC2_2: |
1028 | case WM8994_AIF1_DRC2_3: |
1029 | case WM8994_AIF1_DRC2_4: |
1030 | case WM8994_AIF1_DRC2_5: |
1031 | case WM8994_AIF1_DAC2_EQ_GAINS_1: |
1032 | case WM8994_AIF1_DAC2_EQ_GAINS_2: |
1033 | case WM8994_AIF1_DAC2_EQ_BAND_1_A: |
1034 | case WM8994_AIF1_DAC2_EQ_BAND_1_B: |
1035 | case WM8994_AIF1_DAC2_EQ_BAND_1_PG: |
1036 | case WM8994_AIF1_DAC2_EQ_BAND_2_A: |
1037 | case WM8994_AIF1_DAC2_EQ_BAND_2_B: |
1038 | case WM8994_AIF1_DAC2_EQ_BAND_2_C: |
1039 | case WM8994_AIF1_DAC2_EQ_BAND_2_PG: |
1040 | case WM8994_AIF1_DAC2_EQ_BAND_3_A: |
1041 | case WM8994_AIF1_DAC2_EQ_BAND_3_B: |
1042 | case WM8994_AIF1_DAC2_EQ_BAND_3_C: |
1043 | case WM8994_AIF1_DAC2_EQ_BAND_3_PG: |
1044 | case WM8994_AIF1_DAC2_EQ_BAND_4_A: |
1045 | case WM8994_AIF1_DAC2_EQ_BAND_4_B: |
1046 | case WM8994_AIF1_DAC2_EQ_BAND_4_C: |
1047 | case WM8994_AIF1_DAC2_EQ_BAND_4_PG: |
1048 | case WM8994_AIF1_DAC2_EQ_BAND_5_A: |
1049 | case WM8994_AIF1_DAC2_EQ_BAND_5_B: |
1050 | case WM8994_AIF1_DAC2_EQ_BAND_5_PG: |
1051 | case WM8994_AIF1_DAC2_EQ_BAND_1_C: |
1052 | case WM8994_DAC2_MIXER_VOLUMES: |
1053 | case WM8994_DAC2_LEFT_MIXER_ROUTING: |
1054 | case WM8994_DAC2_RIGHT_MIXER_ROUTING: |
1055 | case WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING: |
1056 | case WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING: |
1057 | case WM8994_DAC2_LEFT_VOLUME: |
1058 | case WM8994_DAC2_RIGHT_VOLUME: |
1059 | return true; |
1060 | default: |
1061 | return wm1811_readable_register(dev, reg); |
1062 | } |
1063 | } |
1064 | |
1065 | static bool wm8958_readable_register(struct device *dev, unsigned int reg) |
1066 | { |
1067 | switch (reg) { |
1068 | case WM8958_DSP2_PROGRAM: |
1069 | case WM8958_DSP2_CONFIG: |
1070 | case WM8958_DSP2_MAGICNUM: |
1071 | case WM8958_DSP2_RELEASEYEAR: |
1072 | case WM8958_DSP2_RELEASEMONTHDAY: |
1073 | case WM8958_DSP2_RELEASETIME: |
1074 | case WM8958_DSP2_VERMAJMIN: |
1075 | case WM8958_DSP2_VERBUILD: |
1076 | case WM8958_DSP2_TESTREG: |
1077 | case WM8958_DSP2_XORREG: |
1078 | case WM8958_DSP2_SHIFTMAXX: |
1079 | case WM8958_DSP2_SHIFTMAXY: |
1080 | case WM8958_DSP2_SHIFTMAXZ: |
1081 | case WM8958_DSP2_SHIFTMAXEXTLO: |
1082 | case WM8958_DSP2_AESSELECT: |
1083 | case WM8958_DSP2_EXECCONTROL: |
1084 | case WM8958_DSP2_SAMPLEBREAK: |
1085 | case WM8958_DSP2_COUNTBREAK: |
1086 | case WM8958_DSP2_INTSTATUS: |
1087 | case WM8958_DSP2_EVENTSTATUS: |
1088 | case WM8958_DSP2_INTMASK: |
1089 | case WM8958_DSP2_CONFIGDWIDTH: |
1090 | case WM8958_DSP2_CONFIGINSTR: |
1091 | case WM8958_DSP2_CONFIGDMEM: |
1092 | case WM8958_DSP2_CONFIGDELAYS: |
1093 | case WM8958_DSP2_CONFIGNUMIO: |
1094 | case WM8958_DSP2_CONFIGEXTDEPTH: |
1095 | case WM8958_DSP2_CONFIGMULTIPLIER: |
1096 | case WM8958_DSP2_CONFIGCTRLDWIDTH: |
1097 | case WM8958_DSP2_CONFIGPIPELINE: |
1098 | case WM8958_DSP2_SHIFTMAXEXTHI: |
1099 | case WM8958_DSP2_SWVERSIONREG: |
1100 | case WM8958_DSP2_CONFIGXMEM: |
1101 | case WM8958_DSP2_CONFIGYMEM: |
1102 | case WM8958_DSP2_CONFIGZMEM: |
1103 | case WM8958_FW_BUILD_1: |
1104 | case WM8958_FW_BUILD_0: |
1105 | case WM8958_FW_ID_1: |
1106 | case WM8958_FW_ID_0: |
1107 | case WM8958_FW_MAJOR_1: |
1108 | case WM8958_FW_MAJOR_0: |
1109 | case WM8958_FW_MINOR_1: |
1110 | case WM8958_FW_MINOR_0: |
1111 | case WM8958_FW_PATCH_1: |
1112 | case WM8958_FW_PATCH_0: |
1113 | case WM8958_MBC_BAND_1_K_1: |
1114 | case WM8958_MBC_BAND_1_K_2: |
1115 | case WM8958_MBC_BAND_1_N1_1: |
1116 | case WM8958_MBC_BAND_1_N1_2: |
1117 | case WM8958_MBC_BAND_1_N2_1: |
1118 | case WM8958_MBC_BAND_1_N2_2: |
1119 | case WM8958_MBC_BAND_1_N3_1: |
1120 | case WM8958_MBC_BAND_1_N3_2: |
1121 | case WM8958_MBC_BAND_1_N4_1: |
1122 | case WM8958_MBC_BAND_1_N4_2: |
1123 | case WM8958_MBC_BAND_1_N5_1: |
1124 | case WM8958_MBC_BAND_1_N5_2: |
1125 | case WM8958_MBC_BAND_1_X1_1: |
1126 | case WM8958_MBC_BAND_1_X1_2: |
1127 | case WM8958_MBC_BAND_1_X2_1: |
1128 | case WM8958_MBC_BAND_1_X2_2: |
1129 | case WM8958_MBC_BAND_1_X3_1: |
1130 | case WM8958_MBC_BAND_1_X3_2: |
1131 | case WM8958_MBC_BAND_1_ATTACK_1: |
1132 | case WM8958_MBC_BAND_1_ATTACK_2: |
1133 | case WM8958_MBC_BAND_1_DECAY_1: |
1134 | case WM8958_MBC_BAND_1_DECAY_2: |
1135 | case WM8958_MBC_BAND_2_K_1: |
1136 | case WM8958_MBC_BAND_2_K_2: |
1137 | case WM8958_MBC_BAND_2_N1_1: |
1138 | case WM8958_MBC_BAND_2_N1_2: |
1139 | case WM8958_MBC_BAND_2_N2_1: |
1140 | case WM8958_MBC_BAND_2_N2_2: |
1141 | case WM8958_MBC_BAND_2_N3_1: |
1142 | case WM8958_MBC_BAND_2_N3_2: |
1143 | case WM8958_MBC_BAND_2_N4_1: |
1144 | case WM8958_MBC_BAND_2_N4_2: |
1145 | case WM8958_MBC_BAND_2_N5_1: |
1146 | case WM8958_MBC_BAND_2_N5_2: |
1147 | case WM8958_MBC_BAND_2_X1_1: |
1148 | case WM8958_MBC_BAND_2_X1_2: |
1149 | case WM8958_MBC_BAND_2_X2_1: |
1150 | case WM8958_MBC_BAND_2_X2_2: |
1151 | case WM8958_MBC_BAND_2_X3_1: |
1152 | case WM8958_MBC_BAND_2_X3_2: |
1153 | case WM8958_MBC_BAND_2_ATTACK_1: |
1154 | case WM8958_MBC_BAND_2_ATTACK_2: |
1155 | case WM8958_MBC_BAND_2_DECAY_1: |
1156 | case WM8958_MBC_BAND_2_DECAY_2: |
1157 | case WM8958_MBC_B2_PG2_1: |
1158 | case WM8958_MBC_B2_PG2_2: |
1159 | case WM8958_MBC_B1_PG2_1: |
1160 | case WM8958_MBC_B1_PG2_2: |
1161 | case WM8958_MBC_CROSSOVER_1: |
1162 | case WM8958_MBC_CROSSOVER_2: |
1163 | case WM8958_MBC_HPF_1: |
1164 | case WM8958_MBC_HPF_2: |
1165 | case WM8958_MBC_LPF_1: |
1166 | case WM8958_MBC_LPF_2: |
1167 | case WM8958_MBC_RMS_LIMIT_1: |
1168 | case WM8958_MBC_RMS_LIMIT_2: |
1169 | return true; |
1170 | default: |
1171 | return wm8994_readable_register(dev, reg); |
1172 | } |
1173 | } |
1174 | |
1175 | static bool wm8994_volatile_register(struct device *dev, unsigned int reg) |
1176 | { |
1177 | switch (reg) { |
1178 | case WM8994_SOFTWARE_RESET: |
1179 | case WM8994_DC_SERVO_1: |
1180 | case WM8994_DC_SERVO_READBACK: |
1181 | case WM8994_RATE_STATUS: |
1182 | case WM8958_MIC_DETECT_3: |
1183 | case WM8994_DC_SERVO_4E: |
1184 | case WM8994_INTERRUPT_STATUS_1: |
1185 | case WM8994_INTERRUPT_STATUS_2: |
1186 | return true; |
1187 | default: |
1188 | return false; |
1189 | } |
1190 | } |
1191 | |
1192 | static bool wm1811_volatile_register(struct device *dev, unsigned int reg) |
1193 | { |
1194 | struct wm8994 *wm8994 = dev_get_drvdata(dev); |
1195 | |
1196 | switch (reg) { |
1197 | case WM8994_GPIO_6: |
1198 | if (wm8994->cust_id > 1 || wm8994->revision > 1) |
1199 | return true; |
1200 | else |
1201 | return false; |
1202 | default: |
1203 | return wm8994_volatile_register(dev, reg); |
1204 | } |
1205 | } |
1206 | |
1207 | static bool wm8958_volatile_register(struct device *dev, unsigned int reg) |
1208 | { |
1209 | switch (reg) { |
1210 | case WM8958_DSP2_MAGICNUM: |
1211 | case WM8958_DSP2_RELEASEYEAR: |
1212 | case WM8958_DSP2_RELEASEMONTHDAY: |
1213 | case WM8958_DSP2_RELEASETIME: |
1214 | case WM8958_DSP2_VERMAJMIN: |
1215 | case WM8958_DSP2_VERBUILD: |
1216 | case WM8958_DSP2_EXECCONTROL: |
1217 | case WM8958_DSP2_SWVERSIONREG: |
1218 | case WM8958_DSP2_CONFIGXMEM: |
1219 | case WM8958_DSP2_CONFIGYMEM: |
1220 | case WM8958_DSP2_CONFIGZMEM: |
1221 | case WM8958_FW_BUILD_1: |
1222 | case WM8958_FW_BUILD_0: |
1223 | case WM8958_FW_ID_1: |
1224 | case WM8958_FW_ID_0: |
1225 | case WM8958_FW_MAJOR_1: |
1226 | case WM8958_FW_MAJOR_0: |
1227 | case WM8958_FW_MINOR_1: |
1228 | case WM8958_FW_MINOR_0: |
1229 | case WM8958_FW_PATCH_1: |
1230 | case WM8958_FW_PATCH_0: |
1231 | return true; |
1232 | default: |
1233 | return wm8994_volatile_register(dev, reg); |
1234 | } |
1235 | } |
1236 | |
1237 | struct regmap_config wm1811_regmap_config = { |
1238 | .reg_bits = 16, |
1239 | .val_bits = 16, |
1240 | |
1241 | .cache_type = REGCACHE_MAPLE, |
1242 | |
1243 | .reg_defaults = wm1811_defaults, |
1244 | .num_reg_defaults = ARRAY_SIZE(wm1811_defaults), |
1245 | |
1246 | .max_register = WM8994_MAX_REGISTER, |
1247 | .volatile_reg = wm1811_volatile_register, |
1248 | .readable_reg = wm1811_readable_register, |
1249 | }; |
1250 | EXPORT_SYMBOL(wm1811_regmap_config); |
1251 | |
1252 | struct regmap_config wm8994_regmap_config = { |
1253 | .reg_bits = 16, |
1254 | .val_bits = 16, |
1255 | |
1256 | .cache_type = REGCACHE_MAPLE, |
1257 | |
1258 | .reg_defaults = wm8994_defaults, |
1259 | .num_reg_defaults = ARRAY_SIZE(wm8994_defaults), |
1260 | |
1261 | .max_register = WM8994_MAX_REGISTER, |
1262 | .volatile_reg = wm8994_volatile_register, |
1263 | .readable_reg = wm8994_readable_register, |
1264 | }; |
1265 | EXPORT_SYMBOL(wm8994_regmap_config); |
1266 | |
1267 | struct regmap_config wm8958_regmap_config = { |
1268 | .reg_bits = 16, |
1269 | .val_bits = 16, |
1270 | |
1271 | .cache_type = REGCACHE_MAPLE, |
1272 | |
1273 | .reg_defaults = wm8958_defaults, |
1274 | .num_reg_defaults = ARRAY_SIZE(wm8958_defaults), |
1275 | |
1276 | .max_register = WM8994_MAX_REGISTER, |
1277 | .volatile_reg = wm8958_volatile_register, |
1278 | .readable_reg = wm8958_readable_register, |
1279 | }; |
1280 | EXPORT_SYMBOL(wm8958_regmap_config); |
1281 | |
1282 | struct regmap_config wm8994_base_regmap_config = { |
1283 | .reg_bits = 16, |
1284 | .val_bits = 16, |
1285 | }; |
1286 | EXPORT_SYMBOL(wm8994_base_regmap_config); |
1287 | |