1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Synopsys DesignWare Multimedia Card Interface driver |
4 | * (Based on NXP driver for lpc 31xx) |
5 | * |
6 | * Copyright (C) 2009 NXP Semiconductors |
7 | * Copyright (C) 2009, 2010 Imagination Technologies Ltd. |
8 | */ |
9 | |
10 | #ifndef _DW_MMC_H_ |
11 | #define _DW_MMC_H_ |
12 | |
13 | #include <linux/scatterlist.h> |
14 | #include <linux/mmc/core.h> |
15 | #include <linux/dmaengine.h> |
16 | #include <linux/reset.h> |
17 | #include <linux/fault-inject.h> |
18 | #include <linux/hrtimer.h> |
19 | #include <linux/interrupt.h> |
20 | |
21 | enum dw_mci_state { |
22 | STATE_IDLE = 0, |
23 | STATE_SENDING_CMD, |
24 | STATE_SENDING_DATA, |
25 | STATE_DATA_BUSY, |
26 | STATE_SENDING_STOP, |
27 | STATE_DATA_ERROR, |
28 | STATE_SENDING_CMD11, |
29 | STATE_WAITING_CMD11_DONE, |
30 | }; |
31 | |
32 | enum { |
33 | EVENT_CMD_COMPLETE = 0, |
34 | EVENT_XFER_COMPLETE, |
35 | EVENT_DATA_COMPLETE, |
36 | EVENT_DATA_ERROR, |
37 | }; |
38 | |
39 | enum dw_mci_cookie { |
40 | COOKIE_UNMAPPED, |
41 | COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */ |
42 | COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */ |
43 | }; |
44 | |
45 | struct mmc_data; |
46 | |
47 | enum { |
48 | TRANS_MODE_PIO = 0, |
49 | TRANS_MODE_IDMAC, |
50 | TRANS_MODE_EDMAC |
51 | }; |
52 | |
53 | struct dw_mci_dma_slave { |
54 | struct dma_chan *ch; |
55 | enum dma_transfer_direction direction; |
56 | }; |
57 | |
58 | /** |
59 | * struct dw_mci - MMC controller state shared between all slots |
60 | * @lock: Spinlock protecting the queue and associated data. |
61 | * @irq_lock: Spinlock protecting the INTMASK setting. |
62 | * @regs: Pointer to MMIO registers. |
63 | * @fifo_reg: Pointer to MMIO registers for data FIFO |
64 | * @sg: Scatterlist entry currently being processed by PIO code, if any. |
65 | * @sg_miter: PIO mapping scatterlist iterator. |
66 | * @mrq: The request currently being processed on @slot, |
67 | * or NULL if the controller is idle. |
68 | * @cmd: The command currently being sent to the card, or NULL. |
69 | * @data: The data currently being transferred, or NULL if no data |
70 | * transfer is in progress. |
71 | * @stop_abort: The command currently prepared for stoping transfer. |
72 | * @prev_blksz: The former transfer blksz record. |
73 | * @timing: Record of current ios timing. |
74 | * @use_dma: Which DMA channel is in use for the current transfer, zero |
75 | * denotes PIO mode. |
76 | * @using_dma: Whether DMA is in use for the current transfer. |
77 | * @dma_64bit_address: Whether DMA supports 64-bit address mode or not. |
78 | * @sg_dma: Bus address of DMA buffer. |
79 | * @sg_cpu: Virtual address of DMA buffer. |
80 | * @dma_ops: Pointer to platform-specific DMA callbacks. |
81 | * @cmd_status: Snapshot of SR taken upon completion of the current |
82 | * @ring_size: Buffer size for idma descriptors. |
83 | * command. Only valid when EVENT_CMD_COMPLETE is pending. |
84 | * @dms: structure of slave-dma private data. |
85 | * @phy_regs: physical address of controller's register map |
86 | * @data_status: Snapshot of SR taken upon completion of the current |
87 | * data transfer. Only valid when EVENT_DATA_COMPLETE or |
88 | * EVENT_DATA_ERROR is pending. |
89 | * @stop_cmdr: Value to be loaded into CMDR when the stop command is |
90 | * to be sent. |
91 | * @dir_status: Direction of current transfer. |
92 | * @tasklet: Tasklet running the request state machine. |
93 | * @pending_events: Bitmask of events flagged by the interrupt handler |
94 | * to be processed by the tasklet. |
95 | * @completed_events: Bitmask of events which the state machine has |
96 | * processed. |
97 | * @state: Tasklet state. |
98 | * @queue: List of slots waiting for access to the controller. |
99 | * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus |
100 | * rate and timeout calculations. |
101 | * @current_speed: Configured rate of the controller. |
102 | * @minimum_speed: Stored minimum rate of the controller. |
103 | * @fifoth_val: The value of FIFOTH register. |
104 | * @verid: Denote Version ID. |
105 | * @dev: Device associated with the MMC controller. |
106 | * @pdata: Platform data associated with the MMC controller. |
107 | * @drv_data: Driver specific data for identified variant of the controller |
108 | * @priv: Implementation defined private data. |
109 | * @biu_clk: Pointer to bus interface unit clock instance. |
110 | * @ciu_clk: Pointer to card interface unit clock instance. |
111 | * @slot: Slots sharing this MMC controller. |
112 | * @fifo_depth: depth of FIFO. |
113 | * @data_addr_override: override fifo reg offset with this value. |
114 | * @wm_aligned: force fifo watermark equal with data length in PIO mode. |
115 | * Set as true if alignment is needed. |
116 | * @data_shift: log2 of FIFO item size. |
117 | * @part_buf_start: Start index in part_buf. |
118 | * @part_buf_count: Bytes of partial data in part_buf. |
119 | * @part_buf: Simple buffer for partial fifo reads/writes. |
120 | * @push_data: Pointer to FIFO push function. |
121 | * @pull_data: Pointer to FIFO pull function. |
122 | * @quirks: Set of quirks that apply to specific versions of the IP. |
123 | * @vqmmc_enabled: Status of vqmmc, should be true or false. |
124 | * @irq_flags: The flags to be passed to request_irq. |
125 | * @irq: The irq value to be passed to request_irq. |
126 | * @sdio_id0: Number of slot0 in the SDIO interrupt registers. |
127 | * @cmd11_timer: Timer for SD3.0 voltage switch over scheme. |
128 | * @cto_timer: Timer for broken command transfer over scheme. |
129 | * @dto_timer: Timer for broken data transfer over scheme. |
130 | * |
131 | * Locking |
132 | * ======= |
133 | * |
134 | * @lock is a softirq-safe spinlock protecting @queue as well as |
135 | * @slot, @mrq and @state. These must always be updated |
136 | * at the same time while holding @lock. |
137 | * The @mrq field of struct dw_mci_slot is also protected by @lock, |
138 | * and must always be written at the same time as the slot is added to |
139 | * @queue. |
140 | * |
141 | * @irq_lock is an irq-safe spinlock protecting the INTMASK register |
142 | * to allow the interrupt handler to modify it directly. Held for only long |
143 | * enough to read-modify-write INTMASK and no other locks are grabbed when |
144 | * holding this one. |
145 | * |
146 | * @pending_events and @completed_events are accessed using atomic bit |
147 | * operations, so they don't need any locking. |
148 | * |
149 | * None of the fields touched by the interrupt handler need any |
150 | * locking. However, ordering is important: Before EVENT_DATA_ERROR or |
151 | * EVENT_DATA_COMPLETE is set in @pending_events, all data-related |
152 | * interrupts must be disabled and @data_status updated with a |
153 | * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the |
154 | * CMDRDY interrupt must be disabled and @cmd_status updated with a |
155 | * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the |
156 | * bytes_xfered field of @data must be written. This is ensured by |
157 | * using barriers. |
158 | */ |
159 | struct dw_mci { |
160 | spinlock_t lock; |
161 | spinlock_t irq_lock; |
162 | void __iomem *regs; |
163 | void __iomem *fifo_reg; |
164 | u32 data_addr_override; |
165 | bool wm_aligned; |
166 | |
167 | struct scatterlist *sg; |
168 | struct sg_mapping_iter sg_miter; |
169 | |
170 | struct mmc_request *mrq; |
171 | struct mmc_command *cmd; |
172 | struct mmc_data *data; |
173 | struct mmc_command stop_abort; |
174 | unsigned int prev_blksz; |
175 | unsigned char timing; |
176 | |
177 | /* DMA interface members*/ |
178 | int use_dma; |
179 | int using_dma; |
180 | int dma_64bit_address; |
181 | |
182 | dma_addr_t sg_dma; |
183 | void *sg_cpu; |
184 | const struct dw_mci_dma_ops *dma_ops; |
185 | /* For idmac */ |
186 | unsigned int ring_size; |
187 | |
188 | /* For edmac */ |
189 | struct dw_mci_dma_slave *dms; |
190 | /* Registers's physical base address */ |
191 | resource_size_t phy_regs; |
192 | |
193 | u32 cmd_status; |
194 | u32 data_status; |
195 | u32 stop_cmdr; |
196 | u32 dir_status; |
197 | struct tasklet_struct tasklet; |
198 | unsigned long pending_events; |
199 | unsigned long completed_events; |
200 | enum dw_mci_state state; |
201 | struct list_head queue; |
202 | |
203 | u32 bus_hz; |
204 | u32 current_speed; |
205 | u32 minimum_speed; |
206 | u32 fifoth_val; |
207 | u16 verid; |
208 | struct device *dev; |
209 | struct dw_mci_board *pdata; |
210 | const struct dw_mci_drv_data *drv_data; |
211 | void *priv; |
212 | struct clk *biu_clk; |
213 | struct clk *ciu_clk; |
214 | struct dw_mci_slot *slot; |
215 | |
216 | /* FIFO push and pull */ |
217 | int fifo_depth; |
218 | int data_shift; |
219 | u8 part_buf_start; |
220 | u8 part_buf_count; |
221 | union { |
222 | u16 part_buf16; |
223 | u32 part_buf32; |
224 | u64 part_buf; |
225 | }; |
226 | void (*push_data)(struct dw_mci *host, void *buf, int cnt); |
227 | void (*pull_data)(struct dw_mci *host, void *buf, int cnt); |
228 | |
229 | u32 quirks; |
230 | bool vqmmc_enabled; |
231 | unsigned long irq_flags; /* IRQ flags */ |
232 | int irq; |
233 | |
234 | int sdio_id0; |
235 | |
236 | struct timer_list cmd11_timer; |
237 | struct timer_list cto_timer; |
238 | struct timer_list dto_timer; |
239 | |
240 | #ifdef CONFIG_FAULT_INJECTION |
241 | struct fault_attr fail_data_crc; |
242 | struct hrtimer fault_timer; |
243 | #endif |
244 | }; |
245 | |
246 | /* DMA ops for Internal/External DMAC interface */ |
247 | struct dw_mci_dma_ops { |
248 | /* DMA Ops */ |
249 | int (*init)(struct dw_mci *host); |
250 | int (*start)(struct dw_mci *host, unsigned int sg_len); |
251 | void (*complete)(void *host); |
252 | void (*stop)(struct dw_mci *host); |
253 | void (*cleanup)(struct dw_mci *host); |
254 | void (*exit)(struct dw_mci *host); |
255 | }; |
256 | |
257 | struct dma_pdata; |
258 | |
259 | /* Board platform data */ |
260 | struct dw_mci_board { |
261 | unsigned int bus_hz; /* Clock speed at the cclk_in pad */ |
262 | |
263 | u32 caps; /* Capabilities */ |
264 | u32 caps2; /* More capabilities */ |
265 | u32 pm_caps; /* PM capabilities */ |
266 | /* |
267 | * Override fifo depth. If 0, autodetect it from the FIFOTH register, |
268 | * but note that this may not be reliable after a bootloader has used |
269 | * it. |
270 | */ |
271 | unsigned int fifo_depth; |
272 | |
273 | /* delay in mS before detecting cards after interrupt */ |
274 | u32 detect_delay_ms; |
275 | |
276 | struct reset_control *rstc; |
277 | struct dw_mci_dma_ops *dma_ops; |
278 | struct dma_pdata *data; |
279 | }; |
280 | |
281 | /* Support for longer data read timeout */ |
282 | #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0) |
283 | |
284 | #define DW_MMC_240A 0x240a |
285 | #define DW_MMC_280A 0x280a |
286 | |
287 | #define SDMMC_CTRL 0x000 |
288 | #define SDMMC_PWREN 0x004 |
289 | #define SDMMC_CLKDIV 0x008 |
290 | #define SDMMC_CLKSRC 0x00c |
291 | #define SDMMC_CLKENA 0x010 |
292 | #define SDMMC_TMOUT 0x014 |
293 | #define SDMMC_CTYPE 0x018 |
294 | #define SDMMC_BLKSIZ 0x01c |
295 | #define SDMMC_BYTCNT 0x020 |
296 | #define SDMMC_INTMASK 0x024 |
297 | #define SDMMC_CMDARG 0x028 |
298 | #define SDMMC_CMD 0x02c |
299 | #define SDMMC_RESP0 0x030 |
300 | #define SDMMC_RESP1 0x034 |
301 | #define SDMMC_RESP2 0x038 |
302 | #define SDMMC_RESP3 0x03c |
303 | #define SDMMC_MINTSTS 0x040 |
304 | #define SDMMC_RINTSTS 0x044 |
305 | #define SDMMC_STATUS 0x048 |
306 | #define SDMMC_FIFOTH 0x04c |
307 | #define SDMMC_CDETECT 0x050 |
308 | #define SDMMC_WRTPRT 0x054 |
309 | #define SDMMC_GPIO 0x058 |
310 | #define SDMMC_TCBCNT 0x05c |
311 | #define SDMMC_TBBCNT 0x060 |
312 | #define SDMMC_DEBNCE 0x064 |
313 | #define SDMMC_USRID 0x068 |
314 | #define SDMMC_VERID 0x06c |
315 | #define SDMMC_HCON 0x070 |
316 | #define SDMMC_UHS_REG 0x074 |
317 | #define SDMMC_RST_N 0x078 |
318 | #define SDMMC_BMOD 0x080 |
319 | #define SDMMC_PLDMND 0x084 |
320 | #define SDMMC_DBADDR 0x088 |
321 | #define SDMMC_IDSTS 0x08c |
322 | #define SDMMC_IDINTEN 0x090 |
323 | #define SDMMC_DSCADDR 0x094 |
324 | #define SDMMC_BUFADDR 0x098 |
325 | #define SDMMC_CDTHRCTL 0x100 |
326 | #define SDMMC_UHS_REG_EXT 0x108 |
327 | #define SDMMC_DDR_REG 0x10c |
328 | #define SDMMC_ENABLE_SHIFT 0x110 |
329 | #define SDMMC_DATA(x) (x) |
330 | /* |
331 | * Registers to support idmac 64-bit address mode |
332 | */ |
333 | #define SDMMC_DBADDRL 0x088 |
334 | #define SDMMC_DBADDRU 0x08c |
335 | #define SDMMC_IDSTS64 0x090 |
336 | #define SDMMC_IDINTEN64 0x094 |
337 | #define SDMMC_DSCADDRL 0x098 |
338 | #define SDMMC_DSCADDRU 0x09c |
339 | #define SDMMC_BUFADDRL 0x0A0 |
340 | #define SDMMC_BUFADDRU 0x0A4 |
341 | |
342 | /* |
343 | * Data offset is difference according to Version |
344 | * Lower than 2.40a : data register offest is 0x100 |
345 | */ |
346 | #define DATA_OFFSET 0x100 |
347 | #define DATA_240A_OFFSET 0x200 |
348 | |
349 | /* shift bit field */ |
350 | #define _SBF(f, v) ((v) << (f)) |
351 | |
352 | /* Control register defines */ |
353 | #define SDMMC_CTRL_USE_IDMAC BIT(25) |
354 | #define SDMMC_CTRL_CEATA_INT_EN BIT(11) |
355 | #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) |
356 | #define SDMMC_CTRL_SEND_CCSD BIT(9) |
357 | #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) |
358 | #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) |
359 | #define SDMMC_CTRL_READ_WAIT BIT(6) |
360 | #define SDMMC_CTRL_DMA_ENABLE BIT(5) |
361 | #define SDMMC_CTRL_INT_ENABLE BIT(4) |
362 | #define SDMMC_CTRL_DMA_RESET BIT(2) |
363 | #define SDMMC_CTRL_FIFO_RESET BIT(1) |
364 | #define SDMMC_CTRL_RESET BIT(0) |
365 | /* Clock Enable register defines */ |
366 | #define SDMMC_CLKEN_LOW_PWR BIT(16) |
367 | #define SDMMC_CLKEN_ENABLE BIT(0) |
368 | /* time-out register defines */ |
369 | #define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) |
370 | #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 |
371 | #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) |
372 | #define SDMMC_TMOUT_RESP_MSK 0xFF |
373 | /* card-type register defines */ |
374 | #define SDMMC_CTYPE_8BIT BIT(16) |
375 | #define SDMMC_CTYPE_4BIT BIT(0) |
376 | #define SDMMC_CTYPE_1BIT 0 |
377 | /* Interrupt status & mask register defines */ |
378 | #define SDMMC_INT_SDIO(n) BIT(16 + (n)) |
379 | #define SDMMC_INT_EBE BIT(15) |
380 | #define SDMMC_INT_ACD BIT(14) |
381 | #define SDMMC_INT_SBE BIT(13) |
382 | #define SDMMC_INT_HLE BIT(12) |
383 | #define SDMMC_INT_FRUN BIT(11) |
384 | #define SDMMC_INT_HTO BIT(10) |
385 | #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */ |
386 | #define SDMMC_INT_DRTO BIT(9) |
387 | #define SDMMC_INT_RTO BIT(8) |
388 | #define SDMMC_INT_DCRC BIT(7) |
389 | #define SDMMC_INT_RCRC BIT(6) |
390 | #define SDMMC_INT_RXDR BIT(5) |
391 | #define SDMMC_INT_TXDR BIT(4) |
392 | #define SDMMC_INT_DATA_OVER BIT(3) |
393 | #define SDMMC_INT_CMD_DONE BIT(2) |
394 | #define SDMMC_INT_RESP_ERR BIT(1) |
395 | #define SDMMC_INT_CD BIT(0) |
396 | #define SDMMC_INT_ERROR 0xbfc2 |
397 | /* Command register defines */ |
398 | #define SDMMC_CMD_START BIT(31) |
399 | #define SDMMC_CMD_USE_HOLD_REG BIT(29) |
400 | #define SDMMC_CMD_VOLT_SWITCH BIT(28) |
401 | #define SDMMC_CMD_CCS_EXP BIT(23) |
402 | #define SDMMC_CMD_CEATA_RD BIT(22) |
403 | #define SDMMC_CMD_UPD_CLK BIT(21) |
404 | #define SDMMC_CMD_INIT BIT(15) |
405 | #define SDMMC_CMD_STOP BIT(14) |
406 | #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) |
407 | #define SDMMC_CMD_SEND_STOP BIT(12) |
408 | #define SDMMC_CMD_STRM_MODE BIT(11) |
409 | #define SDMMC_CMD_DAT_WR BIT(10) |
410 | #define SDMMC_CMD_DAT_EXP BIT(9) |
411 | #define SDMMC_CMD_RESP_CRC BIT(8) |
412 | #define SDMMC_CMD_RESP_LONG BIT(7) |
413 | #define SDMMC_CMD_RESP_EXP BIT(6) |
414 | #define SDMMC_CMD_INDX(n) ((n) & 0x1F) |
415 | /* Status register defines */ |
416 | #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) |
417 | #define SDMMC_STATUS_DMA_REQ BIT(31) |
418 | #define SDMMC_STATUS_BUSY BIT(9) |
419 | /* FIFOTH register defines */ |
420 | #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ |
421 | ((r) & 0xFFF) << 16 | \ |
422 | ((t) & 0xFFF)) |
423 | /* HCON register defines */ |
424 | #define DMA_INTERFACE_IDMA (0x0) |
425 | #define DMA_INTERFACE_DWDMA (0x1) |
426 | #define DMA_INTERFACE_GDMA (0x2) |
427 | #define DMA_INTERFACE_NODMA (0x3) |
428 | #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3) |
429 | #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1) |
430 | #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7) |
431 | #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1) |
432 | /* Internal DMAC interrupt defines */ |
433 | #define SDMMC_IDMAC_INT_AI BIT(9) |
434 | #define SDMMC_IDMAC_INT_NI BIT(8) |
435 | #define SDMMC_IDMAC_INT_CES BIT(5) |
436 | #define SDMMC_IDMAC_INT_DU BIT(4) |
437 | #define SDMMC_IDMAC_INT_FBE BIT(2) |
438 | #define SDMMC_IDMAC_INT_RI BIT(1) |
439 | #define SDMMC_IDMAC_INT_TI BIT(0) |
440 | /* Internal DMAC bus mode bits */ |
441 | #define SDMMC_IDMAC_ENABLE BIT(7) |
442 | #define SDMMC_IDMAC_FB BIT(1) |
443 | #define SDMMC_IDMAC_SWRESET BIT(0) |
444 | /* H/W reset */ |
445 | #define SDMMC_RST_HWACTIVE 0x1 |
446 | /* Version ID register define */ |
447 | #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) |
448 | /* Card read threshold */ |
449 | #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x)) |
450 | #define SDMMC_CARD_WR_THR_EN BIT(2) |
451 | #define SDMMC_CARD_RD_THR_EN BIT(0) |
452 | /* UHS-1 register defines */ |
453 | #define SDMMC_UHS_DDR BIT(16) |
454 | #define SDMMC_UHS_18V BIT(0) |
455 | /* DDR register defines */ |
456 | #define SDMMC_DDR_HS400 BIT(31) |
457 | /* Enable shift register defines */ |
458 | #define SDMMC_ENABLE_PHASE BIT(0) |
459 | /* All ctrl reset bits */ |
460 | #define SDMMC_CTRL_ALL_RESET_FLAGS \ |
461 | (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) |
462 | |
463 | /* FIFO register access macros. These should not change the data endian-ness |
464 | * as they are written to memory to be dealt with by the upper layers |
465 | */ |
466 | #define mci_fifo_readw(__reg) __raw_readw(__reg) |
467 | #define mci_fifo_readl(__reg) __raw_readl(__reg) |
468 | #define mci_fifo_readq(__reg) __raw_readq(__reg) |
469 | |
470 | #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value) |
471 | #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value) |
472 | #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value) |
473 | |
474 | /* Register access macros */ |
475 | #define mci_readl(dev, reg) \ |
476 | readl_relaxed((dev)->regs + SDMMC_##reg) |
477 | #define mci_writel(dev, reg, value) \ |
478 | writel_relaxed((value), (dev)->regs + SDMMC_##reg) |
479 | |
480 | /* 16-bit FIFO access macros */ |
481 | #define mci_readw(dev, reg) \ |
482 | readw_relaxed((dev)->regs + SDMMC_##reg) |
483 | #define mci_writew(dev, reg, value) \ |
484 | writew_relaxed((value), (dev)->regs + SDMMC_##reg) |
485 | |
486 | /* 64-bit FIFO access macros */ |
487 | #ifdef readq |
488 | #define mci_readq(dev, reg) \ |
489 | readq_relaxed((dev)->regs + SDMMC_##reg) |
490 | #define mci_writeq(dev, reg, value) \ |
491 | writeq_relaxed((value), (dev)->regs + SDMMC_##reg) |
492 | #else |
493 | /* |
494 | * Dummy readq implementation for architectures that don't define it. |
495 | * |
496 | * We would assume that none of these architectures would configure |
497 | * the IP block with a 64bit FIFO width, so this code will never be |
498 | * executed on those machines. Defining these macros here keeps the |
499 | * rest of the code free from ifdefs. |
500 | */ |
501 | #define mci_readq(dev, reg) \ |
502 | (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)) |
503 | #define mci_writeq(dev, reg, value) \ |
504 | (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) |
505 | |
506 | #define __raw_writeq(__value, __reg) \ |
507 | (*(volatile u64 __force *)(__reg) = (__value)) |
508 | #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg)) |
509 | #endif |
510 | |
511 | extern int dw_mci_probe(struct dw_mci *host); |
512 | extern void dw_mci_remove(struct dw_mci *host); |
513 | #ifdef CONFIG_PM |
514 | extern int dw_mci_runtime_suspend(struct device *device); |
515 | extern int dw_mci_runtime_resume(struct device *device); |
516 | #endif |
517 | |
518 | /** |
519 | * struct dw_mci_slot - MMC slot state |
520 | * @mmc: The mmc_host representing this slot. |
521 | * @host: The MMC controller this slot is using. |
522 | * @ctype: Card type for this slot. |
523 | * @mrq: mmc_request currently being processed or waiting to be |
524 | * processed, or NULL when the slot is idle. |
525 | * @queue_node: List node for placing this node in the @queue list of |
526 | * &struct dw_mci. |
527 | * @clock: Clock rate configured by set_ios(). Protected by host->lock. |
528 | * @__clk_old: The last clock value that was requested from core. |
529 | * Keeping track of this helps us to avoid spamming the console. |
530 | * @flags: Random state bits associated with the slot. |
531 | * @id: Number of this slot. |
532 | * @sdio_id: Number of this slot in the SDIO interrupt registers. |
533 | */ |
534 | struct dw_mci_slot { |
535 | struct mmc_host *mmc; |
536 | struct dw_mci *host; |
537 | |
538 | u32 ctype; |
539 | |
540 | struct mmc_request *mrq; |
541 | struct list_head queue_node; |
542 | |
543 | unsigned int clock; |
544 | unsigned int __clk_old; |
545 | |
546 | unsigned long flags; |
547 | #define DW_MMC_CARD_PRESENT 0 |
548 | #define DW_MMC_CARD_NEED_INIT 1 |
549 | #define DW_MMC_CARD_NO_LOW_PWR 2 |
550 | #define DW_MMC_CARD_NO_USE_HOLD 3 |
551 | #define DW_MMC_CARD_NEEDS_POLL 4 |
552 | int id; |
553 | int sdio_id; |
554 | }; |
555 | |
556 | /** |
557 | * dw_mci driver data - dw-mshc implementation specific driver data. |
558 | * @caps: mmc subsystem specified capabilities of the controller(s). |
559 | * @num_caps: number of capabilities specified by @caps. |
560 | * @common_caps: mmc subsystem specified capabilities applicable to all of |
561 | * the controllers |
562 | * @init: early implementation specific initialization. |
563 | * @set_ios: handle bus specific extensions. |
564 | * @parse_dt: parse implementation specific device tree properties. |
565 | * @execute_tuning: implementation specific tuning procedure. |
566 | * @set_data_timeout: implementation specific timeout. |
567 | * @get_drto_clks: implementation specific cycle count for data read timeout. |
568 | * |
569 | * Provide controller implementation specific extensions. The usage of this |
570 | * data structure is fully optional and usage of each member in this structure |
571 | * is optional as well. |
572 | */ |
573 | struct dw_mci_drv_data { |
574 | unsigned long *caps; |
575 | u32 num_caps; |
576 | u32 common_caps; |
577 | int (*init)(struct dw_mci *host); |
578 | void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); |
579 | int (*parse_dt)(struct dw_mci *host); |
580 | int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode); |
581 | int (*prepare_hs400_tuning)(struct dw_mci *host, |
582 | struct mmc_ios *ios); |
583 | int (*switch_voltage)(struct mmc_host *mmc, |
584 | struct mmc_ios *ios); |
585 | void (*set_data_timeout)(struct dw_mci *host, |
586 | unsigned int timeout_ns); |
587 | u32 (*get_drto_clks)(struct dw_mci *host); |
588 | }; |
589 | #endif /* _DW_MMC_H_ */ |
590 | |