| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2008 Marvell Semiconductors, All Rights Reserved. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __MVSDIO_H |
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| 7 | #define __MVSDIO_H |
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| 8 | |
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| 9 | /* |
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| 10 | * Clock rates |
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| 11 | */ |
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| 12 | |
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| 13 | #define MVSD_CLOCKRATE_MAX 50000000 |
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| 14 | #define MVSD_BASE_DIV_MAX 0x7ff |
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| 15 | |
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| 16 | |
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| 17 | /* |
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| 18 | * Register offsets |
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| 19 | */ |
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| 20 | |
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| 21 | #define MVSD_SYS_ADDR_LOW 0x000 |
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| 22 | #define MVSD_SYS_ADDR_HI 0x004 |
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| 23 | #define MVSD_BLK_SIZE 0x008 |
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| 24 | #define MVSD_BLK_COUNT 0x00c |
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| 25 | #define MVSD_ARG_LOW 0x010 |
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| 26 | #define MVSD_ARG_HI 0x014 |
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| 27 | #define MVSD_XFER_MODE 0x018 |
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| 28 | #define MVSD_CMD 0x01c |
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| 29 | #define MVSD_RSP(i) (0x020 + ((i)<<2)) |
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| 30 | #define MVSD_RSP0 0x020 |
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| 31 | #define MVSD_RSP1 0x024 |
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| 32 | #define MVSD_RSP2 0x028 |
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| 33 | #define MVSD_RSP3 0x02c |
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| 34 | #define MVSD_RSP4 0x030 |
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| 35 | #define MVSD_RSP5 0x034 |
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| 36 | #define MVSD_RSP6 0x038 |
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| 37 | #define MVSD_RSP7 0x03c |
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| 38 | #define MVSD_FIFO 0x040 |
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| 39 | #define MVSD_RSP_CRC7 0x044 |
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| 40 | #define MVSD_HW_STATE 0x048 |
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| 41 | #define MVSD_HOST_CTRL 0x050 |
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| 42 | #define MVSD_BLK_GAP_CTRL 0x054 |
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| 43 | #define MVSD_CLK_CTRL 0x058 |
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| 44 | #define MVSD_SW_RESET 0x05c |
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| 45 | #define MVSD_NOR_INTR_STATUS 0x060 |
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| 46 | #define MVSD_ERR_INTR_STATUS 0x064 |
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| 47 | #define MVSD_NOR_STATUS_EN 0x068 |
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| 48 | #define MVSD_ERR_STATUS_EN 0x06c |
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| 49 | #define MVSD_NOR_INTR_EN 0x070 |
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| 50 | #define MVSD_ERR_INTR_EN 0x074 |
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| 51 | #define MVSD_AUTOCMD12_ERR_STATUS 0x078 |
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| 52 | #define MVSD_CURR_BYTE_LEFT 0x07c |
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| 53 | #define MVSD_CURR_BLK_LEFT 0x080 |
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| 54 | #define MVSD_AUTOCMD12_ARG_LOW 0x084 |
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| 55 | #define MVSD_AUTOCMD12_ARG_HI 0x088 |
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| 56 | #define MVSD_AUTOCMD12_CMD 0x08c |
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| 57 | #define MVSD_AUTO_RSP(i) (0x090 + ((i)<<2)) |
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| 58 | #define MVSD_AUTO_RSP0 0x090 |
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| 59 | #define MVSD_AUTO_RSP1 0x094 |
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| 60 | #define MVSD_AUTO_RSP2 0x098 |
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| 61 | #define MVSD_CLK_DIV 0x128 |
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| 62 | |
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| 63 | #define MVSD_WINDOW_CTRL(i) (0x108 + ((i) << 3)) |
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| 64 | #define MVSD_WINDOW_BASE(i) (0x10c + ((i) << 3)) |
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| 65 | |
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| 66 | |
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| 67 | /* |
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| 68 | * MVSD_CMD |
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| 69 | */ |
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| 70 | |
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| 71 | #define MVSD_CMD_RSP_NONE (0 << 0) |
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| 72 | #define MVSD_CMD_RSP_136 (1 << 0) |
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| 73 | #define MVSD_CMD_RSP_48 (2 << 0) |
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| 74 | #define MVSD_CMD_RSP_48BUSY (3 << 0) |
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| 75 | |
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| 76 | #define MVSD_CMD_CHECK_DATACRC16 (1 << 2) |
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| 77 | #define MVSD_CMD_CHECK_CMDCRC (1 << 3) |
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| 78 | #define MVSD_CMD_INDX_CHECK (1 << 4) |
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| 79 | #define MVSD_CMD_DATA_PRESENT (1 << 5) |
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| 80 | #define MVSD_UNEXPECTED_RESP (1 << 7) |
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| 81 | #define MVSD_CMD_INDEX(x) ((x) << 8) |
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| 82 | |
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| 83 | |
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| 84 | /* |
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| 85 | * MVSD_AUTOCMD12_CMD |
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| 86 | */ |
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| 87 | |
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| 88 | #define MVSD_AUTOCMD12_BUSY (1 << 0) |
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| 89 | #define MVSD_AUTOCMD12_INDX_CHECK (1 << 1) |
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| 90 | #define MVSD_AUTOCMD12_INDEX(x) ((x) << 8) |
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| 91 | |
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| 92 | /* |
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| 93 | * MVSD_XFER_MODE |
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| 94 | */ |
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| 95 | |
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| 96 | #define MVSD_XFER_MODE_WR_DATA_START (1 << 0) |
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| 97 | #define MVSD_XFER_MODE_HW_WR_DATA_EN (1 << 1) |
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| 98 | #define MVSD_XFER_MODE_AUTO_CMD12 (1 << 2) |
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| 99 | #define MVSD_XFER_MODE_INT_CHK_EN (1 << 3) |
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| 100 | #define MVSD_XFER_MODE_TO_HOST (1 << 4) |
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| 101 | #define MVSD_XFER_MODE_STOP_CLK (1 << 5) |
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| 102 | #define MVSD_XFER_MODE_PIO (1 << 6) |
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| 103 | |
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| 104 | |
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| 105 | /* |
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| 106 | * MVSD_HOST_CTRL |
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| 107 | */ |
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| 108 | |
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| 109 | #define MVSD_HOST_CTRL_PUSH_PULL_EN (1 << 0) |
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| 110 | |
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| 111 | #define MVSD_HOST_CTRL_CARD_TYPE_MEM_ONLY (0 << 1) |
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| 112 | #define MVSD_HOST_CTRL_CARD_TYPE_IO_ONLY (1 << 1) |
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| 113 | #define MVSD_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO (2 << 1) |
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| 114 | #define MVSD_HOST_CTRL_CARD_TYPE_IO_MMC (3 << 1) |
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| 115 | #define MVSD_HOST_CTRL_CARD_TYPE_MASK (3 << 1) |
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| 116 | |
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| 117 | #define MVSD_HOST_CTRL_BIG_ENDIAN (1 << 3) |
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| 118 | #define MVSD_HOST_CTRL_LSB_FIRST (1 << 4) |
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| 119 | #define MVSD_HOST_CTRL_DATA_WIDTH_4_BITS (1 << 9) |
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| 120 | #define MVSD_HOST_CTRL_HI_SPEED_EN (1 << 10) |
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| 121 | |
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| 122 | #define MVSD_HOST_CTRL_TMOUT_MAX 0xf |
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| 123 | #define MVSD_HOST_CTRL_TMOUT_MASK (0xf << 11) |
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| 124 | #define MVSD_HOST_CTRL_TMOUT(x) ((x) << 11) |
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| 125 | #define MVSD_HOST_CTRL_TMOUT_EN (1 << 15) |
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| 126 | |
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| 127 | |
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| 128 | /* |
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| 129 | * MVSD_SW_RESET |
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| 130 | */ |
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| 131 | |
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| 132 | #define MVSD_SW_RESET_NOW (1 << 8) |
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| 133 | |
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| 134 | |
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| 135 | /* |
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| 136 | * Normal interrupt status bits |
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| 137 | */ |
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| 138 | |
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| 139 | #define MVSD_NOR_CMD_DONE (1 << 0) |
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| 140 | #define MVSD_NOR_XFER_DONE (1 << 1) |
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| 141 | #define MVSD_NOR_BLK_GAP_EVT (1 << 2) |
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| 142 | #define MVSD_NOR_DMA_DONE (1 << 3) |
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| 143 | #define MVSD_NOR_TX_AVAIL (1 << 4) |
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| 144 | #define MVSD_NOR_RX_READY (1 << 5) |
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| 145 | #define MVSD_NOR_CARD_INT (1 << 8) |
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| 146 | #define MVSD_NOR_READ_WAIT_ON (1 << 9) |
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| 147 | #define MVSD_NOR_RX_FIFO_8W (1 << 10) |
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| 148 | #define MVSD_NOR_TX_FIFO_8W (1 << 11) |
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| 149 | #define MVSD_NOR_SUSPEND_ON (1 << 12) |
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| 150 | #define MVSD_NOR_AUTOCMD12_DONE (1 << 13) |
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| 151 | #define MVSD_NOR_UNEXP_RSP (1 << 14) |
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| 152 | #define MVSD_NOR_ERROR (1 << 15) |
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| 153 | |
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| 154 | |
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| 155 | /* |
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| 156 | * Error status bits |
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| 157 | */ |
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| 158 | |
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| 159 | #define MVSD_ERR_CMD_TIMEOUT (1 << 0) |
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| 160 | #define MVSD_ERR_CMD_CRC (1 << 1) |
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| 161 | #define MVSD_ERR_CMD_ENDBIT (1 << 2) |
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| 162 | #define MVSD_ERR_CMD_INDEX (1 << 3) |
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| 163 | #define MVSD_ERR_DATA_TIMEOUT (1 << 4) |
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| 164 | #define MVSD_ERR_DATA_CRC (1 << 5) |
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| 165 | #define MVSD_ERR_DATA_ENDBIT (1 << 6) |
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| 166 | #define MVSD_ERR_AUTOCMD12 (1 << 8) |
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| 167 | #define MVSD_ERR_CMD_STARTBIT (1 << 9) |
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| 168 | #define MVSD_ERR_XFER_SIZE (1 << 10) |
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| 169 | #define MVSD_ERR_RESP_T_BIT (1 << 11) |
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| 170 | #define MVSD_ERR_CRC_ENDBIT (1 << 12) |
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| 171 | #define MVSD_ERR_CRC_STARTBIT (1 << 13) |
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| 172 | #define MVSD_ERR_CRC_STATUS (1 << 14) |
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| 173 | |
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| 174 | |
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| 175 | /* |
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| 176 | * CMD12 error status bits |
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| 177 | */ |
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| 178 | |
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| 179 | #define MVSD_AUTOCMD12_ERR_NOTEXE (1 << 0) |
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| 180 | #define MVSD_AUTOCMD12_ERR_TIMEOUT (1 << 1) |
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| 181 | #define MVSD_AUTOCMD12_ERR_CRC (1 << 2) |
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| 182 | #define MVSD_AUTOCMD12_ERR_ENDBIT (1 << 3) |
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| 183 | #define MVSD_AUTOCMD12_ERR_INDEX (1 << 4) |
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| 184 | #define MVSD_AUTOCMD12_ERR_RESP_T_BIT (1 << 5) |
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| 185 | #define MVSD_AUTOCMD12_ERR_RESP_STARTBIT (1 << 6) |
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| 186 | |
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| 187 | #endif |
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| 188 | |
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