| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #define MMC_STRPCL 0x0000 |
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| 3 | #define STOP_CLOCK (1 << 0) |
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| 4 | #define START_CLOCK (2 << 0) |
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| 5 | |
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| 6 | #define MMC_STAT 0x0004 |
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| 7 | #define STAT_END_CMD_RES (1 << 13) |
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| 8 | #define STAT_PRG_DONE (1 << 12) |
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| 9 | #define STAT_DATA_TRAN_DONE (1 << 11) |
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| 10 | #define STAT_CLK_EN (1 << 8) |
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| 11 | #define STAT_RECV_FIFO_FULL (1 << 7) |
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| 12 | #define STAT_XMIT_FIFO_EMPTY (1 << 6) |
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| 13 | #define STAT_RES_CRC_ERR (1 << 5) |
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| 14 | #define STAT_SPI_READ_ERROR_TOKEN (1 << 4) |
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| 15 | #define STAT_CRC_READ_ERROR (1 << 3) |
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| 16 | #define STAT_CRC_WRITE_ERROR (1 << 2) |
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| 17 | #define STAT_TIME_OUT_RESPONSE (1 << 1) |
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| 18 | #define STAT_READ_TIME_OUT (1 << 0) |
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| 19 | |
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| 20 | #define MMC_CLKRT 0x0008 /* 3 bit */ |
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| 21 | |
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| 22 | #define MMC_SPI 0x000c |
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| 23 | #define SPI_CS_ADDRESS (1 << 3) |
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| 24 | #define SPI_CS_EN (1 << 2) |
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| 25 | #define CRC_ON (1 << 1) |
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| 26 | #define SPI_EN (1 << 0) |
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| 27 | |
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| 28 | #define MMC_CMDAT 0x0010 |
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| 29 | #define CMDAT_SDIO_INT_EN (1 << 11) |
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| 30 | #define CMDAT_SD_4DAT (1 << 8) |
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| 31 | #define CMDAT_DMAEN (1 << 7) |
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| 32 | #define CMDAT_INIT (1 << 6) |
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| 33 | #define CMDAT_BUSY (1 << 5) |
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| 34 | #define CMDAT_STREAM (1 << 4) /* 1 = stream */ |
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| 35 | #define CMDAT_WRITE (1 << 3) /* 1 = write */ |
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| 36 | #define CMDAT_DATAEN (1 << 2) |
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| 37 | #define CMDAT_RESP_NONE (0 << 0) |
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| 38 | #define CMDAT_RESP_SHORT (1 << 0) |
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| 39 | #define CMDAT_RESP_R2 (2 << 0) |
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| 40 | #define CMDAT_RESP_R3 (3 << 0) |
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| 41 | |
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| 42 | #define MMC_RESTO 0x0014 /* 7 bit */ |
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| 43 | |
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| 44 | #define MMC_RDTO 0x0018 /* 16 bit */ |
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| 45 | |
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| 46 | #define MMC_BLKLEN 0x001c /* 10 bit */ |
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| 47 | |
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| 48 | #define MMC_NOB 0x0020 /* 16 bit */ |
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| 49 | |
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| 50 | #define MMC_PRTBUF 0x0024 |
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| 51 | #define BUF_PART_FULL (1 << 0) |
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| 52 | |
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| 53 | #define MMC_I_MASK 0x0028 |
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| 54 | |
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| 55 | /*PXA27x MMC interrupts*/ |
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| 56 | #define SDIO_SUSPEND_ACK (1 << 12) |
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| 57 | #define SDIO_INT (1 << 11) |
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| 58 | #define RD_STALLED (1 << 10) |
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| 59 | #define RES_ERR (1 << 9) |
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| 60 | #define DAT_ERR (1 << 8) |
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| 61 | #define TINT (1 << 7) |
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| 62 | |
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| 63 | /*PXA2xx MMC interrupts*/ |
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| 64 | #define TXFIFO_WR_REQ (1 << 6) |
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| 65 | #define RXFIFO_RD_REQ (1 << 5) |
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| 66 | #define CLK_IS_OFF (1 << 4) |
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| 67 | #define STOP_CMD (1 << 3) |
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| 68 | #define END_CMD_RES (1 << 2) |
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| 69 | #define PRG_DONE (1 << 1) |
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| 70 | #define DATA_TRAN_DONE (1 << 0) |
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| 71 | |
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| 72 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
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| 73 | #define MMC_I_MASK_ALL 0x00001fff |
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| 74 | #else |
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| 75 | #define MMC_I_MASK_ALL 0x0000007f |
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| 76 | #endif |
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| 77 | |
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| 78 | #define MMC_I_REG 0x002c |
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| 79 | /* same as MMC_I_MASK */ |
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| 80 | |
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| 81 | #define MMC_CMD 0x0030 |
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| 82 | |
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| 83 | #define MMC_ARGH 0x0034 /* 16 bit */ |
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| 84 | |
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| 85 | #define MMC_ARGL 0x0038 /* 16 bit */ |
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| 86 | |
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| 87 | #define MMC_RES 0x003c /* 16 bit */ |
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| 88 | |
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| 89 | #define MMC_RXFIFO 0x0040 /* 8 bit */ |
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| 90 | |
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| 91 | #define MMC_TXFIFO 0x0044 /* 8 bit */ |
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| 92 | |
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