1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef __SDHCI_PCI_H |
3 | #define __SDHCI_PCI_H |
4 | |
5 | /* |
6 | * PCI device IDs, sub IDs |
7 | */ |
8 | |
9 | #define PCI_DEVICE_ID_O2_SDS0 0x8420 |
10 | #define PCI_DEVICE_ID_O2_SDS1 0x8421 |
11 | #define PCI_DEVICE_ID_O2_FUJIN2 0x8520 |
12 | #define PCI_DEVICE_ID_O2_SEABIRD0 0x8620 |
13 | #define PCI_DEVICE_ID_O2_SEABIRD1 0x8621 |
14 | #define PCI_DEVICE_ID_O2_GG8_9860 0x9860 |
15 | #define PCI_DEVICE_ID_O2_GG8_9861 0x9861 |
16 | #define PCI_DEVICE_ID_O2_GG8_9862 0x9862 |
17 | #define PCI_DEVICE_ID_O2_GG8_9863 0x9863 |
18 | |
19 | #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809 |
20 | #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a |
21 | #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14 |
22 | #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15 |
23 | #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16 |
24 | #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50 |
25 | #define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294 |
26 | #define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295 |
27 | #define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296 |
28 | #define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190 |
29 | #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9 |
30 | #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa |
31 | #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb |
32 | #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5 |
33 | #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6 |
34 | #define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7 |
35 | #define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b |
36 | #define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c |
37 | #define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d |
38 | #define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db |
39 | #define PCI_DEVICE_ID_INTEL_CDF_EMMC 0x18db |
40 | #define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca |
41 | #define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc |
42 | #define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0 |
43 | #define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca |
44 | #define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc |
45 | #define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0 |
46 | #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca |
47 | #define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc |
48 | #define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0 |
49 | #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca |
50 | #define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc |
51 | #define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0 |
52 | #define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc4 |
53 | #define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df5 |
54 | #define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375 |
55 | #define PCI_DEVICE_ID_INTEL_ICP_EMMC 0x34c4 |
56 | #define PCI_DEVICE_ID_INTEL_ICP_SD 0x34f8 |
57 | #define PCI_DEVICE_ID_INTEL_EHL_EMMC 0x4b47 |
58 | #define PCI_DEVICE_ID_INTEL_EHL_SD 0x4b48 |
59 | #define PCI_DEVICE_ID_INTEL_CML_EMMC 0x02c4 |
60 | #define PCI_DEVICE_ID_INTEL_CML_SD 0x02f5 |
61 | #define PCI_DEVICE_ID_INTEL_CMLH_SD 0x06f5 |
62 | #define PCI_DEVICE_ID_INTEL_JSL_EMMC 0x4dc4 |
63 | #define PCI_DEVICE_ID_INTEL_JSL_SD 0x4df8 |
64 | #define PCI_DEVICE_ID_INTEL_LKF_EMMC 0x98c4 |
65 | #define PCI_DEVICE_ID_INTEL_LKF_SD 0x98f8 |
66 | #define PCI_DEVICE_ID_INTEL_ADL_EMMC 0x54c4 |
67 | |
68 | #define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000 |
69 | #define PCI_DEVICE_ID_VIA_95D0 0x95d0 |
70 | #define PCI_DEVICE_ID_REALTEK_5250 0x5250 |
71 | |
72 | #define PCI_SUBDEVICE_ID_NI_7884 0x7884 |
73 | #define PCI_SUBDEVICE_ID_NI_78E3 0x78e3 |
74 | |
75 | #define PCI_VENDOR_ID_ARASAN 0x16e6 |
76 | #define PCI_DEVICE_ID_ARASAN_PHY_EMMC 0x0670 |
77 | |
78 | #define PCI_DEVICE_ID_SYNOPSYS_DWC_MSHC 0xc202 |
79 | |
80 | #define PCI_DEVICE_ID_GLI_9755 0x9755 |
81 | #define PCI_DEVICE_ID_GLI_9750 0x9750 |
82 | #define PCI_DEVICE_ID_GLI_9763E 0xe763 |
83 | #define PCI_DEVICE_ID_GLI_9767 0x9767 |
84 | |
85 | /* |
86 | * PCI device class and mask |
87 | */ |
88 | |
89 | #define SYSTEM_SDHCI (PCI_CLASS_SYSTEM_SDHCI << 8) |
90 | #define PCI_CLASS_MASK 0xFFFF00 |
91 | |
92 | /* |
93 | * Macros for PCI device-description |
94 | */ |
95 | |
96 | #define _PCI_VEND(vend) PCI_VENDOR_ID_##vend |
97 | #define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev |
98 | #define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev |
99 | |
100 | #define SDHCI_PCI_DEVICE(vend, dev, cfg) { \ |
101 | .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ |
102 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ |
103 | .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ |
104 | } |
105 | |
106 | #define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \ |
107 | .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \ |
108 | .subvendor = _PCI_VEND(subvend), \ |
109 | .subdevice = _PCI_SUBDEV(subvend, subdev), \ |
110 | .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ |
111 | } |
112 | |
113 | #define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \ |
114 | .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \ |
115 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ |
116 | .class = (cl), .class_mask = (cl_msk), \ |
117 | .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \ |
118 | } |
119 | |
120 | /* |
121 | * PCI registers |
122 | */ |
123 | |
124 | #define PCI_SDHCI_IFPIO 0x00 |
125 | #define PCI_SDHCI_IFDMA 0x01 |
126 | #define PCI_SDHCI_IFVENDOR 0x02 |
127 | |
128 | #define PCI_SLOT_INFO 0x40 /* 8 bits */ |
129 | #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) |
130 | #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 |
131 | |
132 | #define MAX_SLOTS 8 |
133 | |
134 | struct sdhci_pci_chip; |
135 | struct sdhci_pci_slot; |
136 | |
137 | struct sdhci_pci_fixes { |
138 | unsigned int quirks; |
139 | unsigned int quirks2; |
140 | bool allow_runtime_pm; |
141 | bool own_cd_for_runtime_pm; |
142 | |
143 | int (*probe) (struct sdhci_pci_chip *); |
144 | |
145 | int (*probe_slot) (struct sdhci_pci_slot *); |
146 | int (*add_host) (struct sdhci_pci_slot *); |
147 | void (*remove_slot) (struct sdhci_pci_slot *, int); |
148 | |
149 | #ifdef CONFIG_PM_SLEEP |
150 | int (*suspend) (struct sdhci_pci_chip *); |
151 | int (*resume) (struct sdhci_pci_chip *); |
152 | #endif |
153 | #ifdef CONFIG_PM |
154 | int (*runtime_suspend) (struct sdhci_pci_chip *); |
155 | int (*runtime_resume) (struct sdhci_pci_chip *); |
156 | #endif |
157 | |
158 | const struct sdhci_ops *ops; |
159 | size_t priv_size; |
160 | }; |
161 | |
162 | struct sdhci_pci_slot { |
163 | struct sdhci_pci_chip *chip; |
164 | struct sdhci_host *host; |
165 | |
166 | int cd_idx; |
167 | bool cd_override_level; |
168 | |
169 | void (*hw_reset)(struct sdhci_host *host); |
170 | unsigned long private[] ____cacheline_aligned; |
171 | }; |
172 | |
173 | struct sdhci_pci_chip { |
174 | struct pci_dev *pdev; |
175 | |
176 | unsigned int quirks; |
177 | unsigned int quirks2; |
178 | bool allow_runtime_pm; |
179 | bool pm_retune; |
180 | bool rpm_retune; |
181 | const struct sdhci_pci_fixes *fixes; |
182 | |
183 | int num_slots; /* Slots on controller */ |
184 | struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ |
185 | }; |
186 | |
187 | static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot) |
188 | { |
189 | return (void *)slot->private; |
190 | } |
191 | |
192 | #ifdef CONFIG_PM_SLEEP |
193 | int sdhci_pci_resume_host(struct sdhci_pci_chip *chip); |
194 | #endif |
195 | int sdhci_pci_enable_dma(struct sdhci_host *host); |
196 | |
197 | extern const struct sdhci_pci_fixes sdhci_arasan; |
198 | extern const struct sdhci_pci_fixes sdhci_snps; |
199 | extern const struct sdhci_pci_fixes sdhci_o2; |
200 | extern const struct sdhci_pci_fixes sdhci_gl9750; |
201 | extern const struct sdhci_pci_fixes sdhci_gl9755; |
202 | extern const struct sdhci_pci_fixes sdhci_gl9763e; |
203 | extern const struct sdhci_pci_fixes sdhci_gl9767; |
204 | |
205 | #endif /* __SDHCI_PCI_H */ |
206 | |