1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Broadcom Starfighter 2 DSA switch driver
4 *
5 * Copyright (C) 2014, Broadcom Corporation
6 */
7
8#include <linux/list.h>
9#include <linux/module.h>
10#include <linux/netdevice.h>
11#include <linux/interrupt.h>
12#include <linux/platform_device.h>
13#include <linux/phy.h>
14#include <linux/phy_fixed.h>
15#include <linux/phylink.h>
16#include <linux/mii.h>
17#include <linux/clk.h>
18#include <linux/of.h>
19#include <linux/of_irq.h>
20#include <linux/of_address.h>
21#include <linux/of_net.h>
22#include <linux/of_mdio.h>
23#include <net/dsa.h>
24#include <linux/ethtool.h>
25#include <linux/if_bridge.h>
26#include <linux/brcmphy.h>
27#include <linux/etherdevice.h>
28#include <linux/platform_data/b53.h>
29
30#include "bcm_sf2.h"
31#include "bcm_sf2_regs.h"
32#include "b53/b53_priv.h"
33#include "b53/b53_regs.h"
34
35static u16 bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv *priv, int port)
36{
37 switch (priv->type) {
38 case BCM4908_DEVICE_ID:
39 switch (port) {
40 case 7:
41 return REG_RGMII_11_CNTRL;
42 default:
43 break;
44 }
45 break;
46 default:
47 switch (port) {
48 case 0:
49 return REG_RGMII_0_CNTRL;
50 case 1:
51 return REG_RGMII_1_CNTRL;
52 case 2:
53 return REG_RGMII_2_CNTRL;
54 default:
55 break;
56 }
57 }
58
59 WARN_ONCE(1, "Unsupported port %d\n", port);
60
61 /* RO fallback reg */
62 return REG_SWITCH_STATUS;
63}
64
65static u16 bcm_sf2_reg_led_base(struct bcm_sf2_priv *priv, int port)
66{
67 switch (port) {
68 case 0:
69 return REG_LED_0_CNTRL;
70 case 1:
71 return REG_LED_1_CNTRL;
72 case 2:
73 return REG_LED_2_CNTRL;
74 }
75
76 switch (priv->type) {
77 case BCM4908_DEVICE_ID:
78 switch (port) {
79 case 3:
80 return REG_LED_3_CNTRL;
81 case 7:
82 return REG_LED_4_CNTRL;
83 default:
84 break;
85 }
86 break;
87 default:
88 break;
89 }
90
91 WARN_ONCE(1, "Unsupported port %d\n", port);
92
93 /* RO fallback reg */
94 return REG_SWITCH_STATUS;
95}
96
97static u32 bcm_sf2_port_override_offset(struct bcm_sf2_priv *priv, int port)
98{
99 switch (priv->type) {
100 case BCM4908_DEVICE_ID:
101 case BCM7445_DEVICE_ID:
102 return port == 8 ? CORE_STS_OVERRIDE_IMP :
103 CORE_STS_OVERRIDE_GMIIP_PORT(port);
104 case BCM7278_DEVICE_ID:
105 return port == 8 ? CORE_STS_OVERRIDE_IMP2 :
106 CORE_STS_OVERRIDE_GMIIP2_PORT(port);
107 default:
108 WARN_ONCE(1, "Unsupported device: %d\n", priv->type);
109 }
110
111 /* RO fallback register */
112 return REG_SWITCH_STATUS;
113}
114
115/* Return the number of active ports, not counting the IMP (CPU) port */
116static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
117{
118 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
119 unsigned int port, count = 0;
120
121 for (port = 0; port < ds->num_ports; port++) {
122 if (dsa_is_cpu_port(ds, p: port))
123 continue;
124 if (priv->port_sts[port].enabled)
125 count++;
126 }
127
128 return count;
129}
130
131static void bcm_sf2_recalc_clock(struct dsa_switch *ds)
132{
133 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
134 unsigned long new_rate;
135 unsigned int ports_active;
136 /* Frequenty in Mhz */
137 static const unsigned long rate_table[] = {
138 59220000,
139 60820000,
140 62500000,
141 62500000,
142 };
143
144 ports_active = bcm_sf2_num_active_ports(ds);
145 if (ports_active == 0 || !priv->clk_mdiv)
146 return;
147
148 /* If we overflow our table, just use the recommended operational
149 * frequency
150 */
151 if (ports_active > ARRAY_SIZE(rate_table))
152 new_rate = 90000000;
153 else
154 new_rate = rate_table[ports_active - 1];
155 clk_set_rate(clk: priv->clk_mdiv, rate: new_rate);
156}
157
158static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
159{
160 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
161 unsigned int i;
162 u32 reg;
163
164 /* Enable the port memories */
165 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
166 reg &= ~P_TXQ_PSM_VDD(port);
167 core_writel(priv, val: reg, CORE_MEM_PSM_VDD_CTRL);
168
169 /* Enable forwarding */
170 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
171
172 /* Enable IMP port in dumb mode */
173 reg = core_readl(priv, CORE_SWITCH_CTRL);
174 reg |= MII_DUMB_FWDG_EN;
175 core_writel(priv, val: reg, CORE_SWITCH_CTRL);
176
177 /* Configure Traffic Class to QoS mapping, allow each priority to map
178 * to a different queue number
179 */
180 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
181 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
182 reg |= i << (PRT_TO_QID_SHIFT * i);
183 core_writel(priv, val: reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
184
185 b53_brcm_hdr_setup(ds, port);
186
187 if (port == 8) {
188 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
189 reg = core_readl(priv, CORE_IMP_CTL);
190 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
191 reg &= ~(RX_DIS | TX_DIS);
192 core_writel(priv, val: reg, CORE_IMP_CTL);
193 } else {
194 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
195 reg &= ~(RX_DIS | TX_DIS);
196 core_writel(priv, val: reg, CORE_G_PCTL_PORT(port));
197 }
198
199 priv->port_sts[port].enabled = true;
200}
201
202static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
203{
204 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
205 u32 reg;
206
207 reg = reg_readl(priv, off: REG_SPHY_CNTRL);
208 if (enable) {
209 reg |= PHY_RESET;
210 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
211 reg_writel(priv, val: reg, off: REG_SPHY_CNTRL);
212 udelay(21);
213 reg = reg_readl(priv, off: REG_SPHY_CNTRL);
214 reg &= ~PHY_RESET;
215 } else {
216 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
217 reg_writel(priv, val: reg, off: REG_SPHY_CNTRL);
218 mdelay(1);
219 reg |= CK25_DIS;
220 }
221 reg_writel(priv, val: reg, off: REG_SPHY_CNTRL);
222
223 /* Use PHY-driven LED signaling */
224 if (!enable) {
225 u16 led_ctrl = bcm_sf2_reg_led_base(priv, port: 0);
226
227 if (priv->type == BCM7278_DEVICE_ID ||
228 priv->type == BCM7445_DEVICE_ID) {
229 reg = reg_led_readl(priv, off: led_ctrl, reg: 0);
230 reg |= LED_CNTRL_SPDLNK_SRC_SEL;
231 reg_led_writel(priv, val: reg, off: led_ctrl, reg: 0);
232 }
233 }
234}
235
236static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
237 int port)
238{
239 unsigned int off;
240
241 switch (port) {
242 case 7:
243 off = P7_IRQ_OFF;
244 break;
245 case 0:
246 /* Port 0 interrupts are located on the first bank */
247 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
248 return;
249 default:
250 off = P_IRQ_OFF(port);
251 break;
252 }
253
254 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
255}
256
257static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
258 int port)
259{
260 unsigned int off;
261
262 switch (port) {
263 case 7:
264 off = P7_IRQ_OFF;
265 break;
266 case 0:
267 /* Port 0 interrupts are located on the first bank */
268 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
269 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
270 return;
271 default:
272 off = P_IRQ_OFF(port);
273 break;
274 }
275
276 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
277 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
278}
279
280static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
281 struct phy_device *phy)
282{
283 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
284 unsigned int i;
285 u32 reg;
286
287 if (!dsa_is_user_port(ds, p: port))
288 return 0;
289
290 priv->port_sts[port].enabled = true;
291
292 bcm_sf2_recalc_clock(ds);
293
294 /* Clear the memory power down */
295 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
296 reg &= ~P_TXQ_PSM_VDD(port);
297 core_writel(priv, val: reg, CORE_MEM_PSM_VDD_CTRL);
298
299 /* Enable Broadcom tags for that port if requested */
300 if (priv->brcm_tag_mask & BIT(port))
301 b53_brcm_hdr_setup(ds, port);
302
303 /* Configure Traffic Class to QoS mapping, allow each priority to map
304 * to a different queue number
305 */
306 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
307 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
308 reg |= i << (PRT_TO_QID_SHIFT * i);
309 core_writel(priv, val: reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
310
311 /* Re-enable the GPHY and re-apply workarounds */
312 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
313 bcm_sf2_gphy_enable_set(ds, enable: true);
314 if (phy) {
315 /* if phy_stop() has been called before, phy
316 * will be in halted state, and phy_start()
317 * will call resume.
318 *
319 * the resume path does not configure back
320 * autoneg settings, and since we hard reset
321 * the phy manually here, we need to reset the
322 * state machine also.
323 */
324 phy->state = PHY_READY;
325 phy_init_hw(phydev: phy);
326 }
327 }
328
329 /* Enable MoCA port interrupts to get notified */
330 if (port == priv->moca_port)
331 bcm_sf2_port_intr_enable(priv, port);
332
333 /* Set per-queue pause threshold to 32 */
334 core_writel(priv, val: 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
335
336 /* Set ACB threshold to 24 */
337 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
338 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
339 SF2_NUM_EGRESS_QUEUES + i));
340 reg &= ~XOFF_THRESHOLD_MASK;
341 reg |= 24;
342 acb_writel(priv, val: reg, ACB_QUEUE_CFG(port *
343 SF2_NUM_EGRESS_QUEUES + i));
344 }
345
346 return b53_enable_port(ds, port, phy);
347}
348
349static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
350{
351 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
352 u32 reg;
353
354 /* Disable learning while in WoL mode */
355 if (priv->wol_ports_mask & (1 << port)) {
356 reg = core_readl(priv, CORE_DIS_LEARN);
357 reg |= BIT(port);
358 core_writel(priv, val: reg, CORE_DIS_LEARN);
359 return;
360 }
361
362 if (port == priv->moca_port)
363 bcm_sf2_port_intr_disable(priv, port);
364
365 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
366 bcm_sf2_gphy_enable_set(ds, enable: false);
367
368 b53_disable_port(ds, port);
369
370 /* Power down the port memory */
371 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
372 reg |= P_TXQ_PSM_VDD(port);
373 core_writel(priv, val: reg, CORE_MEM_PSM_VDD_CTRL);
374
375 priv->port_sts[port].enabled = false;
376
377 bcm_sf2_recalc_clock(ds);
378}
379
380
381static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
382 int regnum, u16 val)
383{
384 int ret = 0;
385 u32 reg;
386
387 reg = reg_readl(priv, off: REG_SWITCH_CNTRL);
388 reg |= MDIO_MASTER_SEL;
389 reg_writel(priv, val: reg, off: REG_SWITCH_CNTRL);
390
391 /* Page << 8 | offset */
392 reg = 0x70;
393 reg <<= 2;
394 core_writel(priv, val: addr, off: reg);
395
396 /* Page << 8 | offset */
397 reg = 0x80 << 8 | regnum << 1;
398 reg <<= 2;
399
400 if (op)
401 ret = core_readl(priv, off: reg);
402 else
403 core_writel(priv, val, off: reg);
404
405 reg = reg_readl(priv, off: REG_SWITCH_CNTRL);
406 reg &= ~MDIO_MASTER_SEL;
407 reg_writel(priv, val: reg, off: REG_SWITCH_CNTRL);
408
409 return ret & 0xffff;
410}
411
412static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
413{
414 struct bcm_sf2_priv *priv = bus->priv;
415
416 /* Intercept reads from Broadcom pseudo-PHY address, else, send
417 * them to our master MDIO bus controller
418 */
419 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
420 return bcm_sf2_sw_indir_rw(priv, op: 1, addr, regnum, val: 0);
421 else
422 return mdiobus_read_nested(bus: priv->master_mii_bus, addr, regnum);
423}
424
425static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
426 u16 val)
427{
428 struct bcm_sf2_priv *priv = bus->priv;
429
430 /* Intercept writes to the Broadcom pseudo-PHY address, else,
431 * send them to our master MDIO bus controller
432 */
433 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
434 return bcm_sf2_sw_indir_rw(priv, op: 0, addr, regnum, val);
435 else
436 return mdiobus_write_nested(bus: priv->master_mii_bus, addr,
437 regnum, val);
438}
439
440static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
441{
442 struct dsa_switch *ds = dev_id;
443 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
444
445 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
446 ~priv->irq0_mask;
447 intrl2_0_writel(priv, val: priv->irq0_stat, INTRL2_CPU_CLEAR);
448
449 return IRQ_HANDLED;
450}
451
452static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
453{
454 struct dsa_switch *ds = dev_id;
455 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
456
457 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
458 ~priv->irq1_mask;
459 intrl2_1_writel(priv, val: priv->irq1_stat, INTRL2_CPU_CLEAR);
460
461 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
462 priv->port_sts[7].link = true;
463 dsa_port_phylink_mac_change(ds, port: 7, up: true);
464 }
465 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
466 priv->port_sts[7].link = false;
467 dsa_port_phylink_mac_change(ds, port: 7, up: false);
468 }
469
470 return IRQ_HANDLED;
471}
472
473static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
474{
475 unsigned int timeout = 1000;
476 u32 reg;
477 int ret;
478
479 /* The watchdog reset does not work on 7278, we need to hit the
480 * "external" reset line through the reset controller.
481 */
482 if (priv->type == BCM7278_DEVICE_ID) {
483 ret = reset_control_assert(rstc: priv->rcdev);
484 if (ret)
485 return ret;
486
487 return reset_control_deassert(rstc: priv->rcdev);
488 }
489
490 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
491 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
492 core_writel(priv, val: reg, CORE_WATCHDOG_CTRL);
493
494 do {
495 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
496 if (!(reg & SOFTWARE_RESET))
497 break;
498
499 usleep_range(min: 1000, max: 2000);
500 } while (timeout-- > 0);
501
502 if (timeout == 0)
503 return -ETIMEDOUT;
504
505 return 0;
506}
507
508static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv)
509{
510 struct device *dev = priv->dev->ds->dev;
511 int shift;
512 u32 mask;
513 u32 reg;
514 int i;
515
516 mask = BIT(priv->num_crossbar_int_ports) - 1;
517
518 reg = reg_readl(priv, off: REG_CROSSBAR);
519 switch (priv->type) {
520 case BCM4908_DEVICE_ID:
521 shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports;
522 reg &= ~(mask << shift);
523 if (0) /* FIXME */
524 reg |= CROSSBAR_BCM4908_EXT_SERDES << shift;
525 else if (priv->int_phy_mask & BIT(7))
526 reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift;
527 else if (phy_interface_mode_is_rgmii(mode: priv->port_sts[7].mode))
528 reg |= CROSSBAR_BCM4908_EXT_RGMII << shift;
529 else if (WARN(1, "Invalid port mode\n"))
530 return;
531 break;
532 default:
533 return;
534 }
535 reg_writel(priv, val: reg, off: REG_CROSSBAR);
536
537 reg = reg_readl(priv, off: REG_CROSSBAR);
538 for (i = 0; i < priv->num_crossbar_int_ports; i++) {
539 shift = i * priv->num_crossbar_int_ports;
540
541 dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i,
542 (reg >> shift) & mask);
543 }
544}
545
546static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
547{
548 intrl2_0_mask_set(priv, mask: 0xffffffff);
549 intrl2_0_writel(priv, val: 0xffffffff, INTRL2_CPU_CLEAR);
550 intrl2_1_mask_set(priv, mask: 0xffffffff);
551 intrl2_1_writel(priv, val: 0xffffffff, INTRL2_CPU_CLEAR);
552}
553
554static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
555 struct device_node *dn)
556{
557 struct device *dev = priv->dev->ds->dev;
558 struct bcm_sf2_port_status *port_st;
559 struct device_node *port;
560 unsigned int port_num;
561 struct property *prop;
562 int err;
563
564 priv->moca_port = -1;
565
566 for_each_available_child_of_node(dn, port) {
567 if (of_property_read_u32(np: port, propname: "reg", out_value: &port_num))
568 continue;
569
570 if (port_num >= DSA_MAX_PORTS) {
571 dev_err(dev, "Invalid port number %d\n", port_num);
572 continue;
573 }
574
575 port_st = &priv->port_sts[port_num];
576
577 /* Internal PHYs get assigned a specific 'phy-mode' property
578 * value: "internal" to help flag them before MDIO probing
579 * has completed, since they might be turned off at that
580 * time
581 */
582 err = of_get_phy_mode(np: port, interface: &port_st->mode);
583 if (err)
584 continue;
585
586 if (port_st->mode == PHY_INTERFACE_MODE_INTERNAL)
587 priv->int_phy_mask |= 1 << port_num;
588
589 if (port_st->mode == PHY_INTERFACE_MODE_MOCA)
590 priv->moca_port = port_num;
591
592 if (of_property_read_bool(np: port, propname: "brcm,use-bcm-hdr"))
593 priv->brcm_tag_mask |= 1 << port_num;
594
595 /* Ensure that port 5 is not picked up as a DSA CPU port
596 * flavour but a regular port instead. We should be using
597 * devlink to be able to set the port flavour.
598 */
599 if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) {
600 prop = of_find_property(np: port, name: "ethernet", NULL);
601 if (prop)
602 of_remove_property(np: port, prop);
603 }
604 }
605}
606
607static int bcm_sf2_mdio_register(struct dsa_switch *ds)
608{
609 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
610 struct device_node *dn, *child;
611 struct phy_device *phydev;
612 struct property *prop;
613 static int index;
614 int err, reg;
615
616 /* Find our integrated MDIO bus node */
617 dn = of_find_compatible_node(NULL, NULL, compat: "brcm,unimac-mdio");
618 priv->master_mii_bus = of_mdio_find_bus(mdio_np: dn);
619 if (!priv->master_mii_bus) {
620 err = -EPROBE_DEFER;
621 goto err_of_node_put;
622 }
623
624 priv->master_mii_dn = dn;
625
626 priv->user_mii_bus = mdiobus_alloc();
627 if (!priv->user_mii_bus) {
628 err = -ENOMEM;
629 goto err_put_master_mii_bus_dev;
630 }
631
632 priv->user_mii_bus->priv = priv;
633 priv->user_mii_bus->name = "sf2 user mii";
634 priv->user_mii_bus->read = bcm_sf2_sw_mdio_read;
635 priv->user_mii_bus->write = bcm_sf2_sw_mdio_write;
636 snprintf(buf: priv->user_mii_bus->id, MII_BUS_ID_SIZE, fmt: "sf2-%d",
637 index++);
638 priv->user_mii_bus->dev.of_node = dn;
639
640 /* Include the pseudo-PHY address to divert reads towards our
641 * workaround. This is only required for 7445D0, since 7445E0
642 * disconnects the internal switch pseudo-PHY such that we can use the
643 * regular SWITCH_MDIO master controller instead.
644 *
645 * Here we flag the pseudo PHY as needing special treatment and would
646 * otherwise make all other PHY read/writes go to the master MDIO bus
647 * controller that comes with this switch backed by the "mdio-unimac"
648 * driver.
649 */
650 if (of_machine_is_compatible(compat: "brcm,bcm7445d0"))
651 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0);
652 else
653 priv->indir_phy_mask = 0;
654
655 ds->phys_mii_mask = priv->indir_phy_mask;
656 ds->user_mii_bus = priv->user_mii_bus;
657 priv->user_mii_bus->parent = ds->dev->parent;
658 priv->user_mii_bus->phy_mask = ~priv->indir_phy_mask;
659
660 /* We need to make sure that of_phy_connect() will not work by
661 * removing the 'phandle' and 'linux,phandle' properties and
662 * unregister the existing PHY device that was already registered.
663 */
664 for_each_available_child_of_node(dn, child) {
665 if (of_property_read_u32(np: child, propname: "reg", out_value: &reg) ||
666 reg >= PHY_MAX_ADDR)
667 continue;
668
669 if (!(priv->indir_phy_mask & BIT(reg)))
670 continue;
671
672 prop = of_find_property(np: child, name: "phandle", NULL);
673 if (prop)
674 of_remove_property(np: child, prop);
675
676 prop = of_find_property(np: child, name: "linux,phandle", NULL);
677 if (prop)
678 of_remove_property(np: child, prop);
679
680 phydev = of_phy_find_device(phy_np: child);
681 if (phydev)
682 phy_device_remove(phydev);
683 }
684
685 err = mdiobus_register(priv->user_mii_bus);
686 if (err && dn)
687 goto err_free_user_mii_bus;
688
689 return 0;
690
691err_free_user_mii_bus:
692 mdiobus_free(bus: priv->user_mii_bus);
693err_put_master_mii_bus_dev:
694 put_device(dev: &priv->master_mii_bus->dev);
695err_of_node_put:
696 of_node_put(node: dn);
697 return err;
698}
699
700static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
701{
702 mdiobus_unregister(bus: priv->user_mii_bus);
703 mdiobus_free(bus: priv->user_mii_bus);
704 put_device(dev: &priv->master_mii_bus->dev);
705}
706
707static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
708{
709 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
710
711 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
712 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
713 * the REG_PHY_REVISION register layout is.
714 */
715 if (priv->int_phy_mask & BIT(port))
716 return priv->hw_params.gphy_rev;
717 else
718 return PHY_BRCM_AUTO_PWRDWN_ENABLE |
719 PHY_BRCM_DIS_TXCRXC_NOENRGY |
720 PHY_BRCM_IDDQ_SUSPEND;
721}
722
723static void bcm_sf2_sw_get_caps(struct dsa_switch *ds, int port,
724 struct phylink_config *config)
725{
726 unsigned long *interfaces = config->supported_interfaces;
727 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
728
729 if (priv->int_phy_mask & BIT(port)) {
730 __set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces);
731 } else if (priv->moca_port == port) {
732 __set_bit(PHY_INTERFACE_MODE_MOCA, interfaces);
733 } else {
734 __set_bit(PHY_INTERFACE_MODE_MII, interfaces);
735 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces);
736 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
737 phy_interface_set_rgmii(intf: interfaces);
738 }
739
740 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
741 MAC_10 | MAC_100 | MAC_1000;
742}
743
744static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
745 unsigned int mode,
746 const struct phylink_link_state *state)
747{
748 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
749 u32 id_mode_dis = 0, port_mode;
750 u32 reg_rgmii_ctrl;
751 u32 reg;
752
753 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
754 return;
755
756 switch (state->interface) {
757 case PHY_INTERFACE_MODE_RGMII:
758 id_mode_dis = 1;
759 fallthrough;
760 case PHY_INTERFACE_MODE_RGMII_TXID:
761 port_mode = EXT_GPHY;
762 break;
763 case PHY_INTERFACE_MODE_MII:
764 port_mode = EXT_EPHY;
765 break;
766 case PHY_INTERFACE_MODE_REVMII:
767 port_mode = EXT_REVMII;
768 break;
769 default:
770 /* Nothing required for all other PHYs: internal and MoCA */
771 return;
772 }
773
774 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
775
776 /* Clear id_mode_dis bit, and the existing port mode, let
777 * RGMII_MODE_EN bet set by mac_link_{up,down}
778 */
779 reg = reg_readl(priv, off: reg_rgmii_ctrl);
780 reg &= ~ID_MODE_DIS;
781 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
782
783 reg |= port_mode;
784 if (id_mode_dis)
785 reg |= ID_MODE_DIS;
786
787 reg_writel(priv, val: reg, off: reg_rgmii_ctrl);
788}
789
790static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
791 phy_interface_t interface, bool link)
792{
793 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
794 u32 reg_rgmii_ctrl;
795 u32 reg;
796
797 if (!phy_interface_mode_is_rgmii(mode: interface) &&
798 interface != PHY_INTERFACE_MODE_MII &&
799 interface != PHY_INTERFACE_MODE_REVMII)
800 return;
801
802 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
803
804 /* If the link is down, just disable the interface to conserve power */
805 reg = reg_readl(priv, off: reg_rgmii_ctrl);
806 if (link)
807 reg |= RGMII_MODE_EN;
808 else
809 reg &= ~RGMII_MODE_EN;
810 reg_writel(priv, val: reg, off: reg_rgmii_ctrl);
811}
812
813static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
814 unsigned int mode,
815 phy_interface_t interface)
816{
817 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
818 u32 reg, offset;
819
820 if (priv->wol_ports_mask & BIT(port))
821 return;
822
823 offset = bcm_sf2_port_override_offset(priv, port);
824 reg = core_readl(priv, off: offset);
825 reg &= ~LINK_STS;
826 core_writel(priv, val: reg, off: offset);
827
828 bcm_sf2_sw_mac_link_set(ds, port, interface, link: false);
829}
830
831static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
832 unsigned int mode,
833 phy_interface_t interface,
834 struct phy_device *phydev,
835 int speed, int duplex,
836 bool tx_pause, bool rx_pause)
837{
838 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
839 struct ethtool_eee *p = &priv->dev->ports[port].eee;
840 u32 reg_rgmii_ctrl = 0;
841 u32 reg, offset;
842
843 bcm_sf2_sw_mac_link_set(ds, port, interface, link: true);
844
845 offset = bcm_sf2_port_override_offset(priv, port);
846
847 if (phy_interface_mode_is_rgmii(mode: interface) ||
848 interface == PHY_INTERFACE_MODE_MII ||
849 interface == PHY_INTERFACE_MODE_REVMII) {
850 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
851 reg = reg_readl(priv, off: reg_rgmii_ctrl);
852 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
853
854 if (tx_pause)
855 reg |= TX_PAUSE_EN;
856 if (rx_pause)
857 reg |= RX_PAUSE_EN;
858
859 reg_writel(priv, val: reg, off: reg_rgmii_ctrl);
860 }
861
862 reg = LINK_STS;
863 if (port == 8) {
864 if (priv->type == BCM4908_DEVICE_ID)
865 reg |= GMII_SPEED_UP_2G;
866 reg |= MII_SW_OR;
867 } else {
868 reg |= SW_OVERRIDE;
869 }
870
871 switch (speed) {
872 case SPEED_1000:
873 reg |= SPDSTS_1000 << SPEED_SHIFT;
874 break;
875 case SPEED_100:
876 reg |= SPDSTS_100 << SPEED_SHIFT;
877 break;
878 }
879
880 if (duplex == DUPLEX_FULL)
881 reg |= DUPLX_MODE;
882
883 if (tx_pause)
884 reg |= TXFLOW_CNTL;
885 if (rx_pause)
886 reg |= RXFLOW_CNTL;
887
888 core_writel(priv, val: reg, off: offset);
889
890 if (mode == MLO_AN_PHY && phydev)
891 p->eee_enabled = b53_eee_init(ds, port, phy: phydev);
892}
893
894static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
895 struct phylink_link_state *status)
896{
897 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
898
899 status->link = false;
900
901 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
902 * which means that we need to force the link at the port override
903 * level to get the data to flow. We do use what the interrupt handler
904 * did determine before.
905 *
906 * For the other ports, we just force the link status, since this is
907 * a fixed PHY device.
908 */
909 if (port == priv->moca_port) {
910 status->link = priv->port_sts[port].link;
911 /* For MoCA interfaces, also force a link down notification
912 * since some version of the user-space daemon (mocad) use
913 * cmd->autoneg to force the link, which messes up the PHY
914 * state machine and make it go in PHY_FORCING state instead.
915 */
916 if (!status->link)
917 netif_carrier_off(dev: dsa_to_port(ds, p: port)->user);
918 status->duplex = DUPLEX_FULL;
919 } else {
920 status->link = true;
921 }
922}
923
924static void bcm_sf2_enable_acb(struct dsa_switch *ds)
925{
926 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
927 u32 reg;
928
929 /* Enable ACB globally */
930 reg = acb_readl(priv, ACB_CONTROL);
931 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
932 acb_writel(priv, val: reg, ACB_CONTROL);
933 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
934 reg |= ACB_EN | ACB_ALGORITHM;
935 acb_writel(priv, val: reg, ACB_CONTROL);
936}
937
938static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
939{
940 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
941 unsigned int port;
942
943 bcm_sf2_intr_disable(priv);
944
945 /* Disable all ports physically present including the IMP
946 * port, the other ones have already been disabled during
947 * bcm_sf2_sw_setup
948 */
949 for (port = 0; port < ds->num_ports; port++) {
950 if (dsa_is_user_port(ds, p: port) || dsa_is_cpu_port(ds, p: port))
951 bcm_sf2_port_disable(ds, port);
952 }
953
954 if (!priv->wol_ports_mask)
955 clk_disable_unprepare(clk: priv->clk);
956
957 return 0;
958}
959
960static int bcm_sf2_sw_resume(struct dsa_switch *ds)
961{
962 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
963 int ret;
964
965 if (!priv->wol_ports_mask)
966 clk_prepare_enable(clk: priv->clk);
967
968 ret = bcm_sf2_sw_rst(priv);
969 if (ret) {
970 pr_err("%s: failed to software reset switch\n", __func__);
971 return ret;
972 }
973
974 bcm_sf2_crossbar_setup(priv);
975
976 ret = bcm_sf2_cfp_resume(ds);
977 if (ret)
978 return ret;
979
980 if (priv->hw_params.num_gphy == 1)
981 bcm_sf2_gphy_enable_set(ds, enable: true);
982
983 ds->ops->setup(ds);
984
985 return 0;
986}
987
988static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
989 struct ethtool_wolinfo *wol)
990{
991 struct net_device *p = dsa_port_to_conduit(dp: dsa_to_port(ds, p: port));
992 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
993 struct ethtool_wolinfo pwol = { };
994
995 /* Get the parent device WoL settings */
996 if (p->ethtool_ops->get_wol)
997 p->ethtool_ops->get_wol(p, &pwol);
998
999 /* Advertise the parent device supported settings */
1000 wol->supported = pwol.supported;
1001 memset(&wol->sopass, 0, sizeof(wol->sopass));
1002
1003 if (pwol.wolopts & WAKE_MAGICSECURE)
1004 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
1005
1006 if (priv->wol_ports_mask & (1 << port))
1007 wol->wolopts = pwol.wolopts;
1008 else
1009 wol->wolopts = 0;
1010}
1011
1012static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
1013 struct ethtool_wolinfo *wol)
1014{
1015 struct net_device *p = dsa_port_to_conduit(dp: dsa_to_port(ds, p: port));
1016 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
1017 s8 cpu_port = dsa_to_port(ds, p: port)->cpu_dp->index;
1018 struct ethtool_wolinfo pwol = { };
1019
1020 if (p->ethtool_ops->get_wol)
1021 p->ethtool_ops->get_wol(p, &pwol);
1022 if (wol->wolopts & ~pwol.supported)
1023 return -EINVAL;
1024
1025 if (wol->wolopts)
1026 priv->wol_ports_mask |= (1 << port);
1027 else
1028 priv->wol_ports_mask &= ~(1 << port);
1029
1030 /* If we have at least one port enabled, make sure the CPU port
1031 * is also enabled. If the CPU port is the last one enabled, we disable
1032 * it since this configuration does not make sense.
1033 */
1034 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
1035 priv->wol_ports_mask |= (1 << cpu_port);
1036 else
1037 priv->wol_ports_mask &= ~(1 << cpu_port);
1038
1039 return p->ethtool_ops->set_wol(p, wol);
1040}
1041
1042static int bcm_sf2_sw_setup(struct dsa_switch *ds)
1043{
1044 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
1045 unsigned int port;
1046
1047 /* Enable all valid ports and disable those unused */
1048 for (port = 0; port < priv->hw_params.num_ports; port++) {
1049 /* IMP port receives special treatment */
1050 if (dsa_is_user_port(ds, p: port))
1051 bcm_sf2_port_setup(ds, port, NULL);
1052 else if (dsa_is_cpu_port(ds, p: port))
1053 bcm_sf2_imp_setup(ds, port);
1054 else
1055 bcm_sf2_port_disable(ds, port);
1056 }
1057
1058 b53_configure_vlan(ds);
1059 bcm_sf2_enable_acb(ds);
1060
1061 return b53_setup_devlink_resources(ds);
1062}
1063
1064static void bcm_sf2_sw_teardown(struct dsa_switch *ds)
1065{
1066 dsa_devlink_resources_unregister(ds);
1067}
1068
1069/* The SWITCH_CORE register space is managed by b53 but operates on a page +
1070 * register basis so we need to translate that into an address that the
1071 * bus-glue understands.
1072 */
1073#define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
1074
1075static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
1076 u8 *val)
1077{
1078 struct bcm_sf2_priv *priv = dev->priv;
1079
1080 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1081
1082 return 0;
1083}
1084
1085static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
1086 u16 *val)
1087{
1088 struct bcm_sf2_priv *priv = dev->priv;
1089
1090 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1091
1092 return 0;
1093}
1094
1095static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
1096 u32 *val)
1097{
1098 struct bcm_sf2_priv *priv = dev->priv;
1099
1100 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1101
1102 return 0;
1103}
1104
1105static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
1106 u64 *val)
1107{
1108 struct bcm_sf2_priv *priv = dev->priv;
1109
1110 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
1111
1112 return 0;
1113}
1114
1115static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
1116 u8 value)
1117{
1118 struct bcm_sf2_priv *priv = dev->priv;
1119
1120 core_writel(priv, val: value, SF2_PAGE_REG_MKADDR(page, reg));
1121
1122 return 0;
1123}
1124
1125static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
1126 u16 value)
1127{
1128 struct bcm_sf2_priv *priv = dev->priv;
1129
1130 core_writel(priv, val: value, SF2_PAGE_REG_MKADDR(page, reg));
1131
1132 return 0;
1133}
1134
1135static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
1136 u32 value)
1137{
1138 struct bcm_sf2_priv *priv = dev->priv;
1139
1140 core_writel(priv, val: value, SF2_PAGE_REG_MKADDR(page, reg));
1141
1142 return 0;
1143}
1144
1145static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
1146 u64 value)
1147{
1148 struct bcm_sf2_priv *priv = dev->priv;
1149
1150 core_writeq(priv, val: value, SF2_PAGE_REG_MKADDR(page, reg));
1151
1152 return 0;
1153}
1154
1155static const struct b53_io_ops bcm_sf2_io_ops = {
1156 .read8 = bcm_sf2_core_read8,
1157 .read16 = bcm_sf2_core_read16,
1158 .read32 = bcm_sf2_core_read32,
1159 .read48 = bcm_sf2_core_read64,
1160 .read64 = bcm_sf2_core_read64,
1161 .write8 = bcm_sf2_core_write8,
1162 .write16 = bcm_sf2_core_write16,
1163 .write32 = bcm_sf2_core_write32,
1164 .write48 = bcm_sf2_core_write64,
1165 .write64 = bcm_sf2_core_write64,
1166};
1167
1168static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
1169 u32 stringset, uint8_t *data)
1170{
1171 int cnt = b53_get_sset_count(ds, port, sset: stringset);
1172
1173 b53_get_strings(ds, port, stringset, data);
1174 bcm_sf2_cfp_get_strings(ds, port, stringset,
1175 data: data + cnt * ETH_GSTRING_LEN);
1176}
1177
1178static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
1179 uint64_t *data)
1180{
1181 int cnt = b53_get_sset_count(ds, port, sset: ETH_SS_STATS);
1182
1183 b53_get_ethtool_stats(ds, port, data);
1184 bcm_sf2_cfp_get_ethtool_stats(ds, port, data: data + cnt);
1185}
1186
1187static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
1188 int sset)
1189{
1190 int cnt = b53_get_sset_count(ds, port, sset);
1191
1192 if (cnt < 0)
1193 return cnt;
1194
1195 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
1196
1197 return cnt;
1198}
1199
1200static const struct dsa_switch_ops bcm_sf2_ops = {
1201 .get_tag_protocol = b53_get_tag_protocol,
1202 .setup = bcm_sf2_sw_setup,
1203 .teardown = bcm_sf2_sw_teardown,
1204 .get_strings = bcm_sf2_sw_get_strings,
1205 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
1206 .get_sset_count = bcm_sf2_sw_get_sset_count,
1207 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
1208 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
1209 .phylink_get_caps = bcm_sf2_sw_get_caps,
1210 .phylink_mac_config = bcm_sf2_sw_mac_config,
1211 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
1212 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
1213 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
1214 .suspend = bcm_sf2_sw_suspend,
1215 .resume = bcm_sf2_sw_resume,
1216 .get_wol = bcm_sf2_sw_get_wol,
1217 .set_wol = bcm_sf2_sw_set_wol,
1218 .port_enable = bcm_sf2_port_setup,
1219 .port_disable = bcm_sf2_port_disable,
1220 .get_mac_eee = b53_get_mac_eee,
1221 .set_mac_eee = b53_set_mac_eee,
1222 .port_bridge_join = b53_br_join,
1223 .port_bridge_leave = b53_br_leave,
1224 .port_pre_bridge_flags = b53_br_flags_pre,
1225 .port_bridge_flags = b53_br_flags,
1226 .port_stp_state_set = b53_br_set_stp_state,
1227 .port_fast_age = b53_br_fast_age,
1228 .port_vlan_filtering = b53_vlan_filtering,
1229 .port_vlan_add = b53_vlan_add,
1230 .port_vlan_del = b53_vlan_del,
1231 .port_fdb_dump = b53_fdb_dump,
1232 .port_fdb_add = b53_fdb_add,
1233 .port_fdb_del = b53_fdb_del,
1234 .get_rxnfc = bcm_sf2_get_rxnfc,
1235 .set_rxnfc = bcm_sf2_set_rxnfc,
1236 .port_mirror_add = b53_mirror_add,
1237 .port_mirror_del = b53_mirror_del,
1238 .port_mdb_add = b53_mdb_add,
1239 .port_mdb_del = b53_mdb_del,
1240};
1241
1242struct bcm_sf2_of_data {
1243 u32 type;
1244 const u16 *reg_offsets;
1245 unsigned int core_reg_align;
1246 unsigned int num_cfp_rules;
1247 unsigned int num_crossbar_int_ports;
1248};
1249
1250static const u16 bcm_sf2_4908_reg_offsets[] = {
1251 [REG_SWITCH_CNTRL] = 0x00,
1252 [REG_SWITCH_STATUS] = 0x04,
1253 [REG_DIR_DATA_WRITE] = 0x08,
1254 [REG_DIR_DATA_READ] = 0x0c,
1255 [REG_SWITCH_REVISION] = 0x10,
1256 [REG_PHY_REVISION] = 0x14,
1257 [REG_SPHY_CNTRL] = 0x24,
1258 [REG_CROSSBAR] = 0xc8,
1259 [REG_RGMII_11_CNTRL] = 0x014c,
1260 [REG_LED_0_CNTRL] = 0x40,
1261 [REG_LED_1_CNTRL] = 0x4c,
1262 [REG_LED_2_CNTRL] = 0x58,
1263 [REG_LED_3_CNTRL] = 0x64,
1264 [REG_LED_4_CNTRL] = 0x88,
1265 [REG_LED_5_CNTRL] = 0xa0,
1266 [REG_LED_AGGREGATE_CTRL] = 0xb8,
1267
1268};
1269
1270static const struct bcm_sf2_of_data bcm_sf2_4908_data = {
1271 .type = BCM4908_DEVICE_ID,
1272 .core_reg_align = 0,
1273 .reg_offsets = bcm_sf2_4908_reg_offsets,
1274 .num_cfp_rules = 256,
1275 .num_crossbar_int_ports = 2,
1276};
1277
1278/* Register offsets for the SWITCH_REG_* block */
1279static const u16 bcm_sf2_7445_reg_offsets[] = {
1280 [REG_SWITCH_CNTRL] = 0x00,
1281 [REG_SWITCH_STATUS] = 0x04,
1282 [REG_DIR_DATA_WRITE] = 0x08,
1283 [REG_DIR_DATA_READ] = 0x0C,
1284 [REG_SWITCH_REVISION] = 0x18,
1285 [REG_PHY_REVISION] = 0x1C,
1286 [REG_SPHY_CNTRL] = 0x2C,
1287 [REG_RGMII_0_CNTRL] = 0x34,
1288 [REG_RGMII_1_CNTRL] = 0x40,
1289 [REG_RGMII_2_CNTRL] = 0x4c,
1290 [REG_LED_0_CNTRL] = 0x90,
1291 [REG_LED_1_CNTRL] = 0x94,
1292 [REG_LED_2_CNTRL] = 0x98,
1293};
1294
1295static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1296 .type = BCM7445_DEVICE_ID,
1297 .core_reg_align = 0,
1298 .reg_offsets = bcm_sf2_7445_reg_offsets,
1299 .num_cfp_rules = 256,
1300};
1301
1302static const u16 bcm_sf2_7278_reg_offsets[] = {
1303 [REG_SWITCH_CNTRL] = 0x00,
1304 [REG_SWITCH_STATUS] = 0x04,
1305 [REG_DIR_DATA_WRITE] = 0x08,
1306 [REG_DIR_DATA_READ] = 0x0c,
1307 [REG_SWITCH_REVISION] = 0x10,
1308 [REG_PHY_REVISION] = 0x14,
1309 [REG_SPHY_CNTRL] = 0x24,
1310 [REG_RGMII_0_CNTRL] = 0xe0,
1311 [REG_RGMII_1_CNTRL] = 0xec,
1312 [REG_RGMII_2_CNTRL] = 0xf8,
1313 [REG_LED_0_CNTRL] = 0x40,
1314 [REG_LED_1_CNTRL] = 0x4c,
1315 [REG_LED_2_CNTRL] = 0x58,
1316};
1317
1318static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1319 .type = BCM7278_DEVICE_ID,
1320 .core_reg_align = 1,
1321 .reg_offsets = bcm_sf2_7278_reg_offsets,
1322 .num_cfp_rules = 128,
1323};
1324
1325static const struct of_device_id bcm_sf2_of_match[] = {
1326 { .compatible = "brcm,bcm4908-switch",
1327 .data = &bcm_sf2_4908_data
1328 },
1329 { .compatible = "brcm,bcm7445-switch-v4.0",
1330 .data = &bcm_sf2_7445_data
1331 },
1332 { .compatible = "brcm,bcm7278-switch-v4.0",
1333 .data = &bcm_sf2_7278_data
1334 },
1335 { .compatible = "brcm,bcm7278-switch-v4.8",
1336 .data = &bcm_sf2_7278_data
1337 },
1338 { /* sentinel */ },
1339};
1340MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1341
1342static int bcm_sf2_sw_probe(struct platform_device *pdev)
1343{
1344 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1345 struct device_node *dn = pdev->dev.of_node;
1346 const struct of_device_id *of_id = NULL;
1347 const struct bcm_sf2_of_data *data;
1348 struct b53_platform_data *pdata;
1349 struct dsa_switch_ops *ops;
1350 struct device_node *ports;
1351 struct bcm_sf2_priv *priv;
1352 struct b53_device *dev;
1353 struct dsa_switch *ds;
1354 void __iomem **base;
1355 unsigned int i;
1356 u32 reg, rev;
1357 int ret;
1358
1359 priv = devm_kzalloc(dev: &pdev->dev, size: sizeof(*priv), GFP_KERNEL);
1360 if (!priv)
1361 return -ENOMEM;
1362
1363 ops = devm_kzalloc(dev: &pdev->dev, size: sizeof(*ops), GFP_KERNEL);
1364 if (!ops)
1365 return -ENOMEM;
1366
1367 dev = b53_switch_alloc(base: &pdev->dev, ops: &bcm_sf2_io_ops, priv);
1368 if (!dev)
1369 return -ENOMEM;
1370
1371 pdata = devm_kzalloc(dev: &pdev->dev, size: sizeof(*pdata), GFP_KERNEL);
1372 if (!pdata)
1373 return -ENOMEM;
1374
1375 of_id = of_match_node(matches: bcm_sf2_of_match, node: dn);
1376 if (!of_id || !of_id->data)
1377 return -EINVAL;
1378
1379 data = of_id->data;
1380
1381 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1382 priv->type = data->type;
1383 priv->reg_offsets = data->reg_offsets;
1384 priv->core_reg_align = data->core_reg_align;
1385 priv->num_cfp_rules = data->num_cfp_rules;
1386 priv->num_crossbar_int_ports = data->num_crossbar_int_ports;
1387
1388 priv->rcdev = devm_reset_control_get_optional_exclusive(dev: &pdev->dev,
1389 id: "switch");
1390 if (IS_ERR(ptr: priv->rcdev))
1391 return PTR_ERR(ptr: priv->rcdev);
1392
1393 /* Auto-detection using standard registers will not work, so
1394 * provide an indication of what kind of device we are for
1395 * b53_common to work with
1396 */
1397 pdata->chip_id = priv->type;
1398 dev->pdata = pdata;
1399
1400 priv->dev = dev;
1401 ds = dev->ds;
1402 ds->ops = &bcm_sf2_ops;
1403
1404 /* Advertise the 8 egress queues */
1405 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1406
1407 dev_set_drvdata(dev: &pdev->dev, data: priv);
1408
1409 spin_lock_init(&priv->indir_lock);
1410 mutex_init(&priv->cfp.lock);
1411 INIT_LIST_HEAD(list: &priv->cfp.rules_list);
1412
1413 /* CFP rule #0 cannot be used for specific classifications, flag it as
1414 * permanently used
1415 */
1416 set_bit(nr: 0, addr: priv->cfp.used);
1417 set_bit(nr: 0, addr: priv->cfp.unique);
1418
1419 /* Balance of_node_put() done by of_find_node_by_name() */
1420 of_node_get(node: dn);
1421 ports = of_find_node_by_name(from: dn, name: "ports");
1422 if (ports) {
1423 bcm_sf2_identify_ports(priv, dn: ports);
1424 of_node_put(node: ports);
1425 }
1426
1427 priv->irq0 = irq_of_parse_and_map(node: dn, index: 0);
1428 priv->irq1 = irq_of_parse_and_map(node: dn, index: 1);
1429
1430 base = &priv->core;
1431 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1432 *base = devm_platform_ioremap_resource(pdev, index: i);
1433 if (IS_ERR(ptr: *base)) {
1434 pr_err("unable to find register: %s\n", reg_names[i]);
1435 return PTR_ERR(ptr: *base);
1436 }
1437 base++;
1438 }
1439
1440 priv->clk = devm_clk_get_optional(dev: &pdev->dev, id: "sw_switch");
1441 if (IS_ERR(ptr: priv->clk))
1442 return PTR_ERR(ptr: priv->clk);
1443
1444 ret = clk_prepare_enable(clk: priv->clk);
1445 if (ret)
1446 return ret;
1447
1448 priv->clk_mdiv = devm_clk_get_optional(dev: &pdev->dev, id: "sw_switch_mdiv");
1449 if (IS_ERR(ptr: priv->clk_mdiv)) {
1450 ret = PTR_ERR(ptr: priv->clk_mdiv);
1451 goto out_clk;
1452 }
1453
1454 ret = clk_prepare_enable(clk: priv->clk_mdiv);
1455 if (ret)
1456 goto out_clk;
1457
1458 ret = bcm_sf2_sw_rst(priv);
1459 if (ret) {
1460 pr_err("unable to software reset switch: %d\n", ret);
1461 goto out_clk_mdiv;
1462 }
1463
1464 bcm_sf2_crossbar_setup(priv);
1465
1466 bcm_sf2_gphy_enable_set(ds: priv->dev->ds, enable: true);
1467
1468 ret = bcm_sf2_mdio_register(ds);
1469 if (ret) {
1470 pr_err("failed to register MDIO bus\n");
1471 goto out_clk_mdiv;
1472 }
1473
1474 bcm_sf2_gphy_enable_set(ds: priv->dev->ds, enable: false);
1475
1476 ret = bcm_sf2_cfp_rst(priv);
1477 if (ret) {
1478 pr_err("failed to reset CFP\n");
1479 goto out_mdio;
1480 }
1481
1482 /* Disable all interrupts and request them */
1483 bcm_sf2_intr_disable(priv);
1484
1485 ret = devm_request_irq(dev: &pdev->dev, irq: priv->irq0, handler: bcm_sf2_switch_0_isr, irqflags: 0,
1486 devname: "switch_0", dev_id: ds);
1487 if (ret < 0) {
1488 pr_err("failed to request switch_0 IRQ\n");
1489 goto out_mdio;
1490 }
1491
1492 ret = devm_request_irq(dev: &pdev->dev, irq: priv->irq1, handler: bcm_sf2_switch_1_isr, irqflags: 0,
1493 devname: "switch_1", dev_id: ds);
1494 if (ret < 0) {
1495 pr_err("failed to request switch_1 IRQ\n");
1496 goto out_mdio;
1497 }
1498
1499 /* Reset the MIB counters */
1500 reg = core_readl(priv, CORE_GMNCFGCFG);
1501 reg |= RST_MIB_CNT;
1502 core_writel(priv, val: reg, CORE_GMNCFGCFG);
1503 reg &= ~RST_MIB_CNT;
1504 core_writel(priv, val: reg, CORE_GMNCFGCFG);
1505
1506 /* Get the maximum number of ports for this switch */
1507 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1508 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1509 priv->hw_params.num_ports = DSA_MAX_PORTS;
1510
1511 /* Assume a single GPHY setup if we can't read that property */
1512 if (of_property_read_u32(np: dn, propname: "brcm,num-gphy",
1513 out_value: &priv->hw_params.num_gphy))
1514 priv->hw_params.num_gphy = 1;
1515
1516 rev = reg_readl(priv, off: REG_SWITCH_REVISION);
1517 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1518 SWITCH_TOP_REV_MASK;
1519 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1520
1521 rev = reg_readl(priv, off: REG_PHY_REVISION);
1522 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1523
1524 ret = b53_switch_register(dev);
1525 if (ret)
1526 goto out_mdio;
1527
1528 dev_info(&pdev->dev,
1529 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1530 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1531 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1532 priv->irq0, priv->irq1);
1533
1534 return 0;
1535
1536out_mdio:
1537 bcm_sf2_mdio_unregister(priv);
1538out_clk_mdiv:
1539 clk_disable_unprepare(clk: priv->clk_mdiv);
1540out_clk:
1541 clk_disable_unprepare(clk: priv->clk);
1542 return ret;
1543}
1544
1545static void bcm_sf2_sw_remove(struct platform_device *pdev)
1546{
1547 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1548
1549 if (!priv)
1550 return;
1551
1552 priv->wol_ports_mask = 0;
1553 /* Disable interrupts */
1554 bcm_sf2_intr_disable(priv);
1555 dsa_unregister_switch(ds: priv->dev->ds);
1556 bcm_sf2_cfp_exit(ds: priv->dev->ds);
1557 bcm_sf2_mdio_unregister(priv);
1558 clk_disable_unprepare(clk: priv->clk_mdiv);
1559 clk_disable_unprepare(clk: priv->clk);
1560 if (priv->type == BCM7278_DEVICE_ID)
1561 reset_control_assert(rstc: priv->rcdev);
1562}
1563
1564static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1565{
1566 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1567
1568 if (!priv)
1569 return;
1570
1571 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1572 * successful MDIO bus scan to occur. If we did turn off the GPHY
1573 * before (e.g: port_disable), this will also power it back on.
1574 *
1575 * Do not rely on kexec_in_progress, just power the PHY on.
1576 */
1577 if (priv->hw_params.num_gphy == 1)
1578 bcm_sf2_gphy_enable_set(ds: priv->dev->ds, enable: true);
1579
1580 dsa_switch_shutdown(ds: priv->dev->ds);
1581
1582 platform_set_drvdata(pdev, NULL);
1583}
1584
1585#ifdef CONFIG_PM_SLEEP
1586static int bcm_sf2_suspend(struct device *dev)
1587{
1588 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1589
1590 return dsa_switch_suspend(ds: priv->dev->ds);
1591}
1592
1593static int bcm_sf2_resume(struct device *dev)
1594{
1595 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1596
1597 return dsa_switch_resume(ds: priv->dev->ds);
1598}
1599#endif /* CONFIG_PM_SLEEP */
1600
1601static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1602 bcm_sf2_suspend, bcm_sf2_resume);
1603
1604
1605static struct platform_driver bcm_sf2_driver = {
1606 .probe = bcm_sf2_sw_probe,
1607 .remove_new = bcm_sf2_sw_remove,
1608 .shutdown = bcm_sf2_sw_shutdown,
1609 .driver = {
1610 .name = "brcm-sf2",
1611 .of_match_table = bcm_sf2_of_match,
1612 .pm = &bcm_sf2_pm_ops,
1613 },
1614};
1615module_platform_driver(bcm_sf2_driver);
1616
1617MODULE_AUTHOR("Broadcom Corporation");
1618MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1619MODULE_LICENSE("GPL");
1620MODULE_ALIAS("platform:brcm-sf2");
1621

source code of linux/drivers/net/dsa/bcm_sf2.c