| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * drivers/net/dsa/mv88e6060.h - Marvell 88e6060 switch chip support |
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| 4 | * Copyright (c) 2015 Neil Armstrong |
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| 5 | * |
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| 6 | * Based on mv88e6xxx.h |
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| 7 | * Copyright (c) 2008 Marvell Semiconductor |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef __MV88E6060_H |
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| 11 | #define __MV88E6060_H |
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| 12 | |
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| 13 | #define MV88E6060_PORTS 6 |
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| 14 | |
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| 15 | #define REG_PORT(p) (0x8 + (p)) |
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| 16 | #define PORT_STATUS 0x00 |
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| 17 | #define PORT_STATUS_PAUSE_EN BIT(15) |
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| 18 | #define PORT_STATUS_MY_PAUSE BIT(14) |
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| 19 | #define PORT_STATUS_FC (PORT_STATUS_MY_PAUSE | PORT_STATUS_PAUSE_EN) |
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| 20 | #define PORT_STATUS_RESOLVED BIT(13) |
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| 21 | #define PORT_STATUS_LINK BIT(12) |
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| 22 | #define PORT_STATUS_PORTMODE BIT(11) |
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| 23 | #define PORT_STATUS_PHYMODE BIT(10) |
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| 24 | #define PORT_STATUS_DUPLEX BIT(9) |
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| 25 | #define PORT_STATUS_SPEED BIT(8) |
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| 26 | #define PORT_SWITCH_ID 0x03 |
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| 27 | #define PORT_SWITCH_ID_6060 0x0600 |
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| 28 | #define PORT_SWITCH_ID_6060_MASK 0xfff0 |
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| 29 | #define PORT_SWITCH_ID_6060_R1 0x0601 |
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| 30 | #define PORT_SWITCH_ID_6060_R2 0x0602 |
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| 31 | #define PORT_CONTROL 0x04 |
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| 32 | #define PORT_CONTROL_FORCE_FLOW_CTRL BIT(15) |
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| 33 | #define PORT_CONTROL_TRAILER BIT(14) |
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| 34 | #define BIT(11) |
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| 35 | #define PORT_CONTROL_INGRESS_MODE BIT(8) |
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| 36 | #define PORT_CONTROL_VLAN_TUNNEL BIT(7) |
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| 37 | #define PORT_CONTROL_STATE_MASK 0x03 |
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| 38 | #define PORT_CONTROL_STATE_DISABLED 0x00 |
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| 39 | #define PORT_CONTROL_STATE_BLOCKING 0x01 |
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| 40 | #define PORT_CONTROL_STATE_LEARNING 0x02 |
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| 41 | #define PORT_CONTROL_STATE_FORWARDING 0x03 |
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| 42 | #define PORT_VLAN_MAP 0x06 |
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| 43 | #define PORT_VLAN_MAP_DBNUM_SHIFT 12 |
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| 44 | #define PORT_VLAN_MAP_TABLE_MASK 0x1f |
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| 45 | #define PORT_ASSOC_VECTOR 0x0b |
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| 46 | #define PORT_ASSOC_VECTOR_MONITOR BIT(15) |
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| 47 | #define PORT_ASSOC_VECTOR_PAV_MASK 0x1f |
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| 48 | #define PORT_RX_CNTR 0x10 |
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| 49 | #define PORT_TX_CNTR 0x11 |
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| 50 | |
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| 51 | #define REG_GLOBAL 0x0f |
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| 52 | #define GLOBAL_STATUS 0x00 |
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| 53 | #define GLOBAL_STATUS_SW_MODE_MASK (0x3 << 12) |
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| 54 | #define GLOBAL_STATUS_SW_MODE_0 (0x0 << 12) |
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| 55 | #define GLOBAL_STATUS_SW_MODE_1 (0x1 << 12) |
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| 56 | #define GLOBAL_STATUS_SW_MODE_2 (0x2 << 12) |
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| 57 | #define GLOBAL_STATUS_SW_MODE_3 (0x3 << 12) |
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| 58 | #define GLOBAL_STATUS_INIT_READY BIT(11) |
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| 59 | #define GLOBAL_STATUS_ATU_FULL BIT(3) |
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| 60 | #define GLOBAL_STATUS_ATU_DONE BIT(2) |
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| 61 | #define GLOBAL_STATUS_PHY_INT BIT(1) |
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| 62 | #define GLOBAL_STATUS_EEINT BIT(0) |
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| 63 | #define GLOBAL_MAC_01 0x01 |
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| 64 | #define GLOBAL_MAC_01_DIFF_ADDR BIT(8) |
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| 65 | #define GLOBAL_MAC_23 0x02 |
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| 66 | #define GLOBAL_MAC_45 0x03 |
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| 67 | #define GLOBAL_CONTROL 0x04 |
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| 68 | #define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) |
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| 69 | #define GLOBAL_CONTROL_MAX_FRAME_1536 BIT(10) |
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| 70 | #define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) |
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| 71 | #define GLOBAL_CONTROL_CTRMODE BIT(8) |
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| 72 | #define GLOBAL_CONTROL_ATU_FULL_EN BIT(3) |
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| 73 | #define GLOBAL_CONTROL_ATU_DONE_EN BIT(2) |
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| 74 | #define GLOBAL_CONTROL_PHYINT_EN BIT(1) |
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| 75 | #define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0) |
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| 76 | #define GLOBAL_ATU_CONTROL 0x0a |
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| 77 | #define GLOBAL_ATU_CONTROL_SWRESET BIT(15) |
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| 78 | #define GLOBAL_ATU_CONTROL_LEARNDIS BIT(14) |
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| 79 | #define GLOBAL_ATU_CONTROL_ATUSIZE_256 (0x0 << 12) |
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| 80 | #define GLOBAL_ATU_CONTROL_ATUSIZE_512 (0x1 << 12) |
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| 81 | #define GLOBAL_ATU_CONTROL_ATUSIZE_1024 (0x2 << 12) |
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| 82 | #define GLOBAL_ATU_CONTROL_ATE_AGE_SHIFT 4 |
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| 83 | #define GLOBAL_ATU_CONTROL_ATE_AGE_MASK (0xff << 4) |
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| 84 | #define GLOBAL_ATU_CONTROL_ATE_AGE_5MIN (0x13 << 4) |
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| 85 | #define GLOBAL_ATU_OP 0x0b |
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| 86 | #define GLOBAL_ATU_OP_BUSY BIT(15) |
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| 87 | #define GLOBAL_ATU_OP_NOP (0 << 12) |
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| 88 | #define GLOBAL_ATU_OP_FLUSH_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY) |
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| 89 | #define GLOBAL_ATU_OP_FLUSH_UNLOCKED ((2 << 12) | GLOBAL_ATU_OP_BUSY) |
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| 90 | #define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY) |
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| 91 | #define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY) |
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| 92 | #define GLOBAL_ATU_OP_FLUSH_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY) |
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| 93 | #define GLOBAL_ATU_OP_FLUSH_UNLOCKED_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY) |
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| 94 | #define GLOBAL_ATU_DATA 0x0c |
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| 95 | #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3f0 |
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| 96 | #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4 |
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| 97 | #define GLOBAL_ATU_DATA_STATE_MASK 0x0f |
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| 98 | #define GLOBAL_ATU_DATA_STATE_UNUSED 0x00 |
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| 99 | #define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e |
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| 100 | #define GLOBAL_ATU_DATA_STATE_UC_LOCKED 0x0f |
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| 101 | #define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07 |
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| 102 | #define GLOBAL_ATU_DATA_STATE_MC_LOCKED 0x0e |
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| 103 | #define GLOBAL_ATU_MAC_01 0x0d |
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| 104 | #define GLOBAL_ATU_MAC_23 0x0e |
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| 105 | #define GLOBAL_ATU_MAC_45 0x0f |
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| 106 | |
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| 107 | struct mv88e6060_priv { |
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| 108 | /* MDIO bus and address on bus to use. When in single chip |
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| 109 | * mode, address is 0, and the switch uses multiple addresses |
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| 110 | * on the bus. When in multi-chip mode, the switch uses a |
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| 111 | * single address which contains two registers used for |
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| 112 | * indirect access to more registers. |
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| 113 | */ |
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| 114 | struct mii_bus *bus; |
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| 115 | int sw_addr; |
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| 116 | struct dsa_switch *ds; |
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| 117 | }; |
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| 118 | |
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| 119 | #endif |
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| 120 | |
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