1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * 7990.h -- LANCE ethernet IC generic routines. |
4 | * This is an attempt to separate out the bits of various ethernet |
5 | * drivers that are common because they all use the AMD 7990 LANCE |
6 | * (Local Area Network Controller for Ethernet) chip. |
7 | * |
8 | * Copyright (C) 05/1998 Peter Maydell <pmaydell@chiark.greenend.org.uk> |
9 | * |
10 | * Most of this stuff was obtained by looking at other LANCE drivers, |
11 | * in particular a2065.[ch]. The AMD C-LANCE datasheet was also helpful. |
12 | */ |
13 | |
14 | #ifndef _7990_H |
15 | #define _7990_H |
16 | |
17 | /* The lance only has two register locations. We communicate mostly via memory. */ |
18 | #define LANCE_RDP 0 /* Register Data Port */ |
19 | #define LANCE_RAP 2 /* Register Address Port */ |
20 | |
21 | /* Transmit/receive ring definitions. |
22 | * We allow the specific drivers to override these defaults if they want to. |
23 | * NB: according to lance.c, increasing the number of buffers is a waste |
24 | * of space and reduces the chance that an upper layer will be able to |
25 | * reorder queued Tx packets based on priority. [Clearly there is a minimum |
26 | * limit too: too small and we drop rx packets and can't tx at full speed.] |
27 | * 4+4 seems to be the usual setting; the atarilance driver uses 3 and 5. |
28 | */ |
29 | |
30 | /* Blast! This won't work. The problem is that we can't specify a default |
31 | * setting because that would cause the lance_init_block struct to be |
32 | * too long (and overflow the RAM on shared-memory cards like the HP LANCE. |
33 | */ |
34 | #ifndef LANCE_LOG_TX_BUFFERS |
35 | #define LANCE_LOG_TX_BUFFERS 1 |
36 | #define LANCE_LOG_RX_BUFFERS 3 |
37 | #endif |
38 | |
39 | #define TX_RING_SIZE (1 << LANCE_LOG_TX_BUFFERS) |
40 | #define RX_RING_SIZE (1 << LANCE_LOG_RX_BUFFERS) |
41 | #define TX_RING_MOD_MASK (TX_RING_SIZE - 1) |
42 | #define RX_RING_MOD_MASK (RX_RING_SIZE - 1) |
43 | #define TX_RING_LEN_BITS ((LANCE_LOG_TX_BUFFERS) << 29) |
44 | #define RX_RING_LEN_BITS ((LANCE_LOG_RX_BUFFERS) << 29) |
45 | #define PKT_BUFF_SIZE (1544) |
46 | #define RX_BUFF_SIZE PKT_BUFF_SIZE |
47 | #define TX_BUFF_SIZE PKT_BUFF_SIZE |
48 | |
49 | /* Each receive buffer is described by a receive message descriptor (RMD) */ |
50 | struct lance_rx_desc { |
51 | volatile unsigned short rmd0; /* low address of packet */ |
52 | volatile unsigned char rmd1_bits; /* descriptor bits */ |
53 | volatile unsigned char rmd1_hadr; /* high address of packet */ |
54 | volatile short length; /* This length is 2s complement (negative)! |
55 | * Buffer length */ |
56 | volatile unsigned short mblength; /* Actual number of bytes received */ |
57 | }; |
58 | |
59 | /* Ditto for TMD: */ |
60 | struct lance_tx_desc { |
61 | volatile unsigned short tmd0; /* low address of packet */ |
62 | volatile unsigned char tmd1_bits; /* descriptor bits */ |
63 | volatile unsigned char tmd1_hadr; /* high address of packet */ |
64 | volatile short length; /* Length is 2s complement (negative)! */ |
65 | volatile unsigned short misc; |
66 | }; |
67 | |
68 | /* There are three memory structures accessed by the LANCE: |
69 | * the initialization block, the receive and transmit descriptor rings, |
70 | * and the data buffers themselves. In fact we might as well put the |
71 | * init block,the Tx and Rx rings and the buffers together in memory: |
72 | */ |
73 | struct lance_init_block { |
74 | volatile unsigned short mode; /* Pre-set mode (reg. 15) */ |
75 | volatile unsigned char phys_addr[6]; /* Physical ethernet address */ |
76 | volatile unsigned filter[2]; /* Multicast filter (64 bits) */ |
77 | |
78 | /* Receive and transmit ring base, along with extra bits. */ |
79 | volatile unsigned short rx_ptr; /* receive descriptor addr */ |
80 | volatile unsigned short rx_len; /* receive len and high addr */ |
81 | volatile unsigned short tx_ptr; /* transmit descriptor addr */ |
82 | volatile unsigned short tx_len; /* transmit len and high addr */ |
83 | |
84 | /* The Tx and Rx ring entries must be aligned on 8-byte boundaries. |
85 | * This will be true if this whole struct is 8-byte aligned. |
86 | */ |
87 | volatile struct lance_tx_desc btx_ring[TX_RING_SIZE]; |
88 | volatile struct lance_rx_desc brx_ring[RX_RING_SIZE]; |
89 | |
90 | volatile char tx_buf[TX_RING_SIZE][TX_BUFF_SIZE]; |
91 | volatile char rx_buf[RX_RING_SIZE][RX_BUFF_SIZE]; |
92 | /* we use this just to make the struct big enough that we can move its startaddr |
93 | * in order to force alignment to an eight byte boundary. |
94 | */ |
95 | }; |
96 | |
97 | /* This is where we keep all the stuff the driver needs to know about. |
98 | * I'm definitely unhappy about the mechanism for allowing specific |
99 | * drivers to add things... |
100 | */ |
101 | struct lance_private { |
102 | const char *name; |
103 | unsigned long base; |
104 | volatile struct lance_init_block *init_block; /* CPU address of RAM */ |
105 | volatile struct lance_init_block *lance_init_block; /* LANCE address of RAM */ |
106 | |
107 | int rx_new, tx_new; |
108 | int rx_old, tx_old; |
109 | |
110 | int lance_log_rx_bufs, lance_log_tx_bufs; |
111 | int rx_ring_mod_mask, tx_ring_mod_mask; |
112 | |
113 | int tpe; /* TPE is selected */ |
114 | int auto_select; /* cable-selection is by carrier */ |
115 | unsigned short busmaster_regval; |
116 | |
117 | unsigned int irq; /* IRQ to register */ |
118 | |
119 | /* This is because the HP LANCE is disgusting and you have to check |
120 | * a DIO-specific register every time you read/write the LANCE regs :-< |
121 | * [could we get away with making these some sort of macro?] |
122 | */ |
123 | void (*writerap)(void *, unsigned short); |
124 | void (*writerdp)(void *, unsigned short); |
125 | unsigned short (*readrdp)(void *); |
126 | spinlock_t devlock; |
127 | char tx_full; |
128 | }; |
129 | |
130 | /* |
131 | * Am7990 Control and Status Registers |
132 | */ |
133 | #define LE_CSR0 0x0000 /* LANCE Controller Status */ |
134 | #define LE_CSR1 0x0001 /* IADR[15:0] (bit0==0 ie word aligned) */ |
135 | #define LE_CSR2 0x0002 /* IADR[23:16] (high bits reserved) */ |
136 | #define LE_CSR3 0x0003 /* Misc */ |
137 | |
138 | /* |
139 | * Bit definitions for CSR0 (LANCE Controller Status) |
140 | */ |
141 | #define LE_C0_ERR 0x8000 /* Error = BABL | CERR | MISS | MERR */ |
142 | #define LE_C0_BABL 0x4000 /* Babble: Transmitted too many bits */ |
143 | #define LE_C0_CERR 0x2000 /* No Heartbeat (10BASE-T) */ |
144 | #define LE_C0_MISS 0x1000 /* Missed Frame (no rx buffer to put it in) */ |
145 | #define LE_C0_MERR 0x0800 /* Memory Error */ |
146 | #define LE_C0_RINT 0x0400 /* Receive Interrupt */ |
147 | #define LE_C0_TINT 0x0200 /* Transmit Interrupt */ |
148 | #define LE_C0_IDON 0x0100 /* Initialization Done */ |
149 | #define LE_C0_INTR 0x0080 /* Interrupt Flag |
150 | = BABL | MISS | MERR | RINT | TINT | IDON */ |
151 | #define LE_C0_INEA 0x0040 /* Interrupt Enable */ |
152 | #define LE_C0_RXON 0x0020 /* Receive On */ |
153 | #define LE_C0_TXON 0x0010 /* Transmit On */ |
154 | #define LE_C0_TDMD 0x0008 /* Transmit Demand */ |
155 | #define LE_C0_STOP 0x0004 /* Stop */ |
156 | #define LE_C0_STRT 0x0002 /* Start */ |
157 | #define LE_C0_INIT 0x0001 /* Initialize */ |
158 | |
159 | |
160 | /* |
161 | * Bit definitions for CSR3 |
162 | */ |
163 | #define LE_C3_BSWP 0x0004 /* Byte Swap (on for big endian byte order) */ |
164 | #define LE_C3_ACON 0x0002 /* ALE Control (on for active low ALE) */ |
165 | #define LE_C3_BCON 0x0001 /* Byte Control */ |
166 | |
167 | |
168 | /* |
169 | * Mode Flags |
170 | */ |
171 | #define LE_MO_PROM 0x8000 /* Promiscuous Mode */ |
172 | /* these next ones 0x4000 -- 0x0080 are not available on the LANCE 7990, |
173 | * but they are in NetBSD's am7990.h, presumably for backwards-compatible chips |
174 | */ |
175 | #define LE_MO_DRCVBC 0x4000 /* disable receive broadcast */ |
176 | #define LE_MO_DRCVPA 0x2000 /* disable physical address detection */ |
177 | #define LE_MO_DLNKTST 0x1000 /* disable link status */ |
178 | #define LE_MO_DAPC 0x0800 /* disable automatic polarity correction */ |
179 | #define LE_MO_MENDECL 0x0400 /* MENDEC loopback mode */ |
180 | #define LE_MO_LRTTSEL 0x0200 /* lower RX threshold / TX mode selection */ |
181 | #define LE_MO_PSEL1 0x0100 /* port selection bit1 */ |
182 | #define LE_MO_PSEL0 0x0080 /* port selection bit0 */ |
183 | /* and this one is from the C-LANCE data sheet... */ |
184 | #define LE_MO_EMBA 0x0080 /* Enable Modified Backoff Algorithm |
185 | (C-LANCE, not original LANCE) */ |
186 | #define LE_MO_INTL 0x0040 /* Internal Loopback */ |
187 | #define LE_MO_DRTY 0x0020 /* Disable Retry */ |
188 | #define LE_MO_FCOLL 0x0010 /* Force Collision */ |
189 | #define LE_MO_DXMTFCS 0x0008 /* Disable Transmit CRC */ |
190 | #define LE_MO_LOOP 0x0004 /* Loopback Enable */ |
191 | #define LE_MO_DTX 0x0002 /* Disable Transmitter */ |
192 | #define LE_MO_DRX 0x0001 /* Disable Receiver */ |
193 | |
194 | |
195 | /* |
196 | * Receive Flags |
197 | */ |
198 | #define LE_R1_OWN 0x80 /* LANCE owns the descriptor */ |
199 | #define LE_R1_ERR 0x40 /* Error */ |
200 | #define LE_R1_FRA 0x20 /* Framing Error */ |
201 | #define LE_R1_OFL 0x10 /* Overflow Error */ |
202 | #define LE_R1_CRC 0x08 /* CRC Error */ |
203 | #define LE_R1_BUF 0x04 /* Buffer Error */ |
204 | #define LE_R1_SOP 0x02 /* Start of Packet */ |
205 | #define LE_R1_EOP 0x01 /* End of Packet */ |
206 | #define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */ |
207 | |
208 | |
209 | /* |
210 | * Transmit Flags |
211 | */ |
212 | #define LE_T1_OWN 0x80 /* LANCE owns the descriptor */ |
213 | #define LE_T1_ERR 0x40 /* Error */ |
214 | #define LE_T1_RES 0x20 /* Reserved, LANCE writes this with a zero */ |
215 | #define LE_T1_EMORE 0x10 /* More than one retry needed */ |
216 | #define LE_T1_EONE 0x08 /* One retry needed */ |
217 | #define LE_T1_EDEF 0x04 /* Deferred */ |
218 | #define LE_T1_SOP 0x02 /* Start of Packet */ |
219 | #define LE_T1_EOP 0x01 /* End of Packet */ |
220 | #define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */ |
221 | |
222 | /* |
223 | * Error Flags |
224 | */ |
225 | #define LE_T3_BUF 0x8000 /* Buffer Error */ |
226 | #define LE_T3_UFL 0x4000 /* Underflow Error */ |
227 | #define LE_T3_LCOL 0x1000 /* Late Collision */ |
228 | #define LE_T3_CLOS 0x0800 /* Loss of Carrier */ |
229 | #define LE_T3_RTY 0x0400 /* Retry Error */ |
230 | #define LE_T3_TDR 0x03ff /* Time Domain Reflectometry */ |
231 | |
232 | /* Miscellaneous useful macros */ |
233 | |
234 | #define TX_BUFFS_AVAIL ((lp->tx_old <= lp->tx_new) ? \ |
235 | lp->tx_old + lp->tx_ring_mod_mask - lp->tx_new : \ |
236 | lp->tx_old - lp->tx_new - 1) |
237 | |
238 | /* The LANCE only uses 24 bit addresses. This does the obvious thing. */ |
239 | #define LANCE_ADDR(x) ((int)(x) & ~0xff000000) |
240 | |
241 | /* Now the prototypes we export */ |
242 | int lance_open(struct net_device *dev); |
243 | int lance_close(struct net_device *dev); |
244 | netdev_tx_t lance_start_xmit(struct sk_buff *skb, struct net_device *dev); |
245 | void lance_set_multicast(struct net_device *dev); |
246 | void lance_tx_timeout(struct net_device *dev, unsigned int txqueue); |
247 | #ifdef CONFIG_NET_POLL_CONTROLLER |
248 | void lance_poll(struct net_device *dev); |
249 | #endif |
250 | |
251 | #endif /* ndef _7990_H */ |
252 | |