1 | /* |
2 | * Amiga Linux/68k A2065 Ethernet Driver |
3 | * |
4 | * (C) Copyright 1995 by Geert Uytterhoeven <geert@linux-m68k.org> |
5 | * |
6 | * --------------------------------------------------------------------------- |
7 | * |
8 | * This program is based on |
9 | * |
10 | * ariadne.?: Amiga Linux/68k Ariadne Ethernet Driver |
11 | * (C) Copyright 1995 by Geert Uytterhoeven, |
12 | * Peter De Schrijver |
13 | * |
14 | * lance.c: An AMD LANCE ethernet driver for linux. |
15 | * Written 1993-94 by Donald Becker. |
16 | * |
17 | * Am79C960: PCnet(tm)-ISA Single-Chip Ethernet Controller |
18 | * Advanced Micro Devices |
19 | * Publication #16907, Rev. B, Amendment/0, May 1994 |
20 | * |
21 | * --------------------------------------------------------------------------- |
22 | * |
23 | * This file is subject to the terms and conditions of the GNU General Public |
24 | * License. See the file COPYING in the main directory of the Linux |
25 | * distribution for more details. |
26 | * |
27 | * --------------------------------------------------------------------------- |
28 | * |
29 | * The A2065 is a Zorro-II board made by Commodore/Ameristar. It contains: |
30 | * |
31 | * - an Am7990 Local Area Network Controller for Ethernet (LANCE) with |
32 | * both 10BASE-2 (thin coax) and AUI (DB-15) connectors |
33 | */ |
34 | |
35 | |
36 | /* |
37 | * Am7990 Local Area Network Controller for Ethernet (LANCE) |
38 | */ |
39 | |
40 | struct lance_regs { |
41 | unsigned short rdp; /* Register Data Port */ |
42 | unsigned short rap; /* Register Address Port */ |
43 | }; |
44 | |
45 | |
46 | /* |
47 | * Am7990 Control and Status Registers |
48 | */ |
49 | |
50 | #define LE_CSR0 0x0000 /* LANCE Controller Status */ |
51 | #define LE_CSR1 0x0001 /* IADR[15:0] */ |
52 | #define LE_CSR2 0x0002 /* IADR[23:16] */ |
53 | #define LE_CSR3 0x0003 /* Misc */ |
54 | |
55 | |
56 | /* |
57 | * Bit definitions for CSR0 (LANCE Controller Status) |
58 | */ |
59 | |
60 | #define LE_C0_ERR 0x8000 /* Error */ |
61 | #define LE_C0_BABL 0x4000 /* Babble: Transmitted too many bits */ |
62 | #define LE_C0_CERR 0x2000 /* No Heartbeat (10BASE-T) */ |
63 | #define LE_C0_MISS 0x1000 /* Missed Frame */ |
64 | #define LE_C0_MERR 0x0800 /* Memory Error */ |
65 | #define LE_C0_RINT 0x0400 /* Receive Interrupt */ |
66 | #define LE_C0_TINT 0x0200 /* Transmit Interrupt */ |
67 | #define LE_C0_IDON 0x0100 /* Initialization Done */ |
68 | #define LE_C0_INTR 0x0080 /* Interrupt Flag */ |
69 | #define LE_C0_INEA 0x0040 /* Interrupt Enable */ |
70 | #define LE_C0_RXON 0x0020 /* Receive On */ |
71 | #define LE_C0_TXON 0x0010 /* Transmit On */ |
72 | #define LE_C0_TDMD 0x0008 /* Transmit Demand */ |
73 | #define LE_C0_STOP 0x0004 /* Stop */ |
74 | #define LE_C0_STRT 0x0002 /* Start */ |
75 | #define LE_C0_INIT 0x0001 /* Initialize */ |
76 | |
77 | |
78 | /* |
79 | * Bit definitions for CSR3 |
80 | */ |
81 | |
82 | #define LE_C3_BSWP 0x0004 /* Byte Swap |
83 | (on for big endian byte order) */ |
84 | #define LE_C3_ACON 0x0002 /* ALE Control |
85 | (on for active low ALE) */ |
86 | #define LE_C3_BCON 0x0001 /* Byte Control */ |
87 | |
88 | |
89 | /* |
90 | * Mode Flags |
91 | */ |
92 | |
93 | #define LE_MO_PROM 0x8000 /* Promiscuous Mode */ |
94 | #define LE_MO_INTL 0x0040 /* Internal Loopback */ |
95 | #define LE_MO_DRTY 0x0020 /* Disable Retry */ |
96 | #define LE_MO_FCOLL 0x0010 /* Force Collision */ |
97 | #define LE_MO_DXMTFCS 0x0008 /* Disable Transmit CRC */ |
98 | #define LE_MO_LOOP 0x0004 /* Loopback Enable */ |
99 | #define LE_MO_DTX 0x0002 /* Disable Transmitter */ |
100 | #define LE_MO_DRX 0x0001 /* Disable Receiver */ |
101 | |
102 | |
103 | struct lance_rx_desc { |
104 | unsigned short rmd0; /* low address of packet */ |
105 | unsigned char rmd1_bits; /* descriptor bits */ |
106 | unsigned char rmd1_hadr; /* high address of packet */ |
107 | short length; /* This length is 2s complement (negative)! |
108 | * Buffer length |
109 | */ |
110 | unsigned short mblength; /* Aactual number of bytes received */ |
111 | }; |
112 | |
113 | struct lance_tx_desc { |
114 | unsigned short tmd0; /* low address of packet */ |
115 | unsigned char tmd1_bits; /* descriptor bits */ |
116 | unsigned char tmd1_hadr; /* high address of packet */ |
117 | short length; /* Length is 2s complement (negative)! */ |
118 | unsigned short misc; |
119 | }; |
120 | |
121 | |
122 | /* |
123 | * Receive Flags |
124 | */ |
125 | |
126 | #define LE_R1_OWN 0x80 /* LANCE owns the descriptor */ |
127 | #define LE_R1_ERR 0x40 /* Error */ |
128 | #define LE_R1_FRA 0x20 /* Framing Error */ |
129 | #define LE_R1_OFL 0x10 /* Overflow Error */ |
130 | #define LE_R1_CRC 0x08 /* CRC Error */ |
131 | #define LE_R1_BUF 0x04 /* Buffer Error */ |
132 | #define LE_R1_SOP 0x02 /* Start of Packet */ |
133 | #define LE_R1_EOP 0x01 /* End of Packet */ |
134 | #define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */ |
135 | |
136 | |
137 | /* |
138 | * Transmit Flags |
139 | */ |
140 | |
141 | #define LE_T1_OWN 0x80 /* LANCE owns the descriptor */ |
142 | #define LE_T1_ERR 0x40 /* Error */ |
143 | #define LE_T1_RES 0x20 /* Reserved, |
144 | LANCE writes this with a zero */ |
145 | #define LE_T1_EMORE 0x10 /* More than one retry needed */ |
146 | #define LE_T1_EONE 0x08 /* One retry needed */ |
147 | #define LE_T1_EDEF 0x04 /* Deferred */ |
148 | #define LE_T1_SOP 0x02 /* Start of Packet */ |
149 | #define LE_T1_EOP 0x01 /* End of Packet */ |
150 | #define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */ |
151 | |
152 | |
153 | /* |
154 | * Error Flags |
155 | */ |
156 | |
157 | #define LE_T3_BUF 0x8000 /* Buffer Error */ |
158 | #define LE_T3_UFL 0x4000 /* Underflow Error */ |
159 | #define LE_T3_LCOL 0x1000 /* Late Collision */ |
160 | #define LE_T3_CLOS 0x0800 /* Loss of Carrier */ |
161 | #define LE_T3_RTY 0x0400 /* Retry Error */ |
162 | #define LE_T3_TDR 0x03ff /* Time Domain Reflectometry */ |
163 | |
164 | |
165 | /* |
166 | * A2065 Expansion Board Structure |
167 | */ |
168 | |
169 | #define A2065_LANCE 0x4000 |
170 | |
171 | #define A2065_RAM 0x8000 |
172 | #define A2065_RAM_SIZE 0x8000 |
173 | |
174 | |