1	// SPDX-License-Identifier: GPL-2.0-or-later
2
3	/* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
4	* Copyright (C) 2004 Advanced Micro Devices
5	*
6	* Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
7	* Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
8	* Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
9	* Derived from the lance driver written 1993,1994,1995 by Donald Becker.
10	* Copyright 1993 United States Government as represented by the
11	* Director, National Security Agency.[ pcnet32.c ]
12	* Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
13	* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
14	*
15
16	Module Name:
17
18	amd8111e.c
19
20	Abstract:
21
22	AMD8111 based 10/100 Ethernet Controller Driver.
23
24	Environment:
25
26	Kernel Mode
27
28	Revision History:
29	3.0.0
30	Initial Revision.
31	3.0.1
32	1. Dynamic interrupt coalescing.
33	2. Removed prev_stats.
34	3. MII support.
35	4. Dynamic IPG support
36	3.0.2 05/29/2003
37	1. Bug fix: Fixed failure to send jumbo packets larger than 4k.
38	2. Bug fix: Fixed VLAN support failure.
39	3. Bug fix: Fixed receive interrupt coalescing bug.
40	4. Dynamic IPG support is disabled by default.
41	3.0.3 06/05/2003
42	1. Bug fix: Fixed failure to close the interface if SMP is enabled.
43	3.0.4 12/09/2003
44	1. Added set_mac_address routine for bonding driver support.
45	2. Tested the driver for bonding support
46	3. Bug fix: Fixed mismach in actual receive buffer length and length
47	indicated to the h/w.
48	4. Modified amd8111e_rx() routine to receive all the received packets
49	in the first interrupt.
50	5. Bug fix: Corrected rx_errors reported in get_stats() function.
51	3.0.5 03/22/2004
52	1. Added NAPI support
53
54	*/
55
56
57	#include <linux/module.h>
58	#include <linux/kernel.h>
59	#include <linux/types.h>
60	#include <linux/compiler.h>
61	#include <linux/delay.h>
62	#include <linux/interrupt.h>
63	#include <linux/ioport.h>
64	#include <linux/pci.h>
65	#include <linux/netdevice.h>
66	#include <linux/etherdevice.h>
67	#include <linux/skbuff.h>
68	#include <linux/ethtool.h>
69	#include <linux/mii.h>
70	#include <linux/if_vlan.h>
71	#include <linux/ctype.h>
72	#include <linux/crc32.h>
73	#include <linux/dma-mapping.h>
74
75	#include <asm/io.h>
76	#include <asm/byteorder.h>
77	#include <linux/uaccess.h>
78
79	#if IS_ENABLED(CONFIG_VLAN_8021Q)
80	#define AMD8111E_VLAN_TAG_USED 1
81	#else
82	#define AMD8111E_VLAN_TAG_USED 0
83	#endif
84
85	#include "amd8111e.h"
86	#define MODULE_NAME "amd8111e"
87	MODULE_AUTHOR("Advanced Micro Devices, Inc.");
88	MODULE_DESCRIPTION("AMD8111 based 10/100 Ethernet Controller.");
89	MODULE_LICENSE("GPL");
90	module_param_array(speed_duplex, int, NULL, 0);
91	MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotiate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
92	module_param_array(coalesce, bool, NULL, 0);
93	MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
94	module_param_array(dynamic_ipg, bool, NULL, 0);
95	MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
96
97	/* This function will read the PHY registers. */
98	static int amd8111e_read_phy(struct amd8111e_priv *lp,
99	int phy_id, int reg, u32 *val)
100	{
101	void __iomem *mmio = lp->mmio;
102	unsigned int reg_val;
103	unsigned int repeat = REPEAT_CNT;
104
105	reg_val = readl(addr: mmio + PHY_ACCESS);
106	while (reg_val & PHY_CMD_ACTIVE)
107	reg_val = readl(addr: mmio + PHY_ACCESS);
108
109	writel(val: PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
110	((reg & 0x1f) << 16), addr: mmio + PHY_ACCESS);
111	do {
112	reg_val = readl(addr: mmio + PHY_ACCESS);
113	udelay(30); /* It takes 30 us to read/write data */
114	} while (--repeat && (reg_val & PHY_CMD_ACTIVE));
115	if (reg_val & PHY_RD_ERR)
116	goto err_phy_read;
117
118	*val = reg_val & 0xffff;
119	return 0;
120	err_phy_read:
121	*val = 0;
122	return -EINVAL;
123
124	}
125
126	/* This function will write into PHY registers. */
127	static int amd8111e_write_phy(struct amd8111e_priv *lp,
128	int phy_id, int reg, u32 val)
129	{
130	unsigned int repeat = REPEAT_CNT;
131	void __iomem *mmio = lp->mmio;
132	unsigned int reg_val;
133
134	reg_val = readl(addr: mmio + PHY_ACCESS);
135	while (reg_val & PHY_CMD_ACTIVE)
136	reg_val = readl(addr: mmio + PHY_ACCESS);
137
138	writel(val: PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
139	((reg & 0x1f) << 16)|val, addr: mmio + PHY_ACCESS);
140
141	do {
142	reg_val = readl(addr: mmio + PHY_ACCESS);
143	udelay(30); /* It takes 30 us to read/write the data */
144	} while (--repeat && (reg_val & PHY_CMD_ACTIVE));
145
146	if (reg_val & PHY_RD_ERR)
147	goto err_phy_write;
148
149	return 0;
150
151	err_phy_write:
152	return -EINVAL;
153
154	}
155
156	/* This is the mii register read function provided to the mii interface. */
157	static int amd8111e_mdio_read(struct net_device *dev, int phy_id, int reg_num)
158	{
159	struct amd8111e_priv *lp = netdev_priv(dev);
160	unsigned int reg_val;
161
162	amd8111e_read_phy(lp, phy_id, reg: reg_num, val: &reg_val);
163	return reg_val;
164
165	}
166
167	/* This is the mii register write function provided to the mii interface. */
168	static void amd8111e_mdio_write(struct net_device *dev,
169	int phy_id, int reg_num, int val)
170	{
171	struct amd8111e_priv *lp = netdev_priv(dev);
172
173	amd8111e_write_phy(lp, phy_id, reg: reg_num, val);
174	}
175
176	/* This function will set PHY speed. During initialization sets
177	* the original speed to 100 full
178	*/
179	static void amd8111e_set_ext_phy(struct net_device *dev)
180	{
181	struct amd8111e_priv *lp = netdev_priv(dev);
182	u32 bmcr, advert, tmp;
183
184	/* Determine mii register values to set the speed */
185	advert = amd8111e_mdio_read(dev, phy_id: lp->ext_phy_addr, MII_ADVERTISE);
186	tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
187	switch (lp->ext_phy_option) {
188	default:
189	case SPEED_AUTONEG: /* advertise all values */
190	tmp |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
191	ADVERTISE_100HALF | ADVERTISE_100FULL);
192	break;
193	case SPEED10_HALF:
194	tmp |= ADVERTISE_10HALF;
195	break;
196	case SPEED10_FULL:
197	tmp |= ADVERTISE_10FULL;
198	break;
199	case SPEED100_HALF:
200	tmp |= ADVERTISE_100HALF;
201	break;
202	case SPEED100_FULL:
203	tmp |= ADVERTISE_100FULL;
204	break;
205	}
206
207	if(advert != tmp)
208	amd8111e_mdio_write(dev, phy_id: lp->ext_phy_addr, MII_ADVERTISE, val: tmp);
209	/* Restart auto negotiation */
210	bmcr = amd8111e_mdio_read(dev, phy_id: lp->ext_phy_addr, MII_BMCR);
211	bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
212	amd8111e_mdio_write(dev, phy_id: lp->ext_phy_addr, MII_BMCR, val: bmcr);
213
214	}
215
216	/* This function will unmap skb->data space and will free
217	* all transmit and receive skbuffs.
218	*/
219	static int amd8111e_free_skbs(struct net_device *dev)
220	{
221	struct amd8111e_priv *lp = netdev_priv(dev);
222	struct sk_buff *rx_skbuff;
223	int i;
224
225	/* Freeing transmit skbs */
226	for (i = 0; i < NUM_TX_BUFFERS; i++) {
227	if (lp->tx_skbuff[i]) {
228	dma_unmap_single(&lp->pci_dev->dev,
229	lp->tx_dma_addr[i],
230	lp->tx_skbuff[i]->len, DMA_TO_DEVICE);
231	dev_kfree_skb(lp->tx_skbuff[i]);
232	lp->tx_skbuff[i] = NULL;
233	lp->tx_dma_addr[i] = 0;
234	}
235	}
236	/* Freeing previously allocated receive buffers */
237	for (i = 0; i < NUM_RX_BUFFERS; i++) {
238	rx_skbuff = lp->rx_skbuff[i];
239	if (rx_skbuff) {
240	dma_unmap_single(&lp->pci_dev->dev,
241	lp->rx_dma_addr[i],
242	lp->rx_buff_len - 2, DMA_FROM_DEVICE);
243	dev_kfree_skb(lp->rx_skbuff[i]);
244	lp->rx_skbuff[i] = NULL;
245	lp->rx_dma_addr[i] = 0;
246	}
247	}
248
249	return 0;
250	}
251
252	/* This will set the receive buffer length corresponding
253	* to the mtu size of networkinterface.
254	*/
255	static inline void amd8111e_set_rx_buff_len(struct net_device *dev)
256	{
257	struct amd8111e_priv *lp = netdev_priv(dev);
258	unsigned int mtu = dev->mtu;
259
260	if (mtu > ETH_DATA_LEN) {
261	/* MTU + ethernet header + FCS
262	* + optional VLAN tag + skb reserve space 2
263	*/
264	lp->rx_buff_len = mtu + ETH_HLEN + 10;
265	lp->options |= OPTION_JUMBO_ENABLE;
266	} else {
267	lp->rx_buff_len = PKT_BUFF_SZ;
268	lp->options &= ~OPTION_JUMBO_ENABLE;
269	}
270	}
271
272	/* This function will free all the previously allocated buffers,
273	* determine new receive buffer length and will allocate new receive buffers.
274	* This function also allocates and initializes both the transmitter
275	* and receive hardware descriptors.
276	*/
277	static int amd8111e_init_ring(struct net_device *dev)
278	{
279	struct amd8111e_priv *lp = netdev_priv(dev);
280	int i;
281
282	lp->rx_idx = lp->tx_idx = 0;
283	lp->tx_complete_idx = 0;
284	lp->tx_ring_idx = 0;
285
286
287	if (lp->opened)
288	/* Free previously allocated transmit and receive skbs */
289	amd8111e_free_skbs(dev);
290
291	else {
292	/* allocate the tx and rx descriptors */
293	lp->tx_ring = dma_alloc_coherent(dev: &lp->pci_dev->dev,
294	size: sizeof(struct amd8111e_tx_dr) * NUM_TX_RING_DR,
295	dma_handle: &lp->tx_ring_dma_addr, GFP_ATOMIC);
296	if (!lp->tx_ring)
297	goto err_no_mem;
298
299	lp->rx_ring = dma_alloc_coherent(dev: &lp->pci_dev->dev,
300	size: sizeof(struct amd8111e_rx_dr) * NUM_RX_RING_DR,
301	dma_handle: &lp->rx_ring_dma_addr, GFP_ATOMIC);
302	if (!lp->rx_ring)
303	goto err_free_tx_ring;
304	}
305
306	/* Set new receive buff size */
307	amd8111e_set_rx_buff_len(dev);
308
309	/* Allocating receive skbs */
310	for (i = 0; i < NUM_RX_BUFFERS; i++) {
311
312	lp->rx_skbuff[i] = netdev_alloc_skb(dev, length: lp->rx_buff_len);
313	if (!lp->rx_skbuff[i]) {
314	/* Release previos allocated skbs */
315	for (--i; i >= 0; i--)
316	dev_kfree_skb(lp->rx_skbuff[i]);
317	goto err_free_rx_ring;
318	}
319	skb_reserve(skb: lp->rx_skbuff[i], len: 2);
320	}
321	/* Initilaizing receive descriptors */
322	for (i = 0; i < NUM_RX_BUFFERS; i++) {
323	lp->rx_dma_addr[i] = dma_map_single(&lp->pci_dev->dev,
324	lp->rx_skbuff[i]->data,
325	lp->rx_buff_len - 2,
326	DMA_FROM_DEVICE);
327
328	lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
329	lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
330	wmb();
331	lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
332	}
333
334	/* Initializing transmit descriptors */
335	for (i = 0; i < NUM_TX_RING_DR; i++) {
336	lp->tx_ring[i].buff_phy_addr = 0;
337	lp->tx_ring[i].tx_flags = 0;
338	lp->tx_ring[i].buff_count = 0;
339	}
340
341	return 0;
342
343	err_free_rx_ring:
344
345	dma_free_coherent(dev: &lp->pci_dev->dev,
346	size: sizeof(struct amd8111e_rx_dr) * NUM_RX_RING_DR,
347	cpu_addr: lp->rx_ring, dma_handle: lp->rx_ring_dma_addr);
348
349	err_free_tx_ring:
350
351	dma_free_coherent(dev: &lp->pci_dev->dev,
352	size: sizeof(struct amd8111e_tx_dr) * NUM_TX_RING_DR,
353	cpu_addr: lp->tx_ring, dma_handle: lp->tx_ring_dma_addr);
354
355	err_no_mem:
356	return -ENOMEM;
357	}
358
359	/* This function will set the interrupt coalescing according
360	* to the input arguments
361	*/
362	static int amd8111e_set_coalesce(struct net_device *dev, enum coal_mode cmod)
363	{
364	unsigned int timeout;
365	unsigned int event_count;
366
367	struct amd8111e_priv *lp = netdev_priv(dev);
368	void __iomem *mmio = lp->mmio;
369	struct amd8111e_coalesce_conf *coal_conf = &lp->coal_conf;
370
371
372	switch(cmod)
373	{
374	case RX_INTR_COAL :
375	timeout = coal_conf->rx_timeout;
376	event_count = coal_conf->rx_event_count;
377	if (timeout > MAX_TIMEOUT ||
378	event_count > MAX_EVENT_COUNT)
379	return -EINVAL;
380
381	timeout = timeout * DELAY_TIMER_CONV;
382	writel(val: VAL0|STINTEN, addr: mmio+INTEN0);
383	writel(val: (u32)DLY_INT_A_R0 | (event_count << 16) |
384	timeout, addr: mmio + DLY_INT_A);
385	break;
386
387	case TX_INTR_COAL:
388	timeout = coal_conf->tx_timeout;
389	event_count = coal_conf->tx_event_count;
390	if (timeout > MAX_TIMEOUT ||
391	event_count > MAX_EVENT_COUNT)
392	return -EINVAL;
393
394
395	timeout = timeout * DELAY_TIMER_CONV;
396	writel(val: VAL0 | STINTEN, addr: mmio + INTEN0);
397	writel(val: (u32)DLY_INT_B_T0 | (event_count << 16) |
398	timeout, addr: mmio + DLY_INT_B);
399	break;
400
401	case DISABLE_COAL:
402	writel(val: 0, addr: mmio + STVAL);
403	writel(val: STINTEN, addr: mmio + INTEN0);
404	writel(val: 0, addr: mmio + DLY_INT_B);
405	writel(val: 0, addr: mmio + DLY_INT_A);
406	break;
407	case ENABLE_COAL:
408	/* Start the timer */
409	writel(val: (u32)SOFT_TIMER_FREQ, addr: mmio + STVAL); /* 0.5 sec */
410	writel(val: VAL0 | STINTEN, addr: mmio + INTEN0);
411	break;
412	default:
413	break;
414
415	}
416	return 0;
417
418	}
419
420	/* This function initializes the device registers and starts the device. */
421	static int amd8111e_restart(struct net_device *dev)
422	{
423	struct amd8111e_priv *lp = netdev_priv(dev);
424	void __iomem *mmio = lp->mmio;
425	int i, reg_val;
426
427	/* stop the chip */
428	writel(val: RUN, addr: mmio + CMD0);
429
430	if (amd8111e_init_ring(dev))
431	return -ENOMEM;
432
433	/* enable the port manager and set auto negotiation always */
434	writel(val: (u32)VAL1 | EN_PMGR, addr: mmio + CMD3);
435	writel(val: (u32)XPHYANE | XPHYRST, addr: mmio + CTRL2);
436
437	amd8111e_set_ext_phy(dev);
438
439	/* set control registers */
440	reg_val = readl(addr: mmio + CTRL1);
441	reg_val &= ~XMTSP_MASK;
442	writel(val: reg_val | XMTSP_128 | CACHE_ALIGN, addr: mmio + CTRL1);
443
444	/* enable interrupt */
445	writel(val: APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
446	APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN |
447	SPNDINTEN | MPINTEN | SINTEN | STINTEN, addr: mmio + INTEN0);
448
449	writel(val: VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, addr: mmio + INTEN0);
450
451	/* initialize tx and rx ring base addresses */
452	writel(val: (u32)lp->tx_ring_dma_addr, addr: mmio + XMT_RING_BASE_ADDR0);
453	writel(val: (u32)lp->rx_ring_dma_addr, addr: mmio + RCV_RING_BASE_ADDR0);
454
455	writew(val: (u32)NUM_TX_RING_DR, addr: mmio + XMT_RING_LEN0);
456	writew(val: (u16)NUM_RX_RING_DR, addr: mmio + RCV_RING_LEN0);
457
458	/* set default IPG to 96 */
459	writew(val: (u32)DEFAULT_IPG, addr: mmio + IPG);
460	writew(val: (u32)(DEFAULT_IPG-IFS1_DELTA), addr: mmio + IFS1);
461
462	if (lp->options & OPTION_JUMBO_ENABLE) {
463	writel(val: (u32)VAL2|JUMBO, addr: mmio + CMD3);
464	/* Reset REX_UFLO */
465	writel(val: REX_UFLO, addr: mmio + CMD2);
466	/* Should not set REX_UFLO for jumbo frames */
467	writel(val: VAL0 | APAD_XMT | REX_RTRY, addr: mmio + CMD2);
468	} else {
469	writel(val: VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, addr: mmio + CMD2);
470	writel(val: (u32)JUMBO, addr: mmio + CMD3);
471	}
472
473	#if AMD8111E_VLAN_TAG_USED
474	writel(val: (u32)VAL2 | VSIZE | VL_TAG_DEL, addr: mmio + CMD3);
475	#endif
476	writel(val: VAL0 | APAD_XMT | REX_RTRY, addr: mmio + CMD2);
477
478	/* Setting the MAC address to the device */
479	for (i = 0; i < ETH_ALEN; i++)
480	writeb(val: dev->dev_addr[i], addr: mmio + PADR + i);
481
482	/* Enable interrupt coalesce */
483	if (lp->options & OPTION_INTR_COAL_ENABLE) {
484	netdev_info(dev, format: "Interrupt Coalescing Enabled.\n");
485	amd8111e_set_coalesce(dev, cmod: ENABLE_COAL);
486	}
487
488	/* set RUN bit to start the chip */
489	writel(val: VAL2 | RDMD0, addr: mmio + CMD0);
490	writel(val: VAL0 | INTREN | RUN, addr: mmio + CMD0);
491
492	/* To avoid PCI posting bug */
493	readl(addr: mmio+CMD0);
494	return 0;
495	}
496
497	/* This function clears necessary the device registers. */
498	static void amd8111e_init_hw_default(struct amd8111e_priv *lp)
499	{
500	unsigned int reg_val;
501	unsigned int logic_filter[2] = {0,};
502	void __iomem *mmio = lp->mmio;
503
504
505	/* stop the chip */
506	writel(val: RUN, addr: mmio + CMD0);
507
508	/* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
509	writew( val: 0x8100 | lp->ext_phy_addr, addr: mmio + AUTOPOLL0);
510
511	/* Clear RCV_RING_BASE_ADDR */
512	writel(val: 0, addr: mmio + RCV_RING_BASE_ADDR0);
513
514	/* Clear XMT_RING_BASE_ADDR */
515	writel(val: 0, addr: mmio + XMT_RING_BASE_ADDR0);
516	writel(val: 0, addr: mmio + XMT_RING_BASE_ADDR1);
517	writel(val: 0, addr: mmio + XMT_RING_BASE_ADDR2);
518	writel(val: 0, addr: mmio + XMT_RING_BASE_ADDR3);
519
520	/* Clear CMD0 */
521	writel(val: CMD0_CLEAR, addr: mmio + CMD0);
522
523	/* Clear CMD2 */
524	writel(val: CMD2_CLEAR, addr: mmio + CMD2);
525
526	/* Clear CMD7 */
527	writel(val: CMD7_CLEAR, addr: mmio + CMD7);
528
529	/* Clear DLY_INT_A and DLY_INT_B */
530	writel(val: 0x0, addr: mmio + DLY_INT_A);
531	writel(val: 0x0, addr: mmio + DLY_INT_B);
532
533	/* Clear FLOW_CONTROL */
534	writel(val: 0x0, addr: mmio + FLOW_CONTROL);
535
536	/* Clear INT0 write 1 to clear register */
537	reg_val = readl(addr: mmio + INT0);
538	writel(val: reg_val, addr: mmio + INT0);
539
540	/* Clear STVAL */
541	writel(val: 0x0, addr: mmio + STVAL);
542
543	/* Clear INTEN0 */
544	writel(val: INTEN0_CLEAR, addr: mmio + INTEN0);
545
546	/* Clear LADRF */
547	writel(val: 0x0, addr: mmio + LADRF);
548
549	/* Set SRAM_SIZE & SRAM_BOUNDARY registers */
550	writel(val: 0x80010, addr: mmio + SRAM_SIZE);
551
552	/* Clear RCV_RING0_LEN */
553	writel(val: 0x0, addr: mmio + RCV_RING_LEN0);
554
555	/* Clear XMT_RING0/1/2/3_LEN */
556	writel(val: 0x0, addr: mmio + XMT_RING_LEN0);
557	writel(val: 0x0, addr: mmio + XMT_RING_LEN1);
558	writel(val: 0x0, addr: mmio + XMT_RING_LEN2);
559	writel(val: 0x0, addr: mmio + XMT_RING_LEN3);
560
561	/* Clear XMT_RING_LIMIT */
562	writel(val: 0x0, addr: mmio + XMT_RING_LIMIT);
563
564	/* Clear MIB */
565	writew(val: MIB_CLEAR, addr: mmio + MIB_ADDR);
566
567	/* Clear LARF */
568	amd8111e_writeq(*(u64 *)logic_filter, mmio + LADRF);
569
570	/* SRAM_SIZE register */
571	reg_val = readl(addr: mmio + SRAM_SIZE);
572
573	if (lp->options & OPTION_JUMBO_ENABLE)
574	writel(val: VAL2 | JUMBO, addr: mmio + CMD3);
575	#if AMD8111E_VLAN_TAG_USED
576	writel(val: VAL2 | VSIZE | VL_TAG_DEL, addr: mmio + CMD3);
577	#endif
578	/* Set default value to CTRL1 Register */
579	writel(val: CTRL1_DEFAULT, addr: mmio + CTRL1);
580
581	/* To avoid PCI posting bug */
582	readl(addr: mmio + CMD2);
583
584	}
585
586	/* This function disables the interrupt and clears all the pending
587	* interrupts in INT0
588	*/
589	static void amd8111e_disable_interrupt(struct amd8111e_priv *lp)
590	{
591	u32 intr0;
592
593	/* Disable interrupt */
594	writel(val: INTREN, addr: lp->mmio + CMD0);
595
596	/* Clear INT0 */
597	intr0 = readl(addr: lp->mmio + INT0);
598	writel(val: intr0, addr: lp->mmio + INT0);
599
600	/* To avoid PCI posting bug */
601	readl(addr: lp->mmio + INT0);
602
603	}
604
605	/* This function stops the chip. */
606	static void amd8111e_stop_chip(struct amd8111e_priv *lp)
607	{
608	writel(val: RUN, addr: lp->mmio + CMD0);
609
610	/* To avoid PCI posting bug */
611	readl(addr: lp->mmio + CMD0);
612	}
613
614	/* This function frees the transmiter and receiver descriptor rings. */
615	static void amd8111e_free_ring(struct amd8111e_priv *lp)
616	{
617	/* Free transmit and receive descriptor rings */
618	if (lp->rx_ring) {
619	dma_free_coherent(dev: &lp->pci_dev->dev,
620	size: sizeof(struct amd8111e_rx_dr) * NUM_RX_RING_DR,
621	cpu_addr: lp->rx_ring, dma_handle: lp->rx_ring_dma_addr);
622	lp->rx_ring = NULL;
623	}
624
625	if (lp->tx_ring) {
626	dma_free_coherent(dev: &lp->pci_dev->dev,
627	size: sizeof(struct amd8111e_tx_dr) * NUM_TX_RING_DR,
628	cpu_addr: lp->tx_ring, dma_handle: lp->tx_ring_dma_addr);
629
630	lp->tx_ring = NULL;
631	}
632
633	}
634
635	/* This function will free all the transmit skbs that are actually
636	* transmitted by the device. It will check the ownership of the
637	* skb before freeing the skb.
638	*/
639	static int amd8111e_tx(struct net_device *dev)
640	{
641	struct amd8111e_priv *lp = netdev_priv(dev);
642	int tx_index;
643	int status;
644	/* Complete all the transmit packet */
645	while (lp->tx_complete_idx != lp->tx_idx) {
646	tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
647	status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
648
649	if (status & OWN_BIT)
650	break; /* It still hasn't been Txed */
651
652	lp->tx_ring[tx_index].buff_phy_addr = 0;
653
654	/* We must free the original skb */
655	if (lp->tx_skbuff[tx_index]) {
656	dma_unmap_single(&lp->pci_dev->dev,
657	lp->tx_dma_addr[tx_index],
658	lp->tx_skbuff[tx_index]->len,
659	DMA_TO_DEVICE);
660	dev_consume_skb_irq(skb: lp->tx_skbuff[tx_index]);
661	lp->tx_skbuff[tx_index] = NULL;
662	lp->tx_dma_addr[tx_index] = 0;
663	}
664	lp->tx_complete_idx++;
665	/*COAL update tx coalescing parameters */
666	lp->coal_conf.tx_packets++;
667	lp->coal_conf.tx_bytes +=
668	le16_to_cpu(lp->tx_ring[tx_index].buff_count);
669
670	if (netif_queue_stopped(dev) &&
671	lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS + 2) {
672	/* The ring is no longer full, clear tbusy. */
673	/* lp->tx_full = 0; */
674	netif_wake_queue(dev);
675	}
676	}
677	return 0;
678	}
679
680	/* This function handles the driver receive operation in polling mode */
681	static int amd8111e_rx_poll(struct napi_struct *napi, int budget)
682	{
683	struct amd8111e_priv *lp = container_of(napi, struct amd8111e_priv, napi);
684	struct net_device *dev = lp->amd8111e_net_dev;
685	int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
686	void __iomem *mmio = lp->mmio;
687	struct sk_buff *skb, *new_skb;
688	int min_pkt_len, status;
689	int num_rx_pkt = 0;
690	short pkt_len;
691	#if AMD8111E_VLAN_TAG_USED
692	short vtag;
693	#endif
694
695	while (num_rx_pkt < budget) {
696	status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
697	if (status & OWN_BIT)
698	break;
699
700	/* There is a tricky error noted by John Murphy,
701	* <murf@perftech.com> to Russ Nelson: Even with
702	* full-sized * buffers it's possible for a
703	* jabber packet to use two buffers, with only
704	* the last correctly noting the error.
705	*/
706	if (status & ERR_BIT) {
707	/* resetting flags */
708	lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
709	goto err_next_pkt;
710	}
711	/* check for STP and ENP */
712	if (!((status & STP_BIT) && (status & ENP_BIT))) {
713	/* resetting flags */
714	lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
715	goto err_next_pkt;
716	}
717	pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
718
719	#if AMD8111E_VLAN_TAG_USED
720	vtag = status & TT_MASK;
721	/* MAC will strip vlan tag */
722	if (vtag != 0)
723	min_pkt_len = MIN_PKT_LEN - 4;
724	else
725	#endif
726	min_pkt_len = MIN_PKT_LEN;
727
728	if (pkt_len < min_pkt_len) {
729	lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
730	lp->drv_rx_errors++;
731	goto err_next_pkt;
732	}
733	new_skb = netdev_alloc_skb(dev, length: lp->rx_buff_len);
734	if (!new_skb) {
735	/* if allocation fail,
736	* ignore that pkt and go to next one
737	*/
738	lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
739	lp->drv_rx_errors++;
740	goto err_next_pkt;
741	}
742
743	skb_reserve(skb: new_skb, len: 2);
744	skb = lp->rx_skbuff[rx_index];
745	dma_unmap_single(&lp->pci_dev->dev, lp->rx_dma_addr[rx_index],
746	lp->rx_buff_len - 2, DMA_FROM_DEVICE);
747	skb_put(skb, len: pkt_len);
748	lp->rx_skbuff[rx_index] = new_skb;
749	lp->rx_dma_addr[rx_index] = dma_map_single(&lp->pci_dev->dev,
750	new_skb->data,
751	lp->rx_buff_len - 2,
752	DMA_FROM_DEVICE);
753
754	skb->protocol = eth_type_trans(skb, dev);
755
756	#if AMD8111E_VLAN_TAG_USED
757	if (vtag == TT_VLAN_TAGGED) {
758	u16 vlan_tag = le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info);
759	__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci: vlan_tag);
760	}
761	#endif
762	napi_gro_receive(napi, skb);
763	/* COAL update rx coalescing parameters */
764	lp->coal_conf.rx_packets++;
765	lp->coal_conf.rx_bytes += pkt_len;
766	num_rx_pkt++;
767
768	err_next_pkt:
769	lp->rx_ring[rx_index].buff_phy_addr
770	= cpu_to_le32(lp->rx_dma_addr[rx_index]);
771	lp->rx_ring[rx_index].buff_count =
772	cpu_to_le16(lp->rx_buff_len-2);
773	wmb();
774	lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
775	rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
776	}
777
778	if (num_rx_pkt < budget && napi_complete_done(n: napi, work_done: num_rx_pkt)) {
779	unsigned long flags;
780
781	/* Receive descriptor is empty now */
782	spin_lock_irqsave(&lp->lock, flags);
783	writel(val: VAL0|RINTEN0, addr: mmio + INTEN0);
784	writel(val: VAL2 | RDMD0, addr: mmio + CMD0);
785	spin_unlock_irqrestore(lock: &lp->lock, flags);
786	}
787
788	return num_rx_pkt;
789	}
790
791	/* This function will indicate the link status to the kernel. */
792	static int amd8111e_link_change(struct net_device *dev)
793	{
794	struct amd8111e_priv *lp = netdev_priv(dev);
795	int status0, speed;
796
797	/* read the link change */
798	status0 = readl(addr: lp->mmio + STAT0);
799
800	if (status0 & LINK_STATS) {
801	if (status0 & AUTONEG_COMPLETE)
802	lp->link_config.autoneg = AUTONEG_ENABLE;
803	else
804	lp->link_config.autoneg = AUTONEG_DISABLE;
805
806	if (status0 & FULL_DPLX)
807	lp->link_config.duplex = DUPLEX_FULL;
808	else
809	lp->link_config.duplex = DUPLEX_HALF;
810	speed = (status0 & SPEED_MASK) >> 7;
811	if (speed == PHY_SPEED_10)
812	lp->link_config.speed = SPEED_10;
813	else if (speed == PHY_SPEED_100)
814	lp->link_config.speed = SPEED_100;
815
816	netdev_info(dev, format: "Link is Up. Speed is %s Mbps %s Duplex\n",
817	(lp->link_config.speed == SPEED_100) ?
818	"100" : "10",
819	(lp->link_config.duplex == DUPLEX_FULL) ?
820	"Full" : "Half");
821
822	netif_carrier_on(dev);
823	} else {
824	lp->link_config.speed = SPEED_INVALID;
825	lp->link_config.duplex = DUPLEX_INVALID;
826	lp->link_config.autoneg = AUTONEG_INVALID;
827	netdev_info(dev, format: "Link is Down.\n");
828	netif_carrier_off(dev);
829	}
830
831	return 0;
832	}
833
834	/* This function reads the mib counters. */
835	static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
836	{
837	unsigned int status;
838	unsigned int data;
839	unsigned int repeat = REPEAT_CNT;
840
841	writew(val: MIB_RD_CMD | MIB_COUNTER, addr: mmio + MIB_ADDR);
842	do {
843	status = readw(addr: mmio + MIB_ADDR);
844	udelay(2); /* controller takes MAX 2 us to get mib data */
845	}
846	while (--repeat && (status & MIB_CMD_ACTIVE));
847
848	data = readl(addr: mmio + MIB_DATA);
849	return data;
850	}
851
852	/* This function reads the mib registers and returns the hardware statistics.
853	* It updates previous internal driver statistics with new values.
854	*/
855	static struct net_device_stats *amd8111e_get_stats(struct net_device *dev)
856	{
857	struct amd8111e_priv *lp = netdev_priv(dev);
858	void __iomem *mmio = lp->mmio;
859	unsigned long flags;
860	struct net_device_stats *new_stats = &dev->stats;
861
862	if (!lp->opened)
863	return new_stats;
864	spin_lock_irqsave(&lp->lock, flags);
865
866	/* stats.rx_packets */
867	new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
868	amd8111e_read_mib(mmio, rcv_multicast_pkts)+
869	amd8111e_read_mib(mmio, rcv_unicast_pkts);
870
871	/* stats.tx_packets */
872	new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
873
874	/*stats.rx_bytes */
875	new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
876
877	/* stats.tx_bytes */
878	new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
879
880	/* stats.rx_errors */
881	/* hw errors + errors driver reported */
882	new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
883	amd8111e_read_mib(mmio, rcv_fragments)+
884	amd8111e_read_mib(mmio, rcv_jabbers)+
885	amd8111e_read_mib(mmio, rcv_alignment_errors)+
886	amd8111e_read_mib(mmio, rcv_fcs_errors)+
887	amd8111e_read_mib(mmio, rcv_miss_pkts)+
888	lp->drv_rx_errors;
889
890	/* stats.tx_errors */
891	new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
892
893	/* stats.rx_dropped*/
894	new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
895
896	/* stats.tx_dropped*/
897	new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts);
898
899	/* stats.multicast*/
900	new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
901
902	/* stats.collisions*/
903	new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
904
905	/* stats.rx_length_errors*/
906	new_stats->rx_length_errors =
907	amd8111e_read_mib(mmio, rcv_undersize_pkts)+
908	amd8111e_read_mib(mmio, rcv_oversize_pkts);
909
910	/* stats.rx_over_errors*/
911	new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
912
913	/* stats.rx_crc_errors*/
914	new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
915
916	/* stats.rx_frame_errors*/
917	new_stats->rx_frame_errors =
918	amd8111e_read_mib(mmio, rcv_alignment_errors);
919
920	/* stats.rx_fifo_errors */
921	new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
922
923	/* stats.rx_missed_errors */
924	new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
925
926	/* stats.tx_aborted_errors*/
927	new_stats->tx_aborted_errors =
928	amd8111e_read_mib(mmio, xmt_excessive_collision);
929
930	/* stats.tx_carrier_errors*/
931	new_stats->tx_carrier_errors =
932	amd8111e_read_mib(mmio, xmt_loss_carrier);
933
934	/* stats.tx_fifo_errors*/
935	new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
936
937	/* stats.tx_window_errors*/
938	new_stats->tx_window_errors =
939	amd8111e_read_mib(mmio, xmt_late_collision);
940
941	/* Reset the mibs for collecting new statistics */
942	/* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
943
944	spin_unlock_irqrestore(lock: &lp->lock, flags);
945
946	return new_stats;
947	}
948
949	/* This function recalculate the interrupt coalescing mode on every interrupt
950	* according to the datarate and the packet rate.
951	*/
952	static int amd8111e_calc_coalesce(struct net_device *dev)
953	{
954	struct amd8111e_priv *lp = netdev_priv(dev);
955	struct amd8111e_coalesce_conf *coal_conf = &lp->coal_conf;
956	int tx_pkt_rate;
957	int rx_pkt_rate;
958	int tx_data_rate;
959	int rx_data_rate;
960	int rx_pkt_size;
961	int tx_pkt_size;
962
963	tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
964	coal_conf->tx_prev_packets = coal_conf->tx_packets;
965
966	tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
967	coal_conf->tx_prev_bytes = coal_conf->tx_bytes;
968
969	rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
970	coal_conf->rx_prev_packets = coal_conf->rx_packets;
971
972	rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
973	coal_conf->rx_prev_bytes = coal_conf->rx_bytes;
974
975	if (rx_pkt_rate < 800) {
976	if (coal_conf->rx_coal_type != NO_COALESCE) {
977
978	coal_conf->rx_timeout = 0x0;
979	coal_conf->rx_event_count = 0;
980	amd8111e_set_coalesce(dev, cmod: RX_INTR_COAL);
981	coal_conf->rx_coal_type = NO_COALESCE;
982	}
983	} else {
984
985	rx_pkt_size = rx_data_rate/rx_pkt_rate;
986	if (rx_pkt_size < 128) {
987	if (coal_conf->rx_coal_type != NO_COALESCE) {
988
989	coal_conf->rx_timeout = 0;
990	coal_conf->rx_event_count = 0;
991	amd8111e_set_coalesce(dev, cmod: RX_INTR_COAL);
992	coal_conf->rx_coal_type = NO_COALESCE;
993	}
994
995	} else if ((rx_pkt_size >= 128) && (rx_pkt_size < 512)) {
996
997	if (coal_conf->rx_coal_type != LOW_COALESCE) {
998	coal_conf->rx_timeout = 1;
999	coal_conf->rx_event_count = 4;
1000	amd8111e_set_coalesce(dev, cmod: RX_INTR_COAL);
1001	coal_conf->rx_coal_type = LOW_COALESCE;
1002	}
1003	} else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)) {
1004
1005	if (coal_conf->rx_coal_type != MEDIUM_COALESCE) {
1006	coal_conf->rx_timeout = 1;
1007	coal_conf->rx_event_count = 4;
1008	amd8111e_set_coalesce(dev, cmod: RX_INTR_COAL);
1009	coal_conf->rx_coal_type = MEDIUM_COALESCE;
1010	}
1011
1012	} else if (rx_pkt_size >= 1024) {
1013
1014	if (coal_conf->rx_coal_type != HIGH_COALESCE) {
1015	coal_conf->rx_timeout = 2;
1016	coal_conf->rx_event_count = 3;
1017	amd8111e_set_coalesce(dev, cmod: RX_INTR_COAL);
1018	coal_conf->rx_coal_type = HIGH_COALESCE;
1019	}
1020	}
1021	}
1022	/* NOW FOR TX INTR COALESC */
1023	if (tx_pkt_rate < 800) {
1024	if (coal_conf->tx_coal_type != NO_COALESCE) {
1025
1026	coal_conf->tx_timeout = 0x0;
1027	coal_conf->tx_event_count = 0;
1028	amd8111e_set_coalesce(dev, cmod: TX_INTR_COAL);
1029	coal_conf->tx_coal_type = NO_COALESCE;
1030	}
1031	} else {
1032
1033	tx_pkt_size = tx_data_rate/tx_pkt_rate;
1034	if (tx_pkt_size < 128) {
1035
1036	if (coal_conf->tx_coal_type != NO_COALESCE) {
1037
1038	coal_conf->tx_timeout = 0;
1039	coal_conf->tx_event_count = 0;
1040	amd8111e_set_coalesce(dev, cmod: TX_INTR_COAL);
1041	coal_conf->tx_coal_type = NO_COALESCE;
1042	}
1043
1044	} else if ((tx_pkt_size >= 128) && (tx_pkt_size < 512)) {
1045
1046	if (coal_conf->tx_coal_type != LOW_COALESCE) {
1047	coal_conf->tx_timeout = 1;
1048	coal_conf->tx_event_count = 2;
1049	amd8111e_set_coalesce(dev, cmod: TX_INTR_COAL);
1050	coal_conf->tx_coal_type = LOW_COALESCE;
1051
1052	}
1053	} else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)) {
1054
1055	if (coal_conf->tx_coal_type != MEDIUM_COALESCE) {
1056	coal_conf->tx_timeout = 2;
1057	coal_conf->tx_event_count = 5;
1058	amd8111e_set_coalesce(dev, cmod: TX_INTR_COAL);
1059	coal_conf->tx_coal_type = MEDIUM_COALESCE;
1060	}
1061	} else if (tx_pkt_size >= 1024) {
1062	if (coal_conf->tx_coal_type != HIGH_COALESCE) {
1063	coal_conf->tx_timeout = 4;
1064	coal_conf->tx_event_count = 8;
1065	amd8111e_set_coalesce(dev, cmod: TX_INTR_COAL);
1066	coal_conf->tx_coal_type = HIGH_COALESCE;
1067	}
1068	}
1069	}
1070	return 0;
1071
1072	}
1073
1074	/* This is device interrupt function. It handles transmit,
1075	* receive,link change and hardware timer interrupts.
1076	*/
1077	static irqreturn_t amd8111e_interrupt(int irq, void *dev_id)
1078	{
1079
1080	struct net_device *dev = (struct net_device *)dev_id;
1081	struct amd8111e_priv *lp = netdev_priv(dev);
1082	void __iomem *mmio = lp->mmio;
1083	unsigned int intr0, intren0;
1084	unsigned int handled = 1;
1085
1086	if (unlikely(!dev))
1087	return IRQ_NONE;
1088
1089	spin_lock(lock: &lp->lock);
1090
1091	/* disabling interrupt */
1092	writel(val: INTREN, addr: mmio + CMD0);
1093
1094	/* Read interrupt status */
1095	intr0 = readl(addr: mmio + INT0);
1096	intren0 = readl(addr: mmio + INTEN0);
1097
1098	/* Process all the INT event until INTR bit is clear. */
1099
1100	if (!(intr0 & INTR)) {
1101	handled = 0;
1102	goto err_no_interrupt;
1103	}
1104
1105	/* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */
1106	writel(val: intr0, addr: mmio + INT0);
1107
1108	/* Check if Receive Interrupt has occurred. */
1109	if (intr0 & RINT0) {
1110	if (napi_schedule_prep(n: &lp->napi)) {
1111	/* Disable receive interrupts */
1112	writel(val: RINTEN0, addr: mmio + INTEN0);
1113	/* Schedule a polling routine */
1114	__napi_schedule(n: &lp->napi);
1115	} else if (intren0 & RINTEN0) {
1116	netdev_dbg(dev, "************Driver bug! interrupt while in poll\n");
1117	/* Fix by disable receive interrupts */
1118	writel(val: RINTEN0, addr: mmio + INTEN0);
1119	}
1120	}
1121
1122	/* Check if Transmit Interrupt has occurred. */
1123	if (intr0 & TINT0)
1124	amd8111e_tx(dev);
1125
1126	/* Check if Link Change Interrupt has occurred. */
1127	if (intr0 & LCINT)
1128	amd8111e_link_change(dev);
1129
1130	/* Check if Hardware Timer Interrupt has occurred. */
1131	if (intr0 & STINT)
1132	amd8111e_calc_coalesce(dev);
1133
1134	err_no_interrupt:
1135	writel(val: VAL0 | INTREN, addr: mmio + CMD0);
1136
1137	spin_unlock(lock: &lp->lock);
1138
1139	return IRQ_RETVAL(handled);
1140	}
1141
1142	#ifdef CONFIG_NET_POLL_CONTROLLER
1143	static void amd8111e_poll(struct net_device *dev)
1144	{
1145	unsigned long flags;
1146	local_irq_save(flags);
1147	amd8111e_interrupt(irq: 0, dev_id: dev);
1148	local_irq_restore(flags);
1149	}
1150	#endif
1151
1152
1153	/* This function closes the network interface and updates
1154	* the statistics so that most recent statistics will be
1155	* available after the interface is down.
1156	*/
1157	static int amd8111e_close(struct net_device *dev)
1158	{
1159	struct amd8111e_priv *lp = netdev_priv(dev);
1160	netif_stop_queue(dev);
1161
1162	napi_disable(n: &lp->napi);
1163
1164	spin_lock_irq(lock: &lp->lock);
1165
1166	amd8111e_disable_interrupt(lp);
1167	amd8111e_stop_chip(lp);
1168
1169	/* Free transmit and receive skbs */
1170	amd8111e_free_skbs(dev: lp->amd8111e_net_dev);
1171
1172	netif_carrier_off(dev: lp->amd8111e_net_dev);
1173
1174	/* Delete ipg timer */
1175	if (lp->options & OPTION_DYN_IPG_ENABLE)
1176	del_timer_sync(timer: &lp->ipg_data.ipg_timer);
1177
1178	spin_unlock_irq(lock: &lp->lock);
1179	free_irq(dev->irq, dev);
1180	amd8111e_free_ring(lp);
1181
1182	/* Update the statistics before closing */
1183	amd8111e_get_stats(dev);
1184	lp->opened = 0;
1185	return 0;
1186	}
1187
1188	/* This function opens new interface.It requests irq for the device,
1189	* initializes the device,buffers and descriptors, and starts the device.
1190	*/
1191	static int amd8111e_open(struct net_device *dev)
1192	{
1193	struct amd8111e_priv *lp = netdev_priv(dev);
1194
1195	if (dev->irq == 0 || request_irq(irq: dev->irq, handler: amd8111e_interrupt,
1196	IRQF_SHARED, name: dev->name, dev))
1197	return -EAGAIN;
1198
1199	napi_enable(n: &lp->napi);
1200
1201	spin_lock_irq(lock: &lp->lock);
1202
1203	amd8111e_init_hw_default(lp);
1204
1205	if (amd8111e_restart(dev)) {
1206	spin_unlock_irq(lock: &lp->lock);
1207	napi_disable(n: &lp->napi);
1208	if (dev->irq)
1209	free_irq(dev->irq, dev);
1210	return -ENOMEM;
1211	}
1212	/* Start ipg timer */
1213	if (lp->options & OPTION_DYN_IPG_ENABLE) {
1214	add_timer(timer: &lp->ipg_data.ipg_timer);
1215	netdev_info(dev, format: "Dynamic IPG Enabled\n");
1216	}
1217
1218	lp->opened = 1;
1219
1220	spin_unlock_irq(lock: &lp->lock);
1221
1222	netif_start_queue(dev);
1223
1224	return 0;
1225	}
1226
1227	/* This function checks if there is any transmit descriptors
1228	* available to queue more packet.
1229	*/
1230	static int amd8111e_tx_queue_avail(struct amd8111e_priv *lp)
1231	{
1232	int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
1233	if (lp->tx_skbuff[tx_index])
1234	return -1;
1235	else
1236	return 0;
1237
1238	}
1239
1240	/* This function will queue the transmit packets to the
1241	* descriptors and will trigger the send operation. It also
1242	* initializes the transmit descriptors with buffer physical address,
1243	* byte count, ownership to hardware etc.
1244	*/
1245	static netdev_tx_t amd8111e_start_xmit(struct sk_buff *skb,
1246	struct net_device *dev)
1247	{
1248	struct amd8111e_priv *lp = netdev_priv(dev);
1249	int tx_index;
1250	unsigned long flags;
1251
1252	spin_lock_irqsave(&lp->lock, flags);
1253
1254	tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1255
1256	lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1257
1258	lp->tx_skbuff[tx_index] = skb;
1259	lp->tx_ring[tx_index].tx_flags = 0;
1260
1261	#if AMD8111E_VLAN_TAG_USED
1262	if (skb_vlan_tag_present(skb)) {
1263	lp->tx_ring[tx_index].tag_ctrl_cmd |=
1264	cpu_to_le16(TCC_VLAN_INSERT);
1265	lp->tx_ring[tx_index].tag_ctrl_info =
1266	cpu_to_le16(skb_vlan_tag_get(skb));
1267
1268	}
1269	#endif
1270	lp->tx_dma_addr[tx_index] =
1271	dma_map_single(&lp->pci_dev->dev, skb->data, skb->len,
1272	DMA_TO_DEVICE);
1273	lp->tx_ring[tx_index].buff_phy_addr =
1274	cpu_to_le32(lp->tx_dma_addr[tx_index]);
1275
1276	/* Set FCS and LTINT bits */
1277	wmb();
1278	lp->tx_ring[tx_index].tx_flags |=
1279	cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
1280
1281	lp->tx_idx++;
1282
1283	/* Trigger an immediate send poll. */
1284	writel(val: VAL1 | TDMD0, addr: lp->mmio + CMD0);
1285	writel(val: VAL2 | RDMD0, addr: lp->mmio + CMD0);
1286
1287	if (amd8111e_tx_queue_avail(lp) < 0) {
1288	netif_stop_queue(dev);
1289	}
1290	spin_unlock_irqrestore(lock: &lp->lock, flags);
1291	return NETDEV_TX_OK;
1292	}
1293	/* This function returns all the memory mapped registers of the device. */
1294	static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1295	{
1296	void __iomem *mmio = lp->mmio;
1297	/* Read only necessary registers */
1298	buf[0] = readl(addr: mmio + XMT_RING_BASE_ADDR0);
1299	buf[1] = readl(addr: mmio + XMT_RING_LEN0);
1300	buf[2] = readl(addr: mmio + RCV_RING_BASE_ADDR0);
1301	buf[3] = readl(addr: mmio + RCV_RING_LEN0);
1302	buf[4] = readl(addr: mmio + CMD0);
1303	buf[5] = readl(addr: mmio + CMD2);
1304	buf[6] = readl(addr: mmio + CMD3);
1305	buf[7] = readl(addr: mmio + CMD7);
1306	buf[8] = readl(addr: mmio + INT0);
1307	buf[9] = readl(addr: mmio + INTEN0);
1308	buf[10] = readl(addr: mmio + LADRF);
1309	buf[11] = readl(addr: mmio + LADRF+4);
1310	buf[12] = readl(addr: mmio + STAT0);
1311	}
1312
1313
1314	/* This function sets promiscuos mode, all-multi mode or the multicast address
1315	* list to the device.
1316	*/
1317	static void amd8111e_set_multicast_list(struct net_device *dev)
1318	{
1319	struct netdev_hw_addr *ha;
1320	struct amd8111e_priv *lp = netdev_priv(dev);
1321	u32 mc_filter[2];
1322	int bit_num;
1323
1324	if (dev->flags & IFF_PROMISC) {
1325	writel(val: VAL2 | PROM, addr: lp->mmio + CMD2);
1326	return;
1327	}
1328	else
1329	writel(val: PROM, addr: lp->mmio + CMD2);
1330	if (dev->flags & IFF_ALLMULTI ||
1331	netdev_mc_count(dev) > MAX_FILTER_SIZE) {
1332	/* get all multicast packet */
1333	mc_filter[1] = mc_filter[0] = 0xffffffff;
1334	lp->options |= OPTION_MULTICAST_ENABLE;
1335	amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1336	return;
1337	}
1338	if (netdev_mc_empty(dev)) {
1339	/* get only own packets */
1340	mc_filter[1] = mc_filter[0] = 0;
1341	lp->options &= ~OPTION_MULTICAST_ENABLE;
1342	amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1343	/* disable promiscuous mode */
1344	writel(val: PROM, addr: lp->mmio + CMD2);
1345	return;
1346	}
1347	/* load all the multicast addresses in the logic filter */
1348	lp->options |= OPTION_MULTICAST_ENABLE;
1349	mc_filter[1] = mc_filter[0] = 0;
1350	netdev_for_each_mc_addr(ha, dev) {
1351	bit_num = (ether_crc_le(ETH_ALEN, ha->addr) >> 26) & 0x3f;
1352	mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
1353	}
1354	amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1355
1356	/* To eliminate PCI posting bug */
1357	readl(addr: lp->mmio + CMD2);
1358
1359	}
1360
1361	static void amd8111e_get_drvinfo(struct net_device *dev,
1362	struct ethtool_drvinfo *info)
1363	{
1364	struct amd8111e_priv *lp = netdev_priv(dev);
1365	struct pci_dev *pci_dev = lp->pci_dev;
1366	strscpy(p: info->driver, MODULE_NAME, size: sizeof(info->driver));
1367	snprintf(buf: info->fw_version, size: sizeof(info->fw_version),
1368	fmt: "%u", chip_version);
1369	strscpy(p: info->bus_info, q: pci_name(pdev: pci_dev), size: sizeof(info->bus_info));
1370	}
1371
1372	static int amd8111e_get_regs_len(struct net_device *dev)
1373	{
1374	return AMD8111E_REG_DUMP_LEN;
1375	}
1376
1377	static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1378	{
1379	struct amd8111e_priv *lp = netdev_priv(dev);
1380	regs->version = 0;
1381	amd8111e_read_regs(lp, buf);
1382	}
1383
1384	static int amd8111e_get_link_ksettings(struct net_device *dev,
1385	struct ethtool_link_ksettings *cmd)
1386	{
1387	struct amd8111e_priv *lp = netdev_priv(dev);
1388	spin_lock_irq(lock: &lp->lock);
1389	mii_ethtool_get_link_ksettings(mii: &lp->mii_if, cmd);
1390	spin_unlock_irq(lock: &lp->lock);
1391	return 0;
1392	}
1393
1394	static int amd8111e_set_link_ksettings(struct net_device *dev,
1395	const struct ethtool_link_ksettings *cmd)
1396	{
1397	struct amd8111e_priv *lp = netdev_priv(dev);
1398	int res;
1399	spin_lock_irq(lock: &lp->lock);
1400	res = mii_ethtool_set_link_ksettings(mii: &lp->mii_if, cmd);
1401	spin_unlock_irq(lock: &lp->lock);
1402	return res;
1403	}
1404
1405	static int amd8111e_nway_reset(struct net_device *dev)
1406	{
1407	struct amd8111e_priv *lp = netdev_priv(dev);
1408	return mii_nway_restart(mii: &lp->mii_if);
1409	}
1410
1411	static u32 amd8111e_get_link(struct net_device *dev)
1412	{
1413	struct amd8111e_priv *lp = netdev_priv(dev);
1414	return mii_link_ok(mii: &lp->mii_if);
1415	}
1416
1417	static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1418	{
1419	struct amd8111e_priv *lp = netdev_priv(dev);
1420	wol_info->supported = WAKE_MAGIC|WAKE_PHY;
1421	if (lp->options & OPTION_WOL_ENABLE)
1422	wol_info->wolopts = WAKE_MAGIC;
1423	}
1424
1425	static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1426	{
1427	struct amd8111e_priv *lp = netdev_priv(dev);
1428	if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY))
1429	return -EINVAL;
1430	spin_lock_irq(lock: &lp->lock);
1431	if (wol_info->wolopts & WAKE_MAGIC)
1432	lp->options |=
1433	(OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE);
1434	else if (wol_info->wolopts & WAKE_PHY)
1435	lp->options |=
1436	(OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE);
1437	else
1438	lp->options &= ~OPTION_WOL_ENABLE;
1439	spin_unlock_irq(lock: &lp->lock);
1440	return 0;
1441	}
1442
1443	static const struct ethtool_ops ops = {
1444	.get_drvinfo = amd8111e_get_drvinfo,
1445	.get_regs_len = amd8111e_get_regs_len,
1446	.get_regs = amd8111e_get_regs,
1447	.nway_reset = amd8111e_nway_reset,
1448	.get_link = amd8111e_get_link,
1449	.get_wol = amd8111e_get_wol,
1450	.set_wol = amd8111e_set_wol,
1451	.get_link_ksettings = amd8111e_get_link_ksettings,
1452	.set_link_ksettings = amd8111e_set_link_ksettings,
1453	};
1454
1455	/* This function handles all the ethtool ioctls. It gives driver info,
1456	* gets/sets driver speed, gets memory mapped register values, forces
1457	* auto negotiation, sets/gets WOL options for ethtool application.
1458	*/
1459	static int amd8111e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1460	{
1461	struct mii_ioctl_data *data = if_mii(rq: ifr);
1462	struct amd8111e_priv *lp = netdev_priv(dev);
1463	int err;
1464	u32 mii_regval;
1465
1466	switch (cmd) {
1467	case SIOCGMIIPHY:
1468	data->phy_id = lp->ext_phy_addr;
1469
1470	fallthrough;
1471	case SIOCGMIIREG:
1472
1473	spin_lock_irq(lock: &lp->lock);
1474	err = amd8111e_read_phy(lp, phy_id: data->phy_id,
1475	reg: data->reg_num & PHY_REG_ADDR_MASK, val: &mii_regval);
1476	spin_unlock_irq(lock: &lp->lock);
1477
1478	data->val_out = mii_regval;
1479	return err;
1480
1481	case SIOCSMIIREG:
1482
1483	spin_lock_irq(lock: &lp->lock);
1484	err = amd8111e_write_phy(lp, phy_id: data->phy_id,
1485	reg: data->reg_num & PHY_REG_ADDR_MASK, val: data->val_in);
1486	spin_unlock_irq(lock: &lp->lock);
1487
1488	return err;
1489
1490	default:
1491	/* do nothing */
1492	break;
1493	}
1494	return -EOPNOTSUPP;
1495	}
1496	static int amd8111e_set_mac_address(struct net_device *dev, void *p)
1497	{
1498	struct amd8111e_priv *lp = netdev_priv(dev);
1499	int i;
1500	struct sockaddr *addr = p;
1501
1502	eth_hw_addr_set(dev, addr: addr->sa_data);
1503	spin_lock_irq(lock: &lp->lock);
1504	/* Setting the MAC address to the device */
1505	for (i = 0; i < ETH_ALEN; i++)
1506	writeb(val: dev->dev_addr[i], addr: lp->mmio + PADR + i);
1507
1508	spin_unlock_irq(lock: &lp->lock);
1509
1510	return 0;
1511	}
1512
1513	/* This function changes the mtu of the device. It restarts the device to
1514	* initialize the descriptor with new receive buffers.
1515	*/
1516	static int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
1517	{
1518	struct amd8111e_priv *lp = netdev_priv(dev);
1519	int err;
1520
1521	if (!netif_running(dev)) {
1522	/* new_mtu will be used
1523	* when device starts netxt time
1524	*/
1525	dev->mtu = new_mtu;
1526	return 0;
1527	}
1528
1529	spin_lock_irq(lock: &lp->lock);
1530
1531	/* stop the chip */
1532	writel(val: RUN, addr: lp->mmio + CMD0);
1533
1534	dev->mtu = new_mtu;
1535
1536	err = amd8111e_restart(dev);
1537	spin_unlock_irq(lock: &lp->lock);
1538	if (!err)
1539	netif_start_queue(dev);
1540	return err;
1541	}
1542
1543	static int amd8111e_enable_magicpkt(struct amd8111e_priv *lp)
1544	{
1545	writel(val: VAL1 | MPPLBA, addr: lp->mmio + CMD3);
1546	writel(val: VAL0 | MPEN_SW, addr: lp->mmio + CMD7);
1547
1548	/* To eliminate PCI posting bug */
1549	readl(addr: lp->mmio + CMD7);
1550	return 0;
1551	}
1552
1553	static int amd8111e_enable_link_change(struct amd8111e_priv *lp)
1554	{
1555
1556	/* Adapter is already stopped/suspended/interrupt-disabled */
1557	writel(val: VAL0 | LCMODE_SW, addr: lp->mmio + CMD7);
1558
1559	/* To eliminate PCI posting bug */
1560	readl(addr: lp->mmio + CMD7);
1561	return 0;
1562	}
1563
1564	/* This function is called when a packet transmission fails to complete
1565	* within a reasonable period, on the assumption that an interrupt have
1566	* failed or the interface is locked up. This function will reinitialize
1567	* the hardware.
1568	*/
1569	static void amd8111e_tx_timeout(struct net_device *dev, unsigned int txqueue)
1570	{
1571	struct amd8111e_priv *lp = netdev_priv(dev);
1572	int err;
1573
1574	netdev_err(dev, format: "transmit timed out, resetting\n");
1575
1576	spin_lock_irq(lock: &lp->lock);
1577	err = amd8111e_restart(dev);
1578	spin_unlock_irq(lock: &lp->lock);
1579	if (!err)
1580	netif_wake_queue(dev);
1581	}
1582
1583	static int __maybe_unused amd8111e_suspend(struct device *dev_d)
1584	{
1585	struct net_device *dev = dev_get_drvdata(dev: dev_d);
1586	struct amd8111e_priv *lp = netdev_priv(dev);
1587
1588	if (!netif_running(dev))
1589	return 0;
1590
1591	/* disable the interrupt */
1592	spin_lock_irq(lock: &lp->lock);
1593	amd8111e_disable_interrupt(lp);
1594	spin_unlock_irq(lock: &lp->lock);
1595
1596	netif_device_detach(dev);
1597
1598	/* stop chip */
1599	spin_lock_irq(lock: &lp->lock);
1600	if (lp->options & OPTION_DYN_IPG_ENABLE)
1601	del_timer_sync(timer: &lp->ipg_data.ipg_timer);
1602	amd8111e_stop_chip(lp);
1603	spin_unlock_irq(lock: &lp->lock);
1604
1605	if (lp->options & OPTION_WOL_ENABLE) {
1606	/* enable wol */
1607	if (lp->options & OPTION_WAKE_MAGIC_ENABLE)
1608	amd8111e_enable_magicpkt(lp);
1609	if (lp->options & OPTION_WAKE_PHY_ENABLE)
1610	amd8111e_enable_link_change(lp);
1611
1612	device_set_wakeup_enable(dev: dev_d, enable: 1);
1613
1614	} else {
1615	device_set_wakeup_enable(dev: dev_d, enable: 0);
1616	}
1617
1618	return 0;
1619	}
1620
1621	static int __maybe_unused amd8111e_resume(struct device *dev_d)
1622	{
1623	struct net_device *dev = dev_get_drvdata(dev: dev_d);
1624	struct amd8111e_priv *lp = netdev_priv(dev);
1625
1626	if (!netif_running(dev))
1627	return 0;
1628
1629	netif_device_attach(dev);
1630
1631	spin_lock_irq(lock: &lp->lock);
1632	amd8111e_restart(dev);
1633	/* Restart ipg timer */
1634	if (lp->options & OPTION_DYN_IPG_ENABLE)
1635	mod_timer(timer: &lp->ipg_data.ipg_timer,
1636	expires: jiffies + IPG_CONVERGE_JIFFIES);
1637	spin_unlock_irq(lock: &lp->lock);
1638
1639	return 0;
1640	}
1641
1642	static void amd8111e_config_ipg(struct timer_list *t)
1643	{
1644	struct amd8111e_priv *lp = from_timer(lp, t, ipg_data.ipg_timer);
1645	struct ipg_info *ipg_data = &lp->ipg_data;
1646	void __iomem *mmio = lp->mmio;
1647	unsigned int prev_col_cnt = ipg_data->col_cnt;
1648	unsigned int total_col_cnt;
1649	unsigned int tmp_ipg;
1650
1651	if (lp->link_config.duplex == DUPLEX_FULL) {
1652	ipg_data->ipg = DEFAULT_IPG;
1653	return;
1654	}
1655
1656	if (ipg_data->ipg_state == SSTATE) {
1657
1658	if (ipg_data->timer_tick == IPG_STABLE_TIME) {
1659
1660	ipg_data->timer_tick = 0;
1661	ipg_data->ipg = MIN_IPG - IPG_STEP;
1662	ipg_data->current_ipg = MIN_IPG;
1663	ipg_data->diff_col_cnt = 0xFFFFFFFF;
1664	ipg_data->ipg_state = CSTATE;
1665	}
1666	else
1667	ipg_data->timer_tick++;
1668	}
1669
1670	if (ipg_data->ipg_state == CSTATE) {
1671
1672	/* Get the current collision count */
1673
1674	total_col_cnt = ipg_data->col_cnt =
1675	amd8111e_read_mib(mmio, xmt_collisions);
1676
1677	if ((total_col_cnt - prev_col_cnt) <
1678	(ipg_data->diff_col_cnt)) {
1679
1680	ipg_data->diff_col_cnt =
1681	total_col_cnt - prev_col_cnt;
1682
1683	ipg_data->ipg = ipg_data->current_ipg;
1684	}
1685
1686	ipg_data->current_ipg += IPG_STEP;
1687
1688	if (ipg_data->current_ipg <= MAX_IPG)
1689	tmp_ipg = ipg_data->current_ipg;
1690	else {
1691	tmp_ipg = ipg_data->ipg;
1692	ipg_data->ipg_state = SSTATE;
1693	}
1694	writew(val: (u32)tmp_ipg, addr: mmio + IPG);
1695	writew(val: (u32)(tmp_ipg - IFS1_DELTA), addr: mmio + IFS1);
1696	}
1697	mod_timer(timer: &lp->ipg_data.ipg_timer, expires: jiffies + IPG_CONVERGE_JIFFIES);
1698	return;
1699
1700	}
1701
1702	static void amd8111e_probe_ext_phy(struct net_device *dev)
1703	{
1704	struct amd8111e_priv *lp = netdev_priv(dev);
1705	int i;
1706
1707	for (i = 0x1e; i >= 0; i--) {
1708	u32 id1, id2;
1709
1710	if (amd8111e_read_phy(lp, phy_id: i, MII_PHYSID1, val: &id1))
1711	continue;
1712	if (amd8111e_read_phy(lp, phy_id: i, MII_PHYSID2, val: &id2))
1713	continue;
1714	lp->ext_phy_id = (id1 << 16) | id2;
1715	lp->ext_phy_addr = i;
1716	return;
1717	}
1718	lp->ext_phy_id = 0;
1719	lp->ext_phy_addr = 1;
1720	}
1721
1722	static const struct net_device_ops amd8111e_netdev_ops = {
1723	.ndo_open = amd8111e_open,
1724	.ndo_stop = amd8111e_close,
1725	.ndo_start_xmit = amd8111e_start_xmit,
1726	.ndo_tx_timeout = amd8111e_tx_timeout,
1727	.ndo_get_stats = amd8111e_get_stats,
1728	.ndo_set_rx_mode = amd8111e_set_multicast_list,
1729	.ndo_validate_addr = eth_validate_addr,
1730	.ndo_set_mac_address = amd8111e_set_mac_address,
1731	.ndo_eth_ioctl = amd8111e_ioctl,
1732	.ndo_change_mtu = amd8111e_change_mtu,
1733	#ifdef CONFIG_NET_POLL_CONTROLLER
1734	.ndo_poll_controller = amd8111e_poll,
1735	#endif
1736	};
1737
1738	static int amd8111e_probe_one(struct pci_dev *pdev,
1739	const struct pci_device_id *ent)
1740	{
1741	int err, i;
1742	unsigned long reg_addr, reg_len;
1743	struct amd8111e_priv *lp;
1744	struct net_device *dev;
1745	u8 addr[ETH_ALEN];
1746
1747	err = pci_enable_device(dev: pdev);
1748	if (err) {
1749	dev_err(&pdev->dev, "Cannot enable new PCI device\n");
1750	return err;
1751	}
1752
1753	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1754	dev_err(&pdev->dev, "Cannot find PCI base address\n");
1755	err = -ENODEV;
1756	goto err_disable_pdev;
1757	}
1758
1759	err = pci_request_regions(pdev, MODULE_NAME);
1760	if (err) {
1761	dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
1762	goto err_disable_pdev;
1763	}
1764
1765	pci_set_master(dev: pdev);
1766
1767	/* Find power-management capability. */
1768	if (!pdev->pm_cap) {
1769	dev_err(&pdev->dev, "No Power Management capability\n");
1770	err = -ENODEV;
1771	goto err_free_reg;
1772	}
1773
1774	/* Initialize DMA */
1775	if (dma_set_mask(dev: &pdev->dev, DMA_BIT_MASK(32)) < 0) {
1776	dev_err(&pdev->dev, "DMA not supported\n");
1777	err = -ENODEV;
1778	goto err_free_reg;
1779	}
1780
1781	reg_addr = pci_resource_start(pdev, 0);
1782	reg_len = pci_resource_len(pdev, 0);
1783
1784	dev = alloc_etherdev(sizeof(struct amd8111e_priv));
1785	if (!dev) {
1786	err = -ENOMEM;
1787	goto err_free_reg;
1788	}
1789
1790	SET_NETDEV_DEV(dev, &pdev->dev);
1791
1792	#if AMD8111E_VLAN_TAG_USED
1793	dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1794	#endif
1795
1796	lp = netdev_priv(dev);
1797	lp->pci_dev = pdev;
1798	lp->amd8111e_net_dev = dev;
1799	lp->pm_cap = pdev->pm_cap;
1800
1801	spin_lock_init(&lp->lock);
1802
1803	lp->mmio = devm_ioremap(dev: &pdev->dev, offset: reg_addr, size: reg_len);
1804	if (!lp->mmio) {
1805	dev_err(&pdev->dev, "Cannot map device registers\n");
1806	err = -ENOMEM;
1807	goto err_free_dev;
1808	}
1809
1810	/* Initializing MAC address */
1811	for (i = 0; i < ETH_ALEN; i++)
1812	addr[i] = readb(addr: lp->mmio + PADR + i);
1813	eth_hw_addr_set(dev, addr);
1814
1815	/* Setting user defined parametrs */
1816	lp->ext_phy_option = speed_duplex[card_idx];
1817	if (coalesce[card_idx])
1818	lp->options |= OPTION_INTR_COAL_ENABLE;
1819	if (dynamic_ipg[card_idx++])
1820	lp->options |= OPTION_DYN_IPG_ENABLE;
1821
1822
1823	/* Initialize driver entry points */
1824	dev->netdev_ops = &amd8111e_netdev_ops;
1825	dev->ethtool_ops = &ops;
1826	dev->irq = pdev->irq;
1827	dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
1828	dev->min_mtu = AMD8111E_MIN_MTU;
1829	dev->max_mtu = AMD8111E_MAX_MTU;
1830	netif_napi_add_weight(dev, napi: &lp->napi, poll: amd8111e_rx_poll, weight: 32);
1831
1832	/* Probe the external PHY */
1833	amd8111e_probe_ext_phy(dev);
1834
1835	/* setting mii default values */
1836	lp->mii_if.dev = dev;
1837	lp->mii_if.mdio_read = amd8111e_mdio_read;
1838	lp->mii_if.mdio_write = amd8111e_mdio_write;
1839	lp->mii_if.phy_id = lp->ext_phy_addr;
1840
1841	/* Set receive buffer length and set jumbo option*/
1842	amd8111e_set_rx_buff_len(dev);
1843
1844
1845	err = register_netdev(dev);
1846	if (err) {
1847	dev_err(&pdev->dev, "Cannot register net device\n");
1848	goto err_free_dev;
1849	}
1850
1851	pci_set_drvdata(pdev, data: dev);
1852
1853	/* Initialize software ipg timer */
1854	if (lp->options & OPTION_DYN_IPG_ENABLE) {
1855	timer_setup(&lp->ipg_data.ipg_timer, amd8111e_config_ipg, 0);
1856	lp->ipg_data.ipg_timer.expires = jiffies +
1857	IPG_CONVERGE_JIFFIES;
1858	lp->ipg_data.ipg = DEFAULT_IPG;
1859	lp->ipg_data.ipg_state = CSTATE;
1860	}
1861
1862	/* display driver and device information */
1863	chip_version = (readl(addr: lp->mmio + CHIPID) & 0xf0000000) >> 28;
1864	dev_info(&pdev->dev, "[ Rev %x ] PCI 10/100BaseT Ethernet %pM\n",
1865	chip_version, dev->dev_addr);
1866	if (lp->ext_phy_id)
1867	dev_info(&pdev->dev, "Found MII PHY ID 0x%08x at address 0x%02x\n",
1868	lp->ext_phy_id, lp->ext_phy_addr);
1869	else
1870	dev_info(&pdev->dev, "Couldn't detect MII PHY, assuming address 0x01\n");
1871
1872	return 0;
1873
1874	err_free_dev:
1875	free_netdev(dev);
1876
1877	err_free_reg:
1878	pci_release_regions(pdev);
1879
1880	err_disable_pdev:
1881	pci_disable_device(dev: pdev);
1882	return err;
1883
1884	}
1885
1886	static void amd8111e_remove_one(struct pci_dev *pdev)
1887	{
1888	struct net_device *dev = pci_get_drvdata(pdev);
1889
1890	if (dev) {
1891	unregister_netdev(dev);
1892	free_netdev(dev);
1893	pci_release_regions(pdev);
1894	pci_disable_device(dev: pdev);
1895	}
1896	}
1897
1898	static const struct pci_device_id amd8111e_pci_tbl[] = {
1899	{
1900	.vendor = PCI_VENDOR_ID_AMD,
1901	.device = PCI_DEVICE_ID_AMD8111E_7462,
1902	},
1903	{
1904	.vendor = 0,
1905	}
1906	};
1907	MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
1908
1909	static SIMPLE_DEV_PM_OPS(amd8111e_pm_ops, amd8111e_suspend, amd8111e_resume);
1910
1911	static struct pci_driver amd8111e_driver = {
1912	.name = MODULE_NAME,
1913	.id_table = amd8111e_pci_tbl,
1914	.probe = amd8111e_probe_one,
1915	.remove = amd8111e_remove_one,
1916	.driver.pm = &amd8111e_pm_ops
1917	};
1918
1919	module_pci_driver(amd8111e_driver);
1920