1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * |
4 | * Alchemy Au1x00 ethernet driver include file |
5 | * |
6 | * Author: Pete Popov <ppopov@mvista.com> |
7 | * |
8 | * Copyright 2001 MontaVista Software Inc. |
9 | */ |
10 | |
11 | |
12 | #define MAC_IOSIZE 0x10000 |
13 | #define NUM_RX_DMA 4 /* Au1x00 has 4 rx hardware descriptors */ |
14 | #define NUM_TX_DMA 4 /* Au1x00 has 4 tx hardware descriptors */ |
15 | |
16 | #define NUM_RX_BUFFS 4 |
17 | #define NUM_TX_BUFFS 4 |
18 | #define MAX_BUF_SIZE 2048 |
19 | |
20 | #define ETH_TX_TIMEOUT (HZ/4) |
21 | #define MAC_MIN_PKT_SIZE 64 |
22 | |
23 | #define MULTICAST_FILTER_LIMIT 64 |
24 | |
25 | /* |
26 | * Data Buffer Descriptor. Data buffers must be aligned on 32 byte |
27 | * boundary for both, receive and transmit. |
28 | */ |
29 | struct db_dest { |
30 | struct db_dest *pnext; |
31 | u32 *vaddr; |
32 | dma_addr_t dma_addr; |
33 | }; |
34 | |
35 | /* |
36 | * The transmit and receive descriptors are memory |
37 | * mapped registers. |
38 | */ |
39 | struct tx_dma { |
40 | u32 status; |
41 | u32 buff_stat; |
42 | u32 len; |
43 | u32 pad; |
44 | }; |
45 | |
46 | struct rx_dma { |
47 | u32 status; |
48 | u32 buff_stat; |
49 | u32 pad[2]; |
50 | }; |
51 | |
52 | |
53 | /* |
54 | * MAC control registers, memory mapped. |
55 | */ |
56 | struct mac_reg { |
57 | u32 control; |
58 | u32 mac_addr_high; |
59 | u32 mac_addr_low; |
60 | u32 multi_hash_high; |
61 | u32 multi_hash_low; |
62 | u32 mii_control; |
63 | u32 mii_data; |
64 | u32 flow_control; |
65 | u32 vlan1_tag; |
66 | u32 vlan2_tag; |
67 | }; |
68 | |
69 | |
70 | struct au1000_private { |
71 | struct db_dest *pDBfree; |
72 | struct db_dest db[NUM_RX_BUFFS+NUM_TX_BUFFS]; |
73 | struct rx_dma *rx_dma_ring[NUM_RX_DMA]; |
74 | struct tx_dma *tx_dma_ring[NUM_TX_DMA]; |
75 | struct db_dest *rx_db_inuse[NUM_RX_DMA]; |
76 | struct db_dest *tx_db_inuse[NUM_TX_DMA]; |
77 | u32 rx_head; |
78 | u32 tx_head; |
79 | u32 tx_tail; |
80 | u32 tx_full; |
81 | |
82 | int mac_id; |
83 | |
84 | int mac_enabled; /* whether MAC is currently enabled and running |
85 | * (req. for mdio) |
86 | */ |
87 | |
88 | int old_link; /* used by au1000_adjust_link */ |
89 | int old_speed; |
90 | int old_duplex; |
91 | |
92 | struct mii_bus *mii_bus; |
93 | |
94 | /* PHY configuration */ |
95 | int phy_static_config; |
96 | int phy_search_highest_addr; |
97 | int phy1_search_mac0; |
98 | |
99 | int phy_addr; |
100 | int phy_busid; |
101 | int phy_irq; |
102 | |
103 | /* These variables are just for quick access |
104 | * to certain regs addresses. |
105 | */ |
106 | struct mac_reg *mac; /* mac registers */ |
107 | u32 *enable; /* address of MAC Enable Register */ |
108 | void __iomem *macdma; /* base of MAC DMA port */ |
109 | void *vaddr; /* virtual address of rx/tx buffers */ |
110 | dma_addr_t dma_addr; /* dma address of rx/tx buffers */ |
111 | |
112 | spinlock_t lock; /* Serialise access to device */ |
113 | |
114 | u32 msg_enable; |
115 | }; |
116 | |